Merge IOASIC register definitions.
This commit is contained in:
nisimura
parent
25db46c9cf
commit
c6641d91a8
@ -1,4 +1,4 @@
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/* $NetBSD: ioasic.c,v 1.27 1999/11/07 09:14:34 mrg Exp $ */
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/* $NetBSD: ioasic.c,v 1.28 2000/02/03 08:13:45 nisimura Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -68,7 +68,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.27 1999/11/07 09:14:34 mrg Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.28 2000/02/03 08:13:45 nisimura Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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@ -84,7 +84,7 @@ __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.27 1999/11/07 09:14:34 mrg Exp $");
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#endif
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#include <dev/tc/tcvar.h>
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#include <alpha/tc/ioasicreg.h>
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#include <dev/tc/ioasicreg.h>
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#include <dev/tc/ioasicvar.h>
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/* Definition of the driver for autoconfig. */
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@ -1,226 +0,0 @@
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/* $NetBSD: ioasicreg.h,v 1.2 1997/04/06 22:30:28 cgd Exp $ */
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/*
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* Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* The Mach Operating System project at Carnegie-Mellon University,
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)asic.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* Slot definitions
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*/
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#define IOASIC_SLOT_0_START 0x000000
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#define IOASIC_SLOT_1_START 0x040000
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#define IOASIC_SLOT_2_START 0x080000
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#define IOASIC_SLOT_3_START 0x0c0000
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#define IOASIC_SLOT_4_START 0x100000
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#define IOASIC_SLOT_5_START 0x140000
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#define IOASIC_SLOT_6_START 0x180000
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#define IOASIC_SLOT_7_START 0x1c0000
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#define IOASIC_SLOT_8_START 0x200000
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#define IOASIC_SLOT_9_START 0x240000
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#define IOASIC_SLOT_10_START 0x280000
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#define IOASIC_SLOT_11_START 0x2c0000
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#define IOASIC_SLOT_12_START 0x300000
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#define IOASIC_SLOT_13_START 0x340000
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#define IOASIC_SLOT_14_START 0x380000
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#define IOASIC_SLOT_15_START 0x3c0000
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#define IOASIC_SLOTS_END 0x3fffff
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/*
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* Register offsets (slot 1)
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*/
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#define IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000
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#define IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010
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#define IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020
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#define IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030
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#define IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040
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#define IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050
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#define IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060
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#define IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070
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#define IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080
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#define IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090
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#define IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0
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#define IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0
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#define IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0
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#define IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0
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#define IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0
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#define IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0
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#define IOASIC_CSR IOASIC_SLOT_1_START+0x100
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#define IOASIC_INTR IOASIC_SLOT_1_START+0x110
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#define IOASIC_IMSK IOASIC_SLOT_1_START+0x120
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#define IOASIC_CURADDR IOASIC_SLOT_1_START+0x130
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#define IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140
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#define IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150
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#define IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160
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#define IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170
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#define IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180
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#define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190
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#define IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0
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#define IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0
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#define IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0
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#define IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0
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/* System Status and control Register (SSR). */
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#define IOASIC_CSR_DMAEN_T1 0x80000000 /* rw */
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#define IOASIC_CSR_DMAEN_R1 0x40000000 /* rw */
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#define IOASIC_CSR_DMAEN_T2 0x20000000 /* rw */
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#define IOASIC_CSR_DMAEN_R2 0x10000000 /* rw */
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#define IOASIC_CSR_FASTMODE 0x08000000 /* rw */
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#define IOASIC_CSR_xxx 0x07800000 /* unused/reserved */
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#define IOASIC_CSR_FLOPPY_DIR 0x00400000 /* rw */
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#define IOASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw */
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#define IOASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */
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#define IOASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */
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#define IOASIC_CSR_SCSI_DIR 0x00040000 /* rw */
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#define IOASIC_CSR_DMAEN_SCSI 0x00020000 /* rw */
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#define IOASIC_CSR_DMAEN_LANCE 0x00010000 /* rw */
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/* low 16 bits are rw gp outputs */
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/* System Interrupt Register (and Interrupt Mask Register). */
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#define IOASIC_INTR_T1_PAGE_END 0x80000000 /* rz */
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#define IOASIC_INTR_T1_READ_E 0x40000000 /* rz */
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#define IOASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */
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#define IOASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */
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#define IOASIC_INTR_T2_PAGE_END 0x08000000 /* rz */
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#define IOASIC_INTR_T2_READ_E 0x04000000 /* rz */
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#define IOASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */
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#define IOASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */
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#define IOASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz */
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#define IOASIC_INTR_ISDN_PTR_LOAD 0x00400000 /* rz */
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#define IOASIC_INTR_ISDN_OVRUN 0x00200000 /* rz */
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#define IOASIC_INTR_ISDN_READ_E 0x00100000 /* rz */
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#define IOASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz */
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#define IOASIC_INTR_SCSI_OVRUN 0x00040000 /* rz */
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#define IOASIC_INTR_SCSI_READ_E 0x00020000 /* rz */
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#define IOASIC_INTR_LANCE_READ_E 0x00010000 /* rz */
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#define IOASIC_INTR_ISDN 0x00002000 /* ro */
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#define IOASIC_INTR_SEC_CON 0x00000200 /* ro */
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#define IOASIC_INTR_LANCE 0x00000100 /* ro */
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#define IOASIC_INTR_SCC_1 0x00000080 /* ro */
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#define IOASIC_INTR_SCC_0 0x00000040 /* ro */
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#define IOASIC_INTR_ALT_CON 0x00000008 /* ro - 3000/500 */
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#define IOASIC_INTR_300_OPT1 IOASIC_INTR_ALT_CON /* ro - 3000/300 */
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#define IOASIC_INTR_300_OPT0 0x00000004 /* ro - 3000/300 */
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/* DMA pointer registers (SCSI, Comm, ...) */
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#define IOASIC_DMAPTR_MASK 0xffffffe0
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#define IOASIC_DMAPTR_SHIFT 5
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#define IOASIC_DMAPTR_SET(reg,val) \
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(reg) = (((val)<<IOASIC_DMAPTR_SHIFT)&IOASIC_DMAPTR_MASK)
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#define IOASIC_DMAPTR_GET(reg,val) \
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(val) = (((reg)&IOASIC_DMAPTR_MASK)>>IOASIC_DMAPTR_SHIFT)
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#define IOASIC_DMA_ADDR(p) (((unsigned)p) << (5-2))
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/* For the LANCE DMA pointer register initialization the above suffices */
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/* More SCSI DMA registers */
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#define IOASIC_SCR_STATUS 0x00000004
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#define IOASIC_SCR_WORD 0x00000003
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/* Various Decode registers */
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#define IOASIC_DECODE_HW_ADDRESS 0x000003f0
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#define IOASIC_DECODE_CHIP_SELECT 0x0000000f
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/*
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* Asic register addresses at offset from base.
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*/
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#define IOASIC_REG_SCSI_DMAPTR(base) ((base) + IOASIC_SCSI_DMAPTR)
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#define IOASIC_REG_SCSI_DMANPTR(base) ((base) + IOASIC_SCSI_NEXTPTR)
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#define IOASIC_REG_LANCE_DMAPTR(base) ((base) + IOASIC_LANCE_DMAPTR)
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#define IOASIC_REG_SCC_T1_DMAPTR(base) ((base) + IOASIC_SCC_T1_DMAPTR)
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#define IOASIC_REG_SCC_R1_DMAPTR(base) ((base) + IOASIC_SCC_R1_DMAPTR)
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#define IOASIC_REG_SCC_T2_DMAPTR(base) ((base) + IOASIC_SCC_T2_DMAPTR)
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#define IOASIC_REG_SCC_R2_DMAPTR(base) ((base) + IOASIC_SCC_R2_DMAPTR)
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#define IOASIC_REG_FLOPPY_DMAPTR(base) ((base) + IOASIC_FLOPPY_DMAPTR)
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#define IOASIC_REG_ISDN_X_DMAPTR(base) ((base) + IOASIC_ISDN_X_DMAPTR)
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#define IOASIC_REG_ISDN_X_NEXTPTR(base) ((base) + IOASIC_ISDN_X_NEXTPTR)
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#define IOASIC_REG_ISDN_R_DMAPTR(base) ((base) + IOASIC_ISDN_R_DMAPTR)
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#define IOASIC_REG_ISDN_R_NEXTPTR(base) ((base) + IOASIC_ISDN_R_NEXTPTR)
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#define IOASIC_REG_BUFF0(base) ((base) + IOASIC_BUFF0)
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#define IOASIC_REG_BUFF1(base) ((base) + IOASIC_BUFF1)
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#define IOASIC_REG_BUFF2(base) ((base) + IOASIC_BUFF2)
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#define IOASIC_REG_BUFF3(base) ((base) + IOASIC_BUFF3)
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#define IOASIC_REG_CSR(base) ((base) + IOASIC_CSR)
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#define IOASIC_REG_INTR(base) ((base) + IOASIC_INTR)
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#define IOASIC_REG_IMSK(base) ((base) + IOASIC_IMSK)
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#define IOASIC_REG_CURADDR(base) ((base) + IOASIC_CURADDR)
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#define IOASIC_REG_ISDN_X_DATA(base) ((base) + IOASIC_ISDN_X_DATA)
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#define IOASIC_REG_ISDN_R_DATA(base) ((base) + IOASIC_ISDN_R_DATA)
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#define IOASIC_REG_LANCE_DECODE(base) ((base) + IOASIC_LANCE_DECODE)
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#define IOASIC_REG_SCSI_DECODE(base) ((base) + IOASIC_SCSI_DECODE)
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#define IOASIC_REG_SCC0_DECODE(base) ((base) + IOASIC_SCC0_DECODE)
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#define IOASIC_REG_SCC1_DECODE(base) ((base) + IOASIC_SCC1_DECODE)
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#define IOASIC_REG_FLOPPY_DECODE(base) ((base) + IOASIC_FLOPPY_DECODE)
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#define IOASIC_REG_SCSI_SCR(base) ((base) + IOASIC_SCSI_SCR)
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#define IOASIC_REG_SCSI_SDR0(base) ((base) + IOASIC_SCSI_SDR0)
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#define IOASIC_REG_SCSI_SDR1(base) ((base) + IOASIC_SCSI_SDR1)
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/*
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* And slot assignments.
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*/
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#define IOASIC_SYS_ETHER_ADDRESS(base) ((base) + IOASIC_SLOT_2_START)
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#define IOASIC_SYS_LANCE(base) ((base) + IOASIC_SLOT_3_START)
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@ -1,4 +1,4 @@
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/* $NetBSD: scc.c,v 1.47 1999/09/17 19:59:37 thorpej Exp $ */
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/* $NetBSD: scc.c,v 1.48 2000/02/03 08:13:45 nisimura Exp $ */
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/*
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* Copyright (c) 1991,1990,1989,1994,1995,1996 Carnegie Mellon University
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@ -64,7 +64,7 @@
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: scc.c,v 1.47 1999/09/17 19:59:37 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: scc.c,v 1.48 2000/02/03 08:13:45 nisimura Exp $");
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#include "opt_ddb.h"
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#ifdef alpha
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@ -111,7 +111,7 @@ __KERNEL_RCSID(0, "$NetBSD: scc.c,v 1.47 1999/09/17 19:59:37 thorpej Exp $");
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#include <machine/conf.h>
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#include <dev/tc/tcvar.h>
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#include <alpha/tc/ioasicreg.h>
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#include <dev/tc/ioasicreg.h>
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#include <dev/tc/ioasicvar.h>
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#ifdef alpha
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@ -1,4 +1,4 @@
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/* $NetBSD: tc_3000_300.c,v 1.20 1999/08/07 12:58:29 drochner Exp $ */
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/* $NetBSD: tc_3000_300.c,v 1.21 2000/02/03 08:13:45 nisimura Exp $ */
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/*
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* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
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@ -29,7 +29,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: tc_3000_300.c,v 1.20 1999/08/07 12:58:29 drochner Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tc_3000_300.c,v 1.21 2000/02/03 08:13:45 nisimura Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -42,9 +42,9 @@ __KERNEL_RCSID(0, "$NetBSD: tc_3000_300.c,v 1.20 1999/08/07 12:58:29 drochner Ex
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#endif
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#include <dev/tc/tcvar.h>
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#include <dev/tc/ioasicreg.h>
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#include <alpha/tc/tc_conf.h>
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#include <alpha/tc/tc_3000_300.h>
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#include <alpha/tc/ioasicreg.h>
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#include "wsdisplay.h"
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#include "sfb.h"
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@ -98,7 +98,7 @@ tc_3000_300_intr_setup()
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/*
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* Disable all interrupts that we can (can't disable builtins).
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*/
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imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR);
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imskp = (volatile u_int32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK);
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*imskp &= ~(IOASIC_INTR_300_OPT0 | IOASIC_INTR_300_OPT1);
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/*
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@ -130,7 +130,7 @@ tc_3000_300_intr_establish(tcadev, cookie, level, func, arg)
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tc_3000_300_intr[dev].tci_func = func;
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tc_3000_300_intr[dev].tci_arg = arg;
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imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR);
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imskp = (volatile u_int32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK);
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switch (dev) {
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case TC_3000_300_DEV_OPT0:
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*imskp |= IOASIC_INTR_300_OPT0;
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@ -160,7 +160,7 @@ tc_3000_300_intr_disestablish(tcadev, cookie)
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panic("tc_3000_300_intr_disestablish: cookie %lu bad intr",
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dev);
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imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR);
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imskp = (volatile u_int32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK);
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switch (dev) {
|
||||
case TC_3000_300_DEV_OPT0:
|
||||
*imskp &= ~IOASIC_INTR_300_OPT0;
|
||||
@ -211,9 +211,9 @@ tc_3000_300_iointr(framep, vec)
|
||||
/* find out what interrupts/errors occurred */
|
||||
tcir = *(volatile u_int32_t *)TC_3000_300_IR;
|
||||
ioasicir = *(volatile u_int32_t *)
|
||||
IOASIC_REG_INTR(DEC_3000_300_IOASIC_ADDR);
|
||||
(DEC_3000_300_IOASIC_ADDR + IOASIC_INTR);
|
||||
ioasicimr = *(volatile u_int32_t *)
|
||||
IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR);
|
||||
(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK);
|
||||
tc_mb();
|
||||
|
||||
/* Ignore interrupts that aren't enabled out. */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: zs_ioasic.c,v 1.7 1999/08/07 12:58:30 drochner Exp $ */
|
||||
/* $NetBSD: zs_ioasic.c,v 1.8 2000/02/03 08:13:45 nisimura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1996, 1998 The NetBSD Foundation, Inc.
|
||||
@ -39,7 +39,7 @@
|
||||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.7 1999/08/07 12:58:30 drochner Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.8 2000/02/03 08:13:45 nisimura Exp $");
|
||||
|
||||
/*
|
||||
* Zilog Z8530 Dual UART driver (machine-dependent part). This driver
|
||||
@ -74,7 +74,7 @@ __KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.7 1999/08/07 12:58:30 drochner Exp $
|
||||
#include <dev/ic/z8530reg.h>
|
||||
|
||||
#include <dev/tc/tcvar.h>
|
||||
#include <alpha/tc/ioasicreg.h>
|
||||
#include <dev/tc/ioasicreg.h>
|
||||
#include <dev/tc/ioasicvar.h>
|
||||
#include <dev/dec/zskbdvar.h>
|
||||
|
||||
@ -402,18 +402,18 @@ zs_ioasic_enable(onoff)
|
||||
{
|
||||
|
||||
if (onoff) {
|
||||
*(volatile u_int *)IOASIC_REG_IMSK(ioasic_base) |=
|
||||
*(volatile u_int *)(ioasic_base + IOASIC_IMSK) |=
|
||||
IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0;
|
||||
#if !defined(DEC_3000_300) && defined(ZS_IOASIC_DMA)
|
||||
*(volatile u_int *)IOASIC_REG_CSR(ioasic_base) |=
|
||||
*(volatile u_int *)(ioasic_base + IOASIC_CSR) |=
|
||||
IOASIC_CSR_DMAEN_T1 | IOASIC_CSR_DMAEN_R1 |
|
||||
IOASIC_CSR_DMAEN_T2 | IOASIC_CSR_DMAEN_R2;
|
||||
#endif
|
||||
} else {
|
||||
*(volatile u_int *)IOASIC_REG_IMSK(ioasic_base) &=
|
||||
*(volatile u_int *)(ioasic_base + IOASIC_IMSK) &=
|
||||
~(IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0);
|
||||
#if !defined(DEC_3000_300) && defined(ZS_IOASIC_DMA)
|
||||
*(volatile u_int *)IOASIC_REG_CSR(ioasic_base) &=
|
||||
*(volatile u_int *)(ioasic_base + IOASIC_CSR) &=
|
||||
~(IOASIC_CSR_DMAEN_T1 | IOASIC_CSR_DMAEN_R1 |
|
||||
IOASIC_CSR_DMAEN_T2 | IOASIC_CSR_DMAEN_R2);
|
||||
#endif
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: dtop.c,v 1.46 2000/02/03 04:09:20 nisimura Exp $ */
|
||||
/* $NetBSD: dtop.c,v 1.47 2000/02/03 08:13:44 nisimura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -94,7 +94,7 @@ SOFTWARE.
|
||||
********************************************************/
|
||||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
__KERNEL_RCSID(0, "$NetBSD: dtop.c,v 1.46 2000/02/03 04:09:20 nisimura Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: dtop.c,v 1.47 2000/02/03 08:13:44 nisimura Exp $");
|
||||
|
||||
#include "rasterconsole.h"
|
||||
|
||||
@ -110,6 +110,7 @@ __KERNEL_RCSID(0, "$NetBSD: dtop.c,v 1.46 2000/02/03 04:09:20 nisimura Exp $");
|
||||
#include <dev/cons.h>
|
||||
#include <dev/dec/lk201.h>
|
||||
#include <dev/tc/tcvar.h>
|
||||
#include <dev/tc/ioasicreg.h>
|
||||
#include <dev/tc/ioasicvar.h>
|
||||
|
||||
#include <machine/conf.h>
|
||||
@ -125,7 +126,6 @@ __KERNEL_RCSID(0, "$NetBSD: dtop.c,v 1.46 2000/02/03 04:09:20 nisimura Exp $");
|
||||
#include <pmax/dev/lk201var.h>
|
||||
#include <pmax/dev/rconsvar.h>
|
||||
|
||||
#include <pmax/pmax/asic.h>
|
||||
#include <pmax/pmax/maxine.h>
|
||||
|
||||
|
||||
|
||||
@ -1,347 +0,0 @@
|
||||
/* $NetBSD: asic.h,v 1.12 1999/08/16 13:10:52 simonb Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Author: Jonathan Stone
|
||||
*
|
||||
* Permission to use, copy, modify and distribute this software and
|
||||
* its documentation is hereby granted, provided that both the copyright
|
||||
* notice and this permission notice appear in all copies of the
|
||||
* software, derivative works or modified versions, and any portions
|
||||
* thereof, and that both notices appear in supporting documentation.
|
||||
*
|
||||
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
|
||||
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
|
||||
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
|
||||
*
|
||||
* Carnegie Mellon requests users of this software to return to
|
||||
*
|
||||
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
|
||||
* School of Computer Science
|
||||
* Carnegie Mellon University
|
||||
* Pittsburgh PA 15213-3890
|
||||
*
|
||||
* any improvements or extensions that they make and grant Carnegie the
|
||||
* rights to redistribute these changes.
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1992, 1993
|
||||
* The Regents of the University of California. All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to Berkeley by
|
||||
* The Mach Operating System project at Carnegie-Mellon University,
|
||||
* Ralph Campbell and Rick Macklem.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
|
||||
* 4. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* @(#)asic.h 8.1 (Berkeley) 6/10/93
|
||||
*/
|
||||
|
||||
#ifndef MIPS_IOASIC_H
|
||||
#define MIPS_IOASIC_H 1
|
||||
|
||||
/*
|
||||
* Slot definitions
|
||||
*
|
||||
* The IOASIC is memory-mapped into a turbochannel slot as the "system"
|
||||
* pseudo-slot pseudo-slot, containing on-the-baseboard devices for
|
||||
* turbochannel Decstations and Alphas. Regardless of the size
|
||||
* of the host turbochannel slots, the IO ASIC provides up to sixteen
|
||||
* fixed-size 256 Kbyte subslots. (or 512 Kbytes on alphas?)
|
||||
*
|
||||
* Slot 0 is always system ROM, with a Turbochannel ROM ident string.
|
||||
* Slot 1 is always the ASIC's own registers.
|
||||
*
|
||||
* Lance ethernet (and dma registers), SCC serial chip, ASC scsi chip
|
||||
* (and DMA registers for all those), and a real-time clock are
|
||||
* present on all IO asic machines. Other slots number vary by machine
|
||||
* (pmax or alpha) and model of machine.
|
||||
*
|
||||
* The Decstation/xx (MAXINE) and all(?) Alphas have an audio/ISDN chip.
|
||||
*
|
||||
* The MAXINE has only one SCC serial chip, but has a DTOP "desktop bus"
|
||||
* device. All other IOASIC machines have two SCCs.
|
||||
*
|
||||
* The MAXINE also a floppy-disk controller, and a free-running
|
||||
* clock with 1-microsecond resolution.
|
||||
*/
|
||||
|
||||
#define IOASIC_SLOT_0_START 0x000000
|
||||
#define IOASIC_SLOT_1_START 0x040000
|
||||
#define IOASIC_SLOT_2_START 0x080000
|
||||
#define IOASIC_SLOT_3_START 0x0c0000
|
||||
#define IOASIC_SLOT_4_START 0x100000
|
||||
#define IOASIC_SLOT_5_START 0x140000
|
||||
#define IOASIC_SLOT_6_START 0x180000
|
||||
#define IOASIC_SLOT_7_START 0x1c0000
|
||||
#define IOASIC_SLOT_8_START 0x200000
|
||||
#define IOASIC_SLOT_9_START 0x240000
|
||||
#define IOASIC_SLOT_10_START 0x280000
|
||||
#define IOASIC_SLOT_11_START 0x2c0000
|
||||
#define IOASIC_SLOT_12_START 0x300000
|
||||
#define IOASIC_SLOT_13_START 0x340000
|
||||
#define IOASIC_SLOT_14_START 0x380000
|
||||
#define IOASIC_SLOT_15_START 0x3c0000
|
||||
#define IOASIC_SLOTS_END 0x3fffff
|
||||
|
||||
/*
|
||||
* IOASIC register offsets (slot 1)
|
||||
*/
|
||||
|
||||
#define IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000
|
||||
#define IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010
|
||||
#define IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020
|
||||
#define IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030
|
||||
#define IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040
|
||||
#define IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050
|
||||
#define IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060
|
||||
#define IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070
|
||||
#define IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080
|
||||
#define IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090
|
||||
#define IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0
|
||||
#define IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0
|
||||
#define IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0
|
||||
#define IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0
|
||||
#define IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0
|
||||
#define IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0
|
||||
#define IOASIC_CSR IOASIC_SLOT_1_START+0x100
|
||||
#define IOASIC_INTR IOASIC_SLOT_1_START+0x110
|
||||
#define IOASIC_IMSK IOASIC_SLOT_1_START+0x120
|
||||
#define IOASIC_CURADDR IOASIC_SLOT_1_START+0x130
|
||||
#define IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140
|
||||
#define IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150
|
||||
#define IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160
|
||||
#define IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170
|
||||
#define IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180
|
||||
#define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190
|
||||
#define IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0
|
||||
#define IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0
|
||||
#define IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0
|
||||
#define IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0
|
||||
#define IOASIC_CTR IOASIC_SLOT_1_START+0x1e0 /*5k/240,alpha only*/
|
||||
|
||||
/*
|
||||
* System Status and Control register (SSR) bit definitions.
|
||||
* (The SSR is the IO ASIC register named ASIC_CSR above).
|
||||
*/
|
||||
|
||||
#define IOASIC_CSR_DMAEN_T1 0x80000000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_R1 0x40000000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_T2 0x20000000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_R2 0x10000000 /* rw */
|
||||
#define IOASIC_CSR_FASTMODE 0x08000000 /* rw */ /*not on pmaxes*/
|
||||
#define IOASIC_CSR_xxx 0x07800000 /* reserved */
|
||||
#define IOASIC_CSR_DS_xxx 0x0f800000 /* reserved */
|
||||
#define IOASIC_CSR_FLOPPY_DIR 0x00400000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */
|
||||
#define IOASIC_CSR_SCSI_DIR 0x00040000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_SCSI 0x00020000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_LANCE 0x00010000 /* rw */
|
||||
|
||||
/*
|
||||
* The low-order 16 bits of SSR are general-purpose bits
|
||||
* with model-dependent meaning.
|
||||
* The following are common on all three IOASIC Decstations,
|
||||
* (except perhaps TXDIS_1 and TXDIS_2 on xine?).
|
||||
* The enable bits appear to be valid on Alphas, also.
|
||||
* XXX CGD -- reorganize to separate out bitfields with
|
||||
* common meaninds on Alpha, pmax?
|
||||
*/
|
||||
#define IOASIC_CSR_DIAGDN 0x00008000 /* rw */ /* (all) */
|
||||
#define IOASIC_CSR_TXDIS_2 0x00004000 /* rw */ /* kmin,kn03 */
|
||||
#define IOASIC_CSR_TXDIS_1 0x00002000 /* rw */ /* kmin,kn03 */
|
||||
#define IOASIC_CSR_SCC_ENABLE 0x00000800 /* rw */ /* (all) */
|
||||
#define IOASIC_CSR_RTC_ENABLE 0x00000400 /* rw */ /* (all) */
|
||||
#define IOASIC_CSR_SCSI_ENABLE 0x00000200 /* rw */ /* (all) */
|
||||
#define IOASIC_CSR_LANCE_ENABLE 0x00000100 /* rw */ /* (all) */
|
||||
|
||||
|
||||
/*
|
||||
* System Interrupt Register (and interrupt mask register).
|
||||
* The defines above call the SIR IOASIC_INTR, and the SIRM is called
|
||||
* IOASIC_IMSK.
|
||||
*/
|
||||
#define IOASIC_INTR_T1_PAGE_END 0x80000000 /* rz */
|
||||
#define IOASIC_INTR_T1_READ_E 0x40000000 /* rz */
|
||||
#define IOASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */
|
||||
#define IOASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */
|
||||
#define IOASIC_INTR_T2_PAGE_END 0x08000000 /* rz */
|
||||
#define IOASIC_INTR_T2_READ_E 0x04000000 /* rz */
|
||||
#define IOASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */
|
||||
#define IOASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */
|
||||
#define IOASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz */
|
||||
#define IOASIC_INTR_ISDN_TXLOAD 0x00400000 /* rz */
|
||||
#define IOASIC_INTR_ISDN_RXLOAD 0x00200000 /* rz */
|
||||
#define IOASIC_INTR_ISDN_OVRUN 0x00100000 /* rz */
|
||||
#define IOASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz */
|
||||
#define IOASIC_INTR_SCSI_OVRUN 0x00040000 /* rz */
|
||||
#define IOASIC_INTR_SCSI_READ_E 0x00020000 /* rz */
|
||||
#define IOASIC_INTR_LANCE_READ_E 0x00010000 /* rz */
|
||||
|
||||
/*
|
||||
* SIR and SIRM low-order bits.
|
||||
|
||||
* The low-order 16 bits of SIR and SIRM are general-purpose bits
|
||||
* with model-dependent meaning.
|
||||
* The following four bits of the SIRM have the same meaning on
|
||||
* all three IOASIC Decstations and apparently on Alphas too.
|
||||
*
|
||||
* the MAXINE (decstation 5000/xx) is weird; see below.
|
||||
*/
|
||||
|
||||
#define IOASIC_INTR_NVR_JUMPER 0x00004000 /* ro */
|
||||
#define IOASIC_INTR_NRMOD_JUMPER 0x00000400 /* ro */
|
||||
#define IOASIC_INTR_SCSI 0x00000200 /* ro */
|
||||
#define IOASIC_INTR_LANCE 0x00000100 /* ro */
|
||||
|
||||
/* The following are valid for both kmin and kn03. */
|
||||
|
||||
#define IOASIC_INTR_SCC_1 0x00000080 /* ro */ /*kmin,kn03*/
|
||||
#define IOASIC_INTR_SCC_0 0x00000040 /* ro */
|
||||
|
||||
#define KMIN_INTR_CLOCK 0x00000020 /* ro */
|
||||
#define KMIN_INTR_PSWARN 0x00000010 /* ro */
|
||||
#define KMIN_INTR_SCSI_FIFO 0x00000004 /* ro */
|
||||
#define KMIN_INTR_PBNC 0x00000002 /* ro */
|
||||
#define KMIN_INTR_PBNO 0x00000001 /* ro */
|
||||
#define KMIN_INTR_ASIC 0xff0f0004
|
||||
|
||||
/* kmin-specific SIR/SIRM definitions */
|
||||
#define KMIN_INTR_TIMEOUT 0x00001000 /* ro */
|
||||
#define KMIN_IM0 0xff0f13f0 /* all good ones enabled */
|
||||
|
||||
|
||||
/* kn03-specific SIR/SIRM definitions */
|
||||
#define KN03_INTR_TC_2 0x00002000 /* ro */
|
||||
#define KN03_INTR_TC_1 0x00001000 /* ro */
|
||||
#define KN03_INTR_TC_0 0x00000800 /* ro */
|
||||
#define KN03_IM0 0xff0f3bf0 /* all good ones enabled */
|
||||
|
||||
/*
|
||||
* SIR/SIRM low-order bit definitions for the MAXINE.
|
||||
* The MAXINE has so many onboard devices that it
|
||||
* has very little in common with the kmin and kn03 --
|
||||
* just the two jumpers and the SCSI and LANCE interrupt bits.
|
||||
* (is the clock-interrupt-enable bit _really_ different)?
|
||||
*/
|
||||
|
||||
#define XINE_INTR_xxxx 0x00002808 /* ro */
|
||||
#define XINE_INTR_FLOPPY 0x00008000 /* ro */
|
||||
/*#define XINE_INTR_NVR_JUMPER 0x00004000 */ /* ro */
|
||||
#define XINE_INTR_POWERUP 0x00002000 /* ro */
|
||||
#define XINE_INTR_TC_0 0x00001000 /* ro */
|
||||
#define XINE_INTR_ISDN 0x00000800 /* ro */
|
||||
/*#define XINE_INTR_NRMOD_JUMPER 0x00000400 */ /* ro */
|
||||
/*#define XINE_INTR_SCSI 0x00000200 */ /* ro */
|
||||
/*#define XINE_INTR_LANCE 0x00000100 */ /* ro */
|
||||
#define XINE_INTR_FLOPPY_HDS 0x00000080 /* ro */
|
||||
#define XINE_INTR_SCC_0 0x00000040 /* ro */
|
||||
#define XINE_INTR_TC_1 0x00000020 /* ro */
|
||||
#define XINE_INTR_FLOPPY_XDS 0x00000010 /* ro */
|
||||
#define XINE_INTR_VINT 0x00000008 /* ro */
|
||||
#define XINE_INTR_N_VINT 0x00000004 /* ro */
|
||||
#define XINE_INTR_DTOP_TX 0x00000002 /* ro */
|
||||
#define XINE_INTR_DTOP_RX 0x00000001 /* ro */
|
||||
#define XINE_INTR_DTOP 0x00000003
|
||||
#define XINE_INTR_ASIC 0xffff0000
|
||||
#define XINE_IM0 0xffff9b6b /* all good ones enabled */
|
||||
|
||||
|
||||
|
||||
|
||||
/* DMA pointer registers (SCSI, Comm, ...) */
|
||||
|
||||
#define IOASIC_DMAPTR_MASK 0xffffffe0
|
||||
#define IOASIC_DMAPTR_SHIFT 5
|
||||
#define IOASIC_DMAPTR_SET(reg,val) \
|
||||
(reg) = (((val)<<IOASIC_DMAPTR_SHIFT)&IOASIC_DMAPTR_MASK)
|
||||
#define IOASIC_DMAPTR_GET(reg,val) \
|
||||
(val) = (((reg)&IOASIC_DMAPTR_MASK)>>IOASIC_DMAPTR_SHIFT)
|
||||
#define IOASIC_DMA_ADDR(p) (((unsigned)p) << (5-2))
|
||||
|
||||
/* For the LANCE DMA pointer register initialization the above suffices */
|
||||
|
||||
/* More SCSI DMA registers */
|
||||
|
||||
#define IOASIC_SCR_STATUS 0x00000004
|
||||
#define IOASIC_SCR_WORD 0x00000003
|
||||
|
||||
/* Various Decode registers */
|
||||
|
||||
#define IOASIC_DECODE_HW_ADDRESS 0x000003f0
|
||||
#define IOASIC_DECODE_CHIP_SELECT 0x0000000f
|
||||
|
||||
/*
|
||||
* The IOASIC is mapped at different addresses on each model, so we
|
||||
* define register addresses as base plus offset.
|
||||
*/
|
||||
#define IOASIC_REG_SCSI_DMAPTR(base) ((base) + IOASIC_SCSI_DMAPTR)
|
||||
#define IOASIC_REG_SCSI_DMANPTR(base) ((base) + IOASIC_SCSI_NEXTPTR)
|
||||
#define IOASIC_REG_LANCE_DMAPTR(base) ((base) + IOASIC_LANCE_DMAPTR)
|
||||
#define IOASIC_REG_SCC_T1_DMAPTR(base) ((base) + IOASIC_SCC_T1_DMAPTR)
|
||||
#define IOASIC_REG_SCC_R1_DMAPTR(base) ((base) + IOASIC_SCC_R1_DMAPTR)
|
||||
#define IOASIC_REG_SCC_T2_DMAPTR(base) ((base) + IOASIC_SCC_T2_DMAPTR)
|
||||
#define IOASIC_REG_SCC_R2_DMAPTR(base) ((base) + IOASIC_SCC_R2_DMAPTR)
|
||||
#define IOASIC_REG_FLOPPY_DMAPTR(base) ((base) + IOASIC_FLOPPY_DMAPTR)
|
||||
#define IOASIC_REG_ISDN_X_DMAPTR(base) ((base) + IOASIC_ISDN_X_DMAPTR)
|
||||
#define IOASIC_REG_ISDN_X_NEXTPTR(base) ((base) + IOASIC_ISDN_X_NEXTPTR)
|
||||
#define IOASIC_REG_ISDN_R_DMAPTR(base) ((base) + IOASIC_ISDN_R_DMAPTR)
|
||||
#define IOASIC_REG_ISDN_R_NEXTPTR(base) ((base) + IOASIC_ISDN_R_NEXTPTR)
|
||||
#define IOASIC_REG_BUFF0(base) ((base) + IOASIC_BUFF0)
|
||||
#define IOASIC_REG_BUFF1(base) ((base) + IOASIC_BUFF1)
|
||||
#define IOASIC_REG_BUFF2(base) ((base) + IOASIC_BUFF2)
|
||||
#define IOASIC_REG_BUFF3(base) ((base) + IOASIC_BUFF3)
|
||||
#define IOASIC_REG_CSR(base) ((base) + IOASIC_CSR)
|
||||
#define IOASIC_REG_INTR(base) ((base) + IOASIC_INTR)
|
||||
#define IOASIC_REG_IMSK(base) ((base) + IOASIC_IMSK)
|
||||
#define IOASIC_REG_CURADDR(base) ((base) + IOASIC_CURADDR)
|
||||
#define IOASIC_REG_ISDN_X_DATA(base) ((base) + IOASIC_ISDN_X_DATA)
|
||||
#define IOASIC_REG_ISDN_R_DATA(base) ((base) + IOASIC_ISDN_R_DATA)
|
||||
#define IOASIC_REG_LANCE_DECODE(base) ((base) + IOASIC_LANCE_DECODE)
|
||||
#define IOASIC_REG_SCSI_DECODE(base) ((base) + IOASIC_SCSI_DECODE)
|
||||
#define IOASIC_REG_SCC0_DECODE(base) ((base) + IOASIC_SCC0_DECODE)
|
||||
#define IOASIC_REG_SCC1_DECODE(base) ((base) + IOASIC_SCC1_DECODE)
|
||||
#define IOASIC_REG_FLOPPY_DECODE(base) ((base) + IOASIC_FLOPPY_DECODE)
|
||||
#define IOASIC_REG_SCSI_SCR(base) ((base) + IOASIC_SCSI_SCR)
|
||||
#define IOASIC_REG_SCSI_SDR0(base) ((base) + IOASIC_SCSI_SDR0)
|
||||
#define IOASIC_REG_SCSI_SDR1(base) ((base) + IOASIC_SCSI_SDR1)
|
||||
#define IOASIC_REG_CTR(base) ((base) + IOASIC_CTR)
|
||||
|
||||
/*
|
||||
* And slot assignments.
|
||||
*/
|
||||
#define IOASIC_SYS_ETHER_ADDRESS(base) ((base) + IOASIC_SLOT_2_START)
|
||||
#define IOASIC_SYS_LANCE(base) ((base) + IOASIC_SLOT_3_START)
|
||||
|
||||
#endif /* MIPS_IOASIC_H */
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: ioasic.c,v 1.9 2000/02/03 05:22:47 nisimura Exp $ */
|
||||
/* $NetBSD: ioasic.c,v 1.10 2000/02/03 08:13:45 nisimura Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
|
||||
@ -28,19 +28,19 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
__KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.9 2000/02/03 05:22:47 nisimura Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.10 2000/02/03 08:13:45 nisimura Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/device.h>
|
||||
|
||||
#include <dev/tc/tcvar.h>
|
||||
#include <dev/tc/ioasicreg.h>
|
||||
#include <dev/tc/ioasicvar.h>
|
||||
|
||||
#include <machine/sysconf.h>
|
||||
|
||||
#include <pmax/pmax/pmaxtype.h>
|
||||
#include <pmax/pmax/asic.h>
|
||||
#include <pmax/pmax/kmin.h>
|
||||
#include <pmax/pmax/maxine.h>
|
||||
#include <pmax/pmax/kn03.h>
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: asc.c,v 1.56 1999/11/15 05:25:57 nisimura Exp $ */
|
||||
/* $NetBSD: asc.c,v 1.57 2000/02/03 08:13:46 nisimura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -146,7 +146,6 @@
|
||||
#include <pmax/dev/scsi.h>
|
||||
#include <pmax/dev/ascreg.h>
|
||||
|
||||
#include <pmax/pmax/asic.h>
|
||||
#include <pmax/pmax/kmin.h>
|
||||
|
||||
|
||||
|
||||
@ -1,12 +1,209 @@
|
||||
/* $NetBSD: ioasicreg.h,v 1.1 1998/05/27 05:30:13 thorpej Exp $ */
|
||||
/* $NetBSD: ioasicreg.h,v 1.2 2000/02/03 08:13:46 nisimura Exp $ */
|
||||
|
||||
/*
|
||||
* XXX This file is just a placeholder until the ioasic register
|
||||
* XXX files can be sanely merged.
|
||||
* Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission to use, copy, modify and distribute this software and
|
||||
* its documentation is hereby granted, provided that both the copyright
|
||||
* notice and this permission notice appear in all copies of the
|
||||
* software, derivative works or modified versions, and any portions
|
||||
* thereof, and that both notices appear in supporting documentation.
|
||||
*
|
||||
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
|
||||
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
|
||||
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
|
||||
*
|
||||
* Carnegie Mellon requests users of this software to return to
|
||||
*
|
||||
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
|
||||
* School of Computer Science
|
||||
* Carnegie Mellon University
|
||||
* Pittsburgh PA 15213-3890
|
||||
*
|
||||
* any improvements or extensions that they make and grant Carnegie the
|
||||
* rights to redistribute these changes.
|
||||
*/
|
||||
|
||||
#ifdef __alpha__
|
||||
#include <alpha/tc/ioasicreg.h>
|
||||
#else
|
||||
#include <pmax/pmax/asic.h>
|
||||
#endif
|
||||
/*-
|
||||
* Copyright (c) 1992, 1993
|
||||
* The Regents of the University of California. All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to Berkeley by
|
||||
* The Mach Operating System project at Carnegie-Mellon University,
|
||||
* Ralph Campbell and Rick Macklem.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
|
||||
* 4. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* @(#)asic.h 8.1 (Berkeley) 6/10/93
|
||||
*/
|
||||
|
||||
/*
|
||||
* Slot definitions
|
||||
*/
|
||||
|
||||
#define IOASIC_SLOT_0_START 0x000000
|
||||
#define IOASIC_SLOT_1_START 0x040000
|
||||
#define IOASIC_SLOT_2_START 0x080000
|
||||
#define IOASIC_SLOT_3_START 0x0c0000
|
||||
#define IOASIC_SLOT_4_START 0x100000
|
||||
#define IOASIC_SLOT_5_START 0x140000
|
||||
#define IOASIC_SLOT_6_START 0x180000
|
||||
#define IOASIC_SLOT_7_START 0x1c0000
|
||||
#define IOASIC_SLOT_8_START 0x200000
|
||||
#define IOASIC_SLOT_9_START 0x240000
|
||||
#define IOASIC_SLOT_10_START 0x280000
|
||||
#define IOASIC_SLOT_11_START 0x2c0000
|
||||
#define IOASIC_SLOT_12_START 0x300000
|
||||
#define IOASIC_SLOT_13_START 0x340000
|
||||
#define IOASIC_SLOT_14_START 0x380000
|
||||
#define IOASIC_SLOT_15_START 0x3c0000
|
||||
#define IOASIC_SLOTS_END 0x3fffff
|
||||
|
||||
/*
|
||||
* Register offsets (slot 1)
|
||||
*/
|
||||
|
||||
#define IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000
|
||||
#define IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010
|
||||
#define IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020
|
||||
#define IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030
|
||||
#define IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040
|
||||
#define IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050
|
||||
#define IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060
|
||||
#define IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070
|
||||
#define IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080
|
||||
#define IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090
|
||||
#define IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0
|
||||
#define IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0
|
||||
#define IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0
|
||||
#define IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0
|
||||
#define IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0
|
||||
#define IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0
|
||||
#define IOASIC_CSR IOASIC_SLOT_1_START+0x100
|
||||
#define IOASIC_INTR IOASIC_SLOT_1_START+0x110
|
||||
#define IOASIC_IMSK IOASIC_SLOT_1_START+0x120
|
||||
#define IOASIC_CURADDR IOASIC_SLOT_1_START+0x130
|
||||
#define IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140
|
||||
#define IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150
|
||||
#define IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160
|
||||
#define IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170
|
||||
#define IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180
|
||||
#define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190
|
||||
#define IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0
|
||||
#define IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0
|
||||
#define IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0
|
||||
#define IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0
|
||||
#define IOASIC_CTR IOASIC_SLOT_1_START+0x1e0 /*3max+/3000*/
|
||||
|
||||
/* System Status and control Register (SSR). */
|
||||
#define IOASIC_CSR_DMAEN_T1 0x80000000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_R1 0x40000000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_T2 0x20000000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_R2 0x10000000 /* rw */
|
||||
#define IOASIC_CSR_FASTMODE 0x08000000 /* rw - 3000 */
|
||||
#define IOASIC_CSR_xxx 0x07800000 /* reserved - 3000 */
|
||||
#define IOASIC_CSR_DS_xxx 0x0f800000 /* reserved - DS */
|
||||
#define IOASIC_CSR_FLOPPY_DIR 0x00400000 /* rw - maxine */
|
||||
#define IOASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw - maxine */
|
||||
#define IOASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */
|
||||
#define IOASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */
|
||||
#define IOASIC_CSR_SCSI_DIR 0x00040000 /* rw - DS */
|
||||
#define IOASIC_CSR_DMAEN_SCSI 0x00020000 /* rw - DS */
|
||||
#define IOASIC_CSR_DMAEN_LANCE 0x00010000 /* rw - DS */
|
||||
/* low 16 bits are rw gp outputs */
|
||||
#define IOASIC_CSR_DIAGDN 0x00008000 /* rw */
|
||||
#define IOASIC_CSR_TXDIS_2 0x00004000 /* rw - 3min,3max+ */
|
||||
#define IOASIC_CSR_TXDIS_1 0x00002000 /* rw - 3min,3max+ */
|
||||
#define IOASIC_CSR_SCC_ENABLE 0x00000800 /* rw */
|
||||
#define IOASIC_CSR_RTC_ENABLE 0x00000400 /* rw */
|
||||
#define IOASIC_CSR_SCSI_ENABLE 0x00000200 /* rw - DS */
|
||||
#define IOASIC_CSR_LANCE_ENABLE 0x00000100 /* rw */
|
||||
|
||||
/* System Interrupt Register (and Interrupt Mask Register). */
|
||||
#define IOASIC_INTR_T1_PAGE_END 0x80000000 /* rz */
|
||||
#define IOASIC_INTR_T1_READ_E 0x40000000 /* rz */
|
||||
#define IOASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */
|
||||
#define IOASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */
|
||||
#define IOASIC_INTR_T2_PAGE_END 0x08000000 /* rz */
|
||||
#define IOASIC_INTR_T2_READ_E 0x04000000 /* rz */
|
||||
#define IOASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */
|
||||
#define IOASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */
|
||||
#define IOASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz - maxine */
|
||||
#define IOASIC_INTR_ISDN_PTR_LOAD 0x00400000 /* rz - 3000 */
|
||||
#define IOASIC_INTR_ISDN_OVRUN 0x00200000 /* rz - 3000 */
|
||||
#define IOASIC_INTR_ISDN_READ_E 0x00100000 /* rz - 3000 */
|
||||
#define IOASIC_INTR_ISDN_DS_TXLOAD 0x00400000 /* rz - maxine */
|
||||
#define IOASIC_INTR_ISDN_DS_RXLOAD 0x00200000 /* rz - maxine */
|
||||
#define IOASIC_INTR_ISDN_DS_OVRUN 0x00100000 /* rz - maxine */
|
||||
#define IOASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz - DS */
|
||||
#define IOASIC_INTR_SCSI_OVRUN 0x00040000 /* rz - DS */
|
||||
#define IOASIC_INTR_SCSI_READ_E 0x00020000 /* rz - DS */
|
||||
#define IOASIC_INTR_LANCE_READ_E 0x00010000 /* rz - DS */
|
||||
|
||||
/* low 16 bits are model-dependent; see also model specific *.h */
|
||||
#define IOASIC_INTR_NVR_JUMPER 0x00004000 /* ro */
|
||||
#define IOASIC_INTR_ISDN 0x00002000 /* ro */
|
||||
#define IOASIC_INTR_NRMOD_JUMPER 0x00000400 /* ro */
|
||||
#define IOASIC_INTR_SEC_CON 0x00000200 /* ro */
|
||||
#define IOASIC_INTR_SCSI 0x00000200 /* ro - DS */
|
||||
#define IOASIC_INTR_LANCE 0x00000100 /* ro */
|
||||
#define IOASIC_INTR_SCC_1 0x00000080 /* ro */
|
||||
#define IOASIC_INTR_SCC_0 0x00000040 /* ro */
|
||||
#define IOASIC_INTR_ALT_CON 0x00000008 /* ro - 3000/500 */
|
||||
#define IOASIC_INTR_300_OPT1 0x00000008 /* ro - 3000/300 */
|
||||
#define IOASIC_INTR_300_OPT0 0x00000004 /* ro - 3000/300 */
|
||||
|
||||
/* DMA pointer registers (SCSI, Comm, ...) */
|
||||
|
||||
#define IOASIC_DMAPTR_MASK 0xffffffe0
|
||||
#define IOASIC_DMAPTR_SHIFT 5
|
||||
#define IOASIC_DMAPTR_SET(reg,val) \
|
||||
(reg) = (((val)<<IOASIC_DMAPTR_SHIFT)&IOASIC_DMAPTR_MASK)
|
||||
#define IOASIC_DMAPTR_GET(reg,val) \
|
||||
(val) = (((reg)&IOASIC_DMAPTR_MASK)>>IOASIC_DMAPTR_SHIFT)
|
||||
#define IOASIC_DMA_ADDR(p) (((unsigned)p) << (5-2))
|
||||
|
||||
/* For the LANCE DMA pointer register initialization the above suffices */
|
||||
|
||||
/* More SCSI DMA registers */
|
||||
|
||||
#define IOASIC_SCR_STATUS 0x00000004
|
||||
#define IOASIC_SCR_WORD 0x00000003
|
||||
|
||||
/* Various Decode registers */
|
||||
|
||||
#define IOASIC_DECODE_HW_ADDRESS 0x000003f0
|
||||
#define IOASIC_DECODE_CHIP_SELECT 0x0000000f
|
||||
|
||||
/*
|
||||
* And slot assignments.
|
||||
*/
|
||||
#define IOASIC_SYS_ETHER_ADDRESS(base) ((base) + IOASIC_SLOT_2_START)
|
||||
#define IOASIC_SYS_LANCE(base) ((base) + IOASIC_SLOT_3_START)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user