The first step to support Intel PXA270.
kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined, CPU is determined run-time.
This commit is contained in:
bsh
parent
c5dfef4764
commit
c61364bf3e
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.c,v 1.71 2005/06/03 15:55:55 rearnsha Exp $ */
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/* $NetBSD: cpufunc.c,v 1.72 2005/07/04 00:42:36 bsh Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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@ -46,7 +46,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.71 2005/06/03 15:55:55 rearnsha Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.72 2005/07/04 00:42:36 bsh Exp $");
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#include "opt_compat_netbsd.h"
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#include "opt_cpuoptions.h"
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@ -745,7 +745,7 @@ struct cpu_functions ixp12x0_cpufuncs = {
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#endif /* CPU_IXP12X0 */
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#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
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defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
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struct cpu_functions xscale_cpufuncs = {
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/* CPU functions */
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@ -801,7 +801,7 @@ struct cpu_functions xscale_cpufuncs = {
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xscale_setup /* cpu setup */
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};
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#endif
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/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
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/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */
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/*
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* Global constants also used by locore.s
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@ -814,7 +814,7 @@ u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
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#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
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defined (CPU_ARM10) || defined (CPU_ARM11) || \
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defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
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defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
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static void get_cachetype_cp15 __P((void));
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/* Additional cache information local to this file. Log2 of some of the
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@ -1209,9 +1209,10 @@ set_cpufuncs()
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return 0;
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}
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#endif /* CPU_XSCALE_80321 */
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#ifdef CPU_XSCALE_PXA2X0
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#ifdef __CPU_XSCALE_PXA2XX
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/* ignore core revision to test PXA2xx CPUs */
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if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA250 ||
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if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X ||
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(cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA250 ||
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(cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA210) {
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cpufuncs = xscale_cpufuncs;
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@ -1228,7 +1229,7 @@ set_cpufuncs()
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return 0;
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}
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#endif /* CPU_XSCALE_PXA2X0 */
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#endif /* __CPU_XSCALE_PXA2XX */
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#ifdef CPU_XSCALE_IXP425
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if (cputype == CPU_ID_IXP425_533 || cputype == CPU_ID_IXP425_400 ||
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cputype == CPU_ID_IXP425_266) {
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@ -1617,7 +1618,7 @@ late_abort_fixup(arg)
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defined(CPU_ARM8) || defined (CPU_ARM9) || defined(CPU_SA110) || \
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defined(CPU_SA1100) || defined(CPU_SA1110) || \
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defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
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defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
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defined(CPU_ARM10) || defined(CPU_ARM11)
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#define IGN 0
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@ -2234,7 +2235,7 @@ ixp12x0_setup(args)
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#endif /* CPU_IXP12X0 */
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#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
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defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
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struct cpu_option xscale_options[] = {
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#ifdef COMPAT_12
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{ "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
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@ -2311,4 +2312,4 @@ xscale_setup(args)
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__asm __volatile("mcr p15, 0, %0, c1, c0, 1"
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: : "r" (auxctl));
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}
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#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
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#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.58 2005/06/03 15:55:55 rearnsha Exp $ */
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/* $NetBSD: cpu.c,v 1.59 2005/07/04 00:42:37 bsh Exp $ */
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/*
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* Copyright (c) 1995 Mark Brinicombe.
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@ -46,7 +46,7 @@
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#include <sys/param.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.58 2005/06/03 15:55:55 rearnsha Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.59 2005/07/04 00:42:37 bsh Exp $");
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#include <sys/systm.h>
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#include <sys/malloc.h>
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@ -245,6 +245,14 @@ static const char * const pxa255_steppings[16] = {
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"rev 12", "rev 13", "rev 14", "rev 15",
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};
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/* Stepping for PXA27x */
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static const char * const pxa27x_steppings[16] = {
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"step A-0", "step A-1", "step B-0", "step B-1",
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"step C-0", "rev 5", "rev 6", "rev 7",
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"rev 8", "rev 9", "rev 10", "rev 11",
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"rev 12", "rev 13", "rev 14", "rev 15",
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};
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static const char * const ixp425_steppings[16] = {
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"step 0", "rev 1", "rev 2", "rev 3",
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"rev 4", "rev 5", "rev 6", "rev 7",
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@ -341,6 +349,8 @@ const struct cpuidtab cpuids[] = {
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{ CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz",
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i80321_steppings },
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{ CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x",
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pxa27x_steppings },
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{ CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250",
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pxa2x0_steppings },
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{ CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210",
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@ -548,7 +558,7 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
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case CPU_CLASS_SA1:
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#endif
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#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
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defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
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case CPU_CLASS_XSCALE:
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#endif
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#ifdef CPU_ARM11
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.153 2005/06/24 15:59:04 scw Exp $ */
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/* $NetBSD: pmap.c,v 1.154 2005/07/04 00:42:37 bsh Exp $ */
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/*
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* Copyright 2003 Wasabi Systems, Inc.
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@ -212,7 +212,7 @@
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#include <machine/param.h>
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#include <arm/arm32/katelib.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.153 2005/06/24 15:59:04 scw Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.154 2005/07/04 00:42:37 bsh Exp $");
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#ifdef PMAP_DEBUG
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@ -4817,7 +4817,7 @@ pmap_pte_init_xscale(void)
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#elif defined(XSCALE_CACHE_WRITE_BACK)
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/* force write back cache mode */
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write_through = 0;
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#elif defined(CPU_XSCALE_PXA2X0)
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#elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270)
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/*
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* Intel PXA2[15]0 processors are known to have a bug in
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* write-back cache on revision 4 and earlier (stepping
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@ -1,4 +1,4 @@
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# $NetBSD: files.arm,v 1.78 2005/06/03 15:55:56 rearnsha Exp $
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# $NetBSD: files.arm,v 1.79 2005/07/04 00:42:37 bsh Exp $
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# temporary define to allow easy moving to ../arch/arm/arm32
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defflag ARM32
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@ -9,7 +9,8 @@ defflag opt_cputypes.h CPU_ARM6 CPU_ARM7 CPU_ARM7TDMI CPU_ARM8
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CPU_ARM9 CPU_ARM10 CPU_ARM11 CPU_SA110
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CPU_SA1100 CPU_SA1110 CPU_IXP12X0
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CPU_XSCALE_80200 CPU_XSCALE_80321
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CPU_XSCALE_PXA2X0 CPU_XSCALE_IXP425
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CPU_XSCALE_PXA250 CPU_XSCALE_PXA270
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CPU_XSCALE_IXP425
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defparam opt_cpuoptions.h XSCALE_CCLKCFG
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defflag opt_cpuoptions.h XSCALE_CACHE_WRITE_THROUGH
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@ -98,7 +99,8 @@ file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9 | cpu_arm10 |
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cpu_xscale_80200 |
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cpu_xscale_80321 |
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cpu_xscale_ixp425 |
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cpu_xscale_pxa2x0
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cpu_xscale_pxa250 |
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cpu_xscale_pxa270
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file arch/arm/arm/cpufunc_asm_armv5.S cpu_arm10 | cpu_arm11
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file arch/arm/arm/cpufunc_asm_sa1.S cpu_sa110 | cpu_sa1100 |
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cpu_sa1110 |
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@ -107,7 +109,8 @@ file arch/arm/arm/cpufunc_asm_sa11x0.S cpu_sa1100 | cpu_sa1110
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file arch/arm/arm/cpufunc_asm_xscale.S cpu_xscale_80200 |
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cpu_xscale_80321 |
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cpu_xscale_ixp425 |
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cpu_xscale_pxa2x0
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cpu_xscale_pxa250 |
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cpu_xscale_pxa270
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file arch/arm/arm/cpufunc_asm_ixp12x0.S cpu_ixp12x0
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file arch/arm/arm/process_machdep.c
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file arch/arm/arm/procfs_machdep.c procfs
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@ -1,4 +1,4 @@
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/* $NetBSD: cpuconf.h,v 1.10 2005/06/03 15:55:56 rearnsha Exp $ */
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/* $NetBSD: cpuconf.h,v 1.11 2005/07/04 00:42:37 bsh Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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@ -42,6 +42,14 @@
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#include "opt_cputypes.h"
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#endif /* _KERNEL_OPT */
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#if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270)
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#define __CPU_XSCALE_PXA2XX
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#endif
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#ifdef CPU_XSCALE_PXA2X0
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#warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270.
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#endif
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/*
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* IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
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* "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
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@ -64,7 +72,7 @@
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defined(CPU_IXP12X0) + \
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defined(CPU_XSCALE_80200) + \
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defined(CPU_XSCALE_80321) + \
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defined(CPU_XSCALE_PXA2X0) + \
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defined(__CPU_XSCALE_PXA2XX) + \
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defined(CPU_XSCALE_IXP425))
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#else
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#define CPU_NTYPES 2
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@ -98,7 +106,7 @@
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#if !defined(_KERNEL_OPT) || \
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(defined(CPU_ARM10) || defined(CPU_XSCALE_80200) || \
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defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_PXA2X0))
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defined(CPU_XSCALE_80321) || defined(__CPU_XSCALE_PXA2XX))
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#define ARM_ARCH_5 1
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#else
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#define ARM_ARCH_5 0
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@ -165,7 +173,7 @@
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#if !defined(_KERNEL_OPT) || \
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(defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
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defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425))
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#define ARM_MMU_XSCALE 1
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#else
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#define ARM_MMU_XSCALE 0
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.h,v 1.33 2005/06/03 15:55:56 rearnsha Exp $ */
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/* $NetBSD: cpufunc.h,v 1.34 2005/07/04 00:42:37 bsh Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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@ -383,7 +383,7 @@ extern unsigned armv5_dcache_index_inc;
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#if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \
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defined(CPU_SA1100) || defined(CPU_SA1110) || \
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defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
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defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
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void armv4_tlb_flushID __P((void));
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void armv4_tlb_flushI __P((void));
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@ -400,7 +400,7 @@ void ixp12x0_setup __P((char *));
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#endif
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#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
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defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
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void xscale_cpwait __P((void));
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void xscale_cpu_sleep __P((int));
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@ -438,7 +438,7 @@ void xscale_cache_flushD_rng __P((vaddr_t, vsize_t));
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void xscale_context_switch __P((void));
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void xscale_setup __P((char *));
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#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
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#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */
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#define tlb_flush cpu_tlb_flushID
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#define setttb cpu_setttb
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@ -1,11 +1,11 @@
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# $NetBSD: files.pxa2x0,v 1.7 2005/04/13 07:42:28 scw Exp $
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# $NetBSD: files.pxa2x0,v 1.8 2005/07/04 00:42:37 bsh Exp $
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#
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# Configuration info for Intel PXA2[51]0 CPU support
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# Configuration info for Intel PXA2[751]0 CPU support
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#
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file arch/arm/arm/softintr.c # Use the generic ARM soft interrupt code.
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# PXA2[51]0's integrated peripherals bus.
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# PXA2[751]0's integrated peripherals bus.
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device pxaip { [addr=-1], [size=0], [intr=-1], [index=-1]} : bus_space_generic
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attach pxaip at mainbus
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file arch/arm/xscale/pxa2x0.c
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@ -59,3 +59,12 @@ defparam opt_pxa2x0_dmac.h PXA2X0_DMAC_DMOVER_CONCURRENCY
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device pxaacu: audiobus, auconv, mulaw, ac97, aurateconv
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attach pxaacu at pxaip
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file arch/arm/xscale/pxa2x0_ac97.c pxaacu
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# PWM controller
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device pwmpxa
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attach pwmpxa at pxaip
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file arch/arm/xscale/pxa2x0_pwm.c pwmpxa
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# OHCI USB controller on PXA270
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attach ohci at pxaip with ohci_pxa
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file arch/arm/xscale/ohci_pxa27x.c ohci_pxa
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@ -1,4 +1,4 @@
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/* $NetBSD: pxa2x0.c,v 1.7 2005/07/03 16:57:44 bsh Exp $ */
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/* $NetBSD: pxa2x0.c,v 1.8 2005/07/04 00:42:37 bsh Exp $ */
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/*
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* Copyright (c) 2002, 2005 Genetec Corporation. All rights reserved.
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@ -94,7 +94,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pxa2x0.c,v 1.7 2005/07/03 16:57:44 bsh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pxa2x0.c,v 1.8 2005/07/04 00:42:37 bsh Exp $");
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#include "pxaintc.h"
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#include "pxagpio.h"
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@ -115,6 +115,7 @@ __KERNEL_RCSID(0, "$NetBSD: pxa2x0.c,v 1.7 2005/07/03 16:57:44 bsh Exp $");
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#include <arm/cpufunc.h>
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#include <arm/mainbus/mainbus.h>
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#include <arm/xscale/pxa2x0cpu.h>
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#include <arm/xscale/pxa2x0reg.h>
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#include <arm/xscale/pxa2x0var.h>
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#include <arm/xscale/xscalereg.h>
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@ -136,6 +137,16 @@ static int pxaip_print(void *, const char *);
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static int pxaip_measure_cpuclock(struct pxaip_softc *);
|
||||
|
||||
#if defined(CPU_XSCALE_PXA250) && defined(CPU_XSCALE_PXA270)
|
||||
# define SUPPORTED_CPU "PXA250 and PXA270"
|
||||
#elif defined(CPU_XSCALE_PXA250)
|
||||
# define SUPPORTED_CPU "PXA250"
|
||||
#elif defined(CPU_XSCALE_PXA270)
|
||||
# define SUPPORTED_CPU "PXA270"
|
||||
#else
|
||||
# define SUPPORTED_CPU "none of PXA2xx"
|
||||
#endif
|
||||
|
||||
/* attach structures */
|
||||
CFATTACH_DECL(pxaip, sizeof(struct pxaip_softc),
|
||||
pxaip_match, pxaip_attach, NULL, NULL);
|
||||
|
|
@ -146,7 +157,24 @@ static int
|
|||
pxaip_match(struct device *parent, struct cfdata *match, void *aux)
|
||||
{
|
||||
|
||||
#if !defined(CPU_XSCALE_PXA270)
|
||||
if (__CPU_IS_PXA270)
|
||||
goto bad_config;
|
||||
#endif
|
||||
|
||||
#if !defined(CPU_XSCALE_PXA250)
|
||||
if (__CPU_IS_PXA250)
|
||||
goto bad_config;
|
||||
#endif
|
||||
|
||||
return 1;
|
||||
|
||||
#if defined(CPU_XSCALE_PXA250) + defined(CPU_XSCALE_PXA270) != 2
|
||||
bad_config:
|
||||
aprint_error("Kernel is configured for %s, but CPU is %s\n",
|
||||
SUPPORTED_CPU, __CPU_IS_PXA270 ? "PXA270" : "PXA250");
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -173,6 +201,11 @@ pxaip_attach(struct device *parent, struct device *self, void *aux)
|
|||
printf("%s: CPU clock = %d.%03d MHz\n", self->dv_xname,
|
||||
cpuclock/1000, cpuclock%1000 );
|
||||
|
||||
aprint_normal("%s: kernel is configured for " SUPPORTED_CPU
|
||||
", cpu type is %s\n",
|
||||
self->dv_xname,
|
||||
__CPU_IS_PXA270 ? "PXA270" : "PXA250");
|
||||
|
||||
/*
|
||||
* Attach critical devices
|
||||
*/
|
||||
|
|
@ -255,7 +288,7 @@ pxaip_print(void *aux, const char *name)
|
|||
}
|
||||
|
||||
static inline uint32_t
|
||||
read_clock_counter(void)
|
||||
read_clock_counter_xsc1(void)
|
||||
{
|
||||
uint32_t x;
|
||||
__asm __volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (x) );
|
||||
|
|
@ -263,6 +296,15 @@ read_clock_counter(void)
|
|||
return x;
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
read_clock_counter_xsc2(void)
|
||||
{
|
||||
uint32_t x;
|
||||
__asm __volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (x) );
|
||||
|
||||
return x;
|
||||
}
|
||||
|
||||
static int
|
||||
pxaip_measure_cpuclock(struct pxaip_softc *sc)
|
||||
{
|
||||
|
|
@ -270,6 +312,9 @@ pxaip_measure_cpuclock(struct pxaip_softc *sc)
|
|||
uint32_t pmcr_save;
|
||||
bus_space_handle_t ioh;
|
||||
int irq;
|
||||
int is_xsc2 = CPU_IS_PXA270;
|
||||
#define read_clock_counter() (is_xsc2 ? read_clock_counter_xsc2() : \
|
||||
read_clock_counter_xsc1())
|
||||
|
||||
if (bus_space_map(sc->sc_bust, PXA2X0_RTC_BASE, PXA2X0_RTC_SIZE, 0,
|
||||
&ioh))
|
||||
|
|
@ -277,9 +322,20 @@ pxaip_measure_cpuclock(struct pxaip_softc *sc)
|
|||
|
||||
irq = disable_interrupts(I32_bit|F32_bit);
|
||||
|
||||
__asm __volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (pmcr_save));
|
||||
if (is_xsc2) {
|
||||
__asm __volatile(
|
||||
"mrc p14, 0, %0, c0, c1, 0" : "=r" (pmcr_save));
|
||||
/* Enable clock counter */
|
||||
__asm __volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (PMNC_E|PMNC_C));
|
||||
__asm __volatile(
|
||||
"mcr p14, 0, %0, c0, c1, 0" : : "r" (PMNC_E|PMNC_C));
|
||||
}
|
||||
else {
|
||||
__asm __volatile(
|
||||
"mrc p14, 0, %0, c0, c0, 0" : "=r" (pmcr_save));
|
||||
/* Enable clock counter */
|
||||
__asm __volatile(
|
||||
"mcr p14, 0, %0, c0, c0, 0" : : "r" (PMNC_E|PMNC_C));
|
||||
}
|
||||
|
||||
rtc0 = bus_space_read_4(sc->sc_bust, ioh, RTC_RCNR);
|
||||
/* Wait for next second starts */
|
||||
|
|
@ -290,7 +346,12 @@ pxaip_measure_cpuclock(struct pxaip_softc *sc)
|
|||
; /* Wait for 1sec */
|
||||
end = read_clock_counter();
|
||||
|
||||
__asm __volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (pmcr_save));
|
||||
if (is_xsc2)
|
||||
__asm __volatile(
|
||||
"mcr p14, 0, %0, c0, c1, 0" : : "r" (pmcr_save));
|
||||
else
|
||||
__asm __volatile(
|
||||
"mcr p14, 0, %0, c0, c0, 0" : : "r" (pmcr_save));
|
||||
restore_interrupts(irq);
|
||||
|
||||
bus_space_unmap(sc->sc_bust, ioh, PXA2X0_RTC_SIZE);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pxa2x0_gpio.c,v 1.2 2003/07/15 00:24:55 lukem Exp $ */
|
||||
/* $NetBSD: pxa2x0_gpio.c,v 1.3 2005/07/04 00:42:37 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 2003 Wasabi Systems, Inc.
|
||||
|
|
@ -36,7 +36,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: pxa2x0_gpio.c,v 1.2 2003/07/15 00:24:55 lukem Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: pxa2x0_gpio.c,v 1.3 2005/07/04 00:42:37 bsh Exp $");
|
||||
|
||||
#include "opt_pxa2x0_gpio.h"
|
||||
|
||||
|
|
@ -48,6 +48,7 @@ __KERNEL_RCSID(0, "$NetBSD: pxa2x0_gpio.c,v 1.2 2003/07/15 00:24:55 lukem Exp $"
|
|||
#include <machine/intr.h>
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <arm/xscale/pxa2x0cpu.h>
|
||||
#include <arm/xscale/pxa2x0reg.h>
|
||||
#include <arm/xscale/pxa2x0var.h>
|
||||
#include <arm/xscale/pxa2x0_gpio.h>
|
||||
|
|
@ -65,8 +66,8 @@ struct pxagpio_softc {
|
|||
struct device sc_dev;
|
||||
bus_space_tag_t sc_bust;
|
||||
bus_space_handle_t sc_bush;
|
||||
void *sc_irqcookie[3];
|
||||
u_int32_t sc_mask[3];
|
||||
void *sc_irqcookie[4];
|
||||
u_int32_t sc_mask[4];
|
||||
#ifdef PXAGPIO_HAS_GPION_INTRS
|
||||
struct gpio_irq_handler *sc_handlers[GPIO_NPINS];
|
||||
#else
|
||||
|
|
@ -145,6 +146,8 @@ pxagpio_attach(struct device *parent, struct device *self, void *aux)
|
|||
return;
|
||||
}
|
||||
|
||||
pxagpio_regs = (vaddr_t)bus_space_vaddr(sc->sc_bust, sc->sc_bush);
|
||||
|
||||
memset(sc->sc_handlers, 0, sizeof(sc->sc_handlers));
|
||||
|
||||
/*
|
||||
|
|
@ -159,6 +162,13 @@ pxagpio_attach(struct device *parent, struct device *self, void *aux)
|
|||
pxagpio_reg_write(sc, GPIO_GEDR0, ~0);
|
||||
pxagpio_reg_write(sc, GPIO_GEDR1, ~0);
|
||||
pxagpio_reg_write(sc, GPIO_GEDR2, ~0);
|
||||
#ifdef CPU_XSCALE_PXA270
|
||||
if (CPU_IS_PXA270) {
|
||||
pxagpio_reg_write(sc, GPIO_GRER3, 0);
|
||||
pxagpio_reg_write(sc, GPIO_GFER3, 0);
|
||||
pxagpio_reg_write(sc, GPIO_GEDR3, ~0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef PXAGPIO_HAS_GPION_INTRS
|
||||
sc->sc_irqcookie[2] = pxa2x0_intr_establish(PXA2X0_INT_GPION, IPL_BIO,
|
||||
|
|
@ -382,6 +392,9 @@ gpio_dispatch(struct pxagpio_softc *sc, int gpio_base)
|
|||
|
||||
gedr &= sc->sc_mask[bank];
|
||||
ghp = &sc->sc_handlers[gpio_base];
|
||||
if (CPU_IS_PXA270)
|
||||
pins = (gpio_base < 96) ? 32 : 25;
|
||||
else
|
||||
pins = (gpio_base < 64) ? 32 : 17;
|
||||
handled = 0;
|
||||
|
||||
|
|
@ -413,7 +426,8 @@ gpio_intrN(void *arg)
|
|||
handled = gpio_dispatch(sc, 0);
|
||||
handled |= gpio_dispatch(sc, 32);
|
||||
handled |= gpio_dispatch(sc, 64);
|
||||
|
||||
if (CPU_IS_PXA270)
|
||||
handled |= gpio_dispatch(sc, 96);
|
||||
return (handled);
|
||||
}
|
||||
#endif /* PXAGPIO_HAS_GPION_INTRS */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pxa2x0_intr.c,v 1.5 2003/07/15 00:24:55 lukem Exp $ */
|
||||
/* $NetBSD: pxa2x0_intr.c,v 1.6 2005/07/04 00:42:37 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Genetec Corporation. All rights reserved.
|
||||
|
|
@ -39,7 +39,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.5 2003/07/15 00:24:55 lukem Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.6 2005/07/04 00:42:37 bsh Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
|
|
@ -49,6 +49,7 @@ __KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.5 2003/07/15 00:24:55 lukem Exp $"
|
|||
#include <machine/intr.h>
|
||||
#include <machine/lock.h>
|
||||
|
||||
#include <arm/xscale/pxa2x0cpu.h>
|
||||
#include <arm/xscale/pxa2x0reg.h>
|
||||
#include <arm/xscale/pxa2x0var.h>
|
||||
#include <arm/xscale/pxa2x0_intr.h>
|
||||
|
|
@ -219,7 +220,7 @@ stray_interrupt(void *cookie)
|
|||
int irqno = (int)cookie;
|
||||
printf("stray interrupt %d\n", irqno);
|
||||
|
||||
if (PXA2X0_IRQ_MIN <= irqno && irqno < ICU_LEN){
|
||||
if (PXA270_IRQ_MIN <= irqno && irqno < ICU_LEN){
|
||||
int save = disable_interrupts(I32_bit);
|
||||
write_icu(SAIPIC_MR,
|
||||
read_icu(SAIPIC_MR) & ~(1U<<irqno));
|
||||
|
|
@ -418,8 +419,9 @@ pxa2x0_intr_establish(int irqno, int level,
|
|||
int (*func)(void *), void *cookie)
|
||||
{
|
||||
int psw;
|
||||
int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN;
|
||||
|
||||
if (irqno < PXA2X0_IRQ_MIN || irqno >= ICU_LEN)
|
||||
if (irqno < irqmin || irqno >= ICU_LEN)
|
||||
panic("intr_establish: bogus irq number %d", irqno);
|
||||
|
||||
psw = disable_interrupts(I32_bit);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pxa2x0_lcd.c,v 1.9 2005/06/05 15:39:17 he Exp $ */
|
||||
/* $NetBSD: pxa2x0_lcd.c,v 1.10 2005/07/04 00:42:37 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Genetec Corporation. All rights reserved.
|
||||
|
|
@ -38,7 +38,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: pxa2x0_lcd.c,v 1.9 2005/06/05 15:39:17 he Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: pxa2x0_lcd.c,v 1.10 2005/07/04 00:42:37 bsh Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
|
|
@ -60,6 +60,7 @@ __KERNEL_RCSID(0, "$NetBSD: pxa2x0_lcd.c,v 1.9 2005/06/05 15:39:17 he Exp $");
|
|||
#include <machine/cpu.h>
|
||||
#include <arm/cpufunc.h>
|
||||
|
||||
#include <arm/xscale/pxa2x0cpu.h>
|
||||
#include <arm/xscale/pxa2x0var.h>
|
||||
#include <arm/xscale/pxa2x0reg.h>
|
||||
#include <arm/xscale/pxa2x0_lcd.h>
|
||||
|
|
@ -177,6 +178,10 @@ pxa2x0_lcd_attach_sub(struct pxa2x0_lcd_softc *sc,
|
|||
nldd = 4;
|
||||
}
|
||||
|
||||
if (CPU_IS_PXA270 && nldd==16) {
|
||||
pxa2x0_gpio_set_function(86, GPIO_ALT_FN_2_OUT);
|
||||
pxa2x0_gpio_set_function(87, GPIO_ALT_FN_2_OUT);
|
||||
}
|
||||
while (nldd--)
|
||||
pxa2x0_gpio_set_function(58 + nldd, GPIO_ALT_FN_2_OUT);
|
||||
|
||||
|
|
@ -216,17 +221,23 @@ pxa2x0_lcd_start_dma(struct pxa2x0_lcd_softc *sc,
|
|||
case 2: val = 1; break;
|
||||
case 4: val = 2; break;
|
||||
case 8: val = 3; break;
|
||||
case 16: /* FALLTHROUGH */
|
||||
case 16: val = 4; break;
|
||||
case 18: val = 5; break;
|
||||
case 24: val = 33; break;
|
||||
default:
|
||||
val = 4; break;
|
||||
}
|
||||
|
||||
tmp = bus_space_read_4(iot, ioh, LCDC_LCCR3);
|
||||
if (CPU_IS_PXA270)
|
||||
bus_space_write_4(iot, ioh, LCDC_LCCR3,
|
||||
(tmp & ~(LCCR3_BPP|(1<<29))) | (val << LCCR3_BPP_SHIFT));
|
||||
else
|
||||
bus_space_write_4(iot, ioh, LCDC_LCCR3,
|
||||
(tmp & ~LCCR3_BPP) | (val << LCCR3_BPP_SHIFT));
|
||||
|
||||
bus_space_write_4(iot, ioh, LCDC_FDADR0,
|
||||
scr->depth == 16 ? scr->dma_desc_pa :
|
||||
scr->depth >= 16 ? scr->dma_desc_pa :
|
||||
scr->dma_desc_pa + 2 * sizeof (struct lcd_dma_descriptor));
|
||||
bus_space_write_4(iot, ioh, LCDC_FDADR1,
|
||||
scr->dma_desc_pa + 1 * sizeof (struct lcd_dma_descriptor));
|
||||
|
|
@ -352,6 +363,14 @@ pxa2x0_lcd_new_screen(struct pxa2x0_lcd_softc *sc,
|
|||
case 16:
|
||||
size = roundup(width,4)*depth/8 * height;
|
||||
break;
|
||||
case 18:
|
||||
case 24:
|
||||
size = roundup(width,4) * 4 * height;
|
||||
break;
|
||||
case 19:
|
||||
case 25:
|
||||
printf("%s: Not supported depth (%d)\n", sc->dev.dv_xname, depth);
|
||||
return NULL;
|
||||
default:
|
||||
printf("%s: Unknown depth (%d)\n", sc->dev.dv_xname, depth);
|
||||
return NULL;
|
||||
|
|
@ -489,6 +508,9 @@ pxa2x0_lcd_setup_wsscreen(struct pxa2x0_wsscreen_descr *descr,
|
|||
rinfo.ri_width = width;
|
||||
rinfo.ri_height = height;
|
||||
rinfo.ri_stride = width * rinfo.ri_depth / 8;
|
||||
#ifdef CPU_XSCALE_PXA270
|
||||
if (rinfo.ri_depth > 16) rinfo.ri_stride = width * 4;
|
||||
#endif
|
||||
rinfo.ri_wsfcookie = cookie;
|
||||
|
||||
rasops_init(&rinfo, 100, 100);
|
||||
|
|
@ -543,6 +565,10 @@ pxa2x0_lcd_alloc_screen(void *v, const struct wsscreen_descr *_type,
|
|||
scr->rinfo.ri_width = sc->geometry->panel_width;
|
||||
scr->rinfo.ri_height = sc->geometry->panel_height;
|
||||
scr->rinfo.ri_stride = scr->rinfo.ri_width * scr->rinfo.ri_depth / 8;
|
||||
#ifdef CPU_XSCALE_PXA270
|
||||
if (scr->rinfo.ri_depth > 16)
|
||||
scr->rinfo.ri_stride = scr->rinfo.ri_width * 4;
|
||||
#endif
|
||||
scr->rinfo.ri_wsfcookie = -1; /* XXX */
|
||||
|
||||
rasops_init(&scr->rinfo, type->c.nrows, type->c.ncols);
|
||||
|
|
@ -600,7 +626,7 @@ pxa2x0_lcd_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p)
|
|||
|
||||
wsdisp_info->height = sc->geometry->panel_height;
|
||||
wsdisp_info->width = sc->geometry->panel_width;
|
||||
wsdisp_info->depth = 16; /* XXX */
|
||||
wsdisp_info->depth = sc->active->depth;
|
||||
wsdisp_info->cmsize = 0;
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,88 @@
|
|||
/* $NetBSD: pxa2x0cpu.h,v 1.1 2005/07/04 00:42:37 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2005 Genetec Corporation. All rights reserved.
|
||||
* Written by Hiroyuki Bessho for Genetec Corporation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of Genetec Corporation may not be used to endorse or
|
||||
* promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* In kernel config file, users can have options
|
||||
* CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270.
|
||||
*
|
||||
* If kernel is configured to support PXA250 and PXA270, CPU type is
|
||||
* determined run-time by reading a co-processor register.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_XSCALE_PXA2X0CPU_H
|
||||
#define _ARM_XSCALE_PXA2X0CPU_H
|
||||
|
||||
#ifdef _KERNEL_OPT
|
||||
#include "opt_cputypes.h" /* User's choice of CPU */
|
||||
#endif
|
||||
|
||||
#if !defined(CPU_XSCALE_PXA250) && !defined(CPU_XSCALE_PXA270)
|
||||
#error neither CPU_XSCALE_PXA250 nor CPU_XSCALE_PXA270 is defined.
|
||||
#endif
|
||||
|
||||
#if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270)
|
||||
# define __CPU_XSCALE_PXA2XX
|
||||
#endif
|
||||
|
||||
#define CPU_ID_PXA_MASK (CPU_ID_IMPLEMETOR_MASK|CPU_ID_VARIANT_MASK|\
|
||||
CPU_ID_ARCH_MASK|CPU_ID_XSCALE_COREGEN_MASK)
|
||||
|
||||
#define __CPU_IS_PXA250 ((cpufunc_id() & CPU_ID_XSCALE_COREGEN_MASK) == 0x2000)
|
||||
#define __CPU_IS_PXA270 ((cpufunc_id() & CPU_ID_XSCALE_COREGEN_MASK) == 0x4000)
|
||||
|
||||
# if defined(CPU_XSCALE_PXA250) && defined(CPU_XSCALE_PXA270)
|
||||
#define CPU_IS_PXA250 __CPU_IS_PXA250
|
||||
#define CPU_IS_PXA270 __CPU_IS_PXA270
|
||||
#elif defined(CPU_XSCALE_PXA250) && !defined(CPU_XSCALE_PXA270)
|
||||
#define CPU_IS_PXA250 (1)
|
||||
#define CPU_IS_PXA270 (0)
|
||||
#elif !defined(CPU_XSCALE_PXA250) && defined(CPU_XSCALE_PXA270)
|
||||
#define CPU_IS_PXA250 (0)
|
||||
#define CPU_IS_PXA270 (1)
|
||||
#elif !defined(CPU_XSCALE_PXA250) && !defined(CPU_XSCALE_PXA270)
|
||||
#define CPU_IS_PXA250 (0)
|
||||
#define CPU_IS_PXA270 (0)
|
||||
#endif
|
||||
|
||||
#include <arm/xscale/pxa2x0reg.h>
|
||||
|
||||
#ifdef CPU_XSCALE_PXA270
|
||||
#define PXA2X0_GPIO_SIZE PXA270_GPIO_SIZE
|
||||
#define GPIO_REG PXA270_GPIO_REG
|
||||
#define GPIO_NPINS PXA270_GPIO_NPINS
|
||||
#else
|
||||
#define PXA2X0_GPIO_SIZE PXA250_GPIO_SIZE
|
||||
#define GPIO_REG PXA250_GPIO_REG
|
||||
#define GPIO_NPINS PXA250_GPIO_NPINS
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_XSCALE_PXA2X0CPU_H */
|
||||
Loading…
Reference in New Issue