Finish off GPIO handler. Add hook for other driver to access a named gpio.
Add two input gpio's for usb0.
This commit is contained in:
matt
parent
18ec38ea7c
commit
c5a9cb82c0
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@ -28,15 +28,17 @@
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*/
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#include "locators.h"
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#include "gpio.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: awin_gpio.c,v 1.3 2013/09/07 02:09:23 matt Exp $");
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__KERNEL_RCSID(1, "$NetBSD: awin_gpio.c,v 1.4 2013/09/07 19:47:28 matt Exp $");
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/kmem.h>
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#include <sys/gpio.h>
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@ -48,6 +50,10 @@ __KERNEL_RCSID(1, "$NetBSD: awin_gpio.c,v 1.3 2013/09/07 02:09:23 matt Exp $");
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static int awin_gpio_match(device_t, cfdata_t, void *);
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static void awin_gpio_attach(device_t, device_t, void *);
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static int awin_gpio_pin_read(void *, int);
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static void awin_gpio_pin_write(void *, int, int);
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static void awin_gpio_pin_ctl(void *, int, int);
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static const int ist_maps[] = {
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[IST_LEVEL_LOW] = AWIN_PIO_EINT_LOW_LEVEL,
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[IST_LEVEL_HIGH] = AWIN_PIO_EINT_HIGH_LEVEL,
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@ -57,7 +63,9 @@ static const int ist_maps[] = {
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};
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struct awin_gpio_pin_cfg {
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uint32_t val[4];
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uint32_t cfg[4];
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uint32_t drv[2];
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uint32_t pul[2];
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};
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static struct awin_gpio_pin_group {
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@ -65,21 +73,101 @@ static struct awin_gpio_pin_group {
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uint32_t grp_pin_inuse_mask;
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bus_space_handle_t grp_bsh;
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struct awin_gpio_pin_cfg grp_cfg;
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struct gpio_chipset_tag grp_gc_tag;
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const char grp_nc_name[6];
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} pin_groups[] = {
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[0] = { .grp_pin_mask = __BIT(AWIN_PIO_PA_PINS) - 1 },
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[1] = { .grp_pin_mask = __BIT(AWIN_PIO_PB_PINS) - 1 },
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[2] = { .grp_pin_mask = __BIT(AWIN_PIO_PC_PINS) - 1 },
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[3] = { .grp_pin_mask = __BIT(AWIN_PIO_PD_PINS) - 1 },
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[4] = { .grp_pin_mask = __BIT(AWIN_PIO_PE_PINS) - 1 },
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[5] = { .grp_pin_mask = __BIT(AWIN_PIO_PF_PINS) - 1 },
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[6] = { .grp_pin_mask = __BIT(AWIN_PIO_PG_PINS) - 1 },
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[7] = { .grp_pin_mask = __BIT(AWIN_PIO_PH_PINS) - 1 },
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[8] = { .grp_pin_mask = __BIT(AWIN_PIO_PI_PINS) - 1 },
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[0] = {
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.grp_pin_mask = __BIT(AWIN_PIO_PA_PINS) - 1,
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.grp_gc_tag = {
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.gp_cookie = &pin_groups[0],
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.gp_pin_read = awin_gpio_pin_read,
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.gp_pin_write = awin_gpio_pin_write,
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.gp_pin_ctl = awin_gpio_pin_ctl,
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},
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.grp_nc_name = "nc-pa",
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},
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[1] = {
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.grp_pin_mask = __BIT(AWIN_PIO_PB_PINS) - 1,
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.grp_gc_tag = {
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.gp_cookie = &pin_groups[1],
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.gp_pin_read = awin_gpio_pin_read,
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.gp_pin_write = awin_gpio_pin_write,
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.gp_pin_ctl = awin_gpio_pin_ctl,
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},
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.grp_nc_name = "nc-pb",
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},
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[2] = {
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.grp_pin_mask = __BIT(AWIN_PIO_PC_PINS) - 1,
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.grp_gc_tag = {
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.gp_cookie = &pin_groups[2],
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.gp_pin_read = awin_gpio_pin_read,
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.gp_pin_write = awin_gpio_pin_write,
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.gp_pin_ctl = awin_gpio_pin_ctl,
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},
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.grp_nc_name = "nc-pc",
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},
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[3] = {
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.grp_pin_mask = __BIT(AWIN_PIO_PD_PINS) - 1,
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.grp_gc_tag = {
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.gp_cookie = &pin_groups[3],
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.gp_pin_read = awin_gpio_pin_read,
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.gp_pin_write = awin_gpio_pin_write,
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.gp_pin_ctl = awin_gpio_pin_ctl,
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},
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.grp_nc_name = "nc-pd",
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},
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[4] = {
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.grp_pin_mask = __BIT(AWIN_PIO_PE_PINS) - 1,
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.grp_gc_tag = {
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.gp_cookie = &pin_groups[4],
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.gp_pin_read = awin_gpio_pin_read,
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.gp_pin_write = awin_gpio_pin_write,
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.gp_pin_ctl = awin_gpio_pin_ctl,
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},
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.grp_nc_name = "nc-pe",
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},
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[5] = {
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.grp_pin_mask = __BIT(AWIN_PIO_PF_PINS) - 1,
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.grp_gc_tag = {
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.gp_cookie = &pin_groups[5],
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.gp_pin_read = awin_gpio_pin_read,
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.gp_pin_write = awin_gpio_pin_write,
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.gp_pin_ctl = awin_gpio_pin_ctl,
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},
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.grp_nc_name = "nc-pf",
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},
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[6] = {
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.grp_pin_mask = __BIT(AWIN_PIO_PG_PINS) - 1,
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.grp_gc_tag = {
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.gp_cookie = &pin_groups[6],
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.gp_pin_read = awin_gpio_pin_read,
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.gp_pin_write = awin_gpio_pin_write,
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.gp_pin_ctl = awin_gpio_pin_ctl,
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},
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.grp_nc_name = "nc-pg",
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},
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[7] = {
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.grp_pin_mask = __BIT(AWIN_PIO_PH_PINS) - 1,
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.grp_gc_tag = {
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.gp_cookie = &pin_groups[7],
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.gp_pin_read = awin_gpio_pin_read,
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.gp_pin_write = awin_gpio_pin_write,
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.gp_pin_ctl = awin_gpio_pin_ctl,
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},
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.grp_nc_name = "nc-ph",
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},
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[8] = {
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.grp_pin_mask = __BIT(AWIN_PIO_PI_PINS) - 1,
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.grp_gc_tag = {
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.gp_cookie = &pin_groups[8],
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.gp_pin_read = awin_gpio_pin_read,
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.gp_pin_write = awin_gpio_pin_write,
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.gp_pin_ctl = awin_gpio_pin_ctl,
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},
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.grp_nc_name = "nc-pi",
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},
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};
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struct awin_eint_info {
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uint32_t grp_pin ;
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};
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static struct awin_gpio_softc {
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device_t sc_dev;
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return 1;
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}
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#if NGPIO > 0
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static void
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awin_gpio_config_pins(device_t self)
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{
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struct awin_gpio_softc * const sc = &awin_gpio_sc;
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/*
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* First find out how many pins we can offer.
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*/
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size_t pin_count = 0;
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for (u_int i = 0; i < __arraycount(pin_groups); i++) {
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struct awin_gpio_pin_group * const grp = &pin_groups[i];
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pin_count +=
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popcount32(grp->grp_pin_mask & ~grp->grp_pin_inuse_mask);
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}
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/*
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* Allocate the pin data.
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*/
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gpio_pin_t * const pins = kmem_zalloc(sizeof(gpio_pin_t) * pin_count,
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KM_SLEEP);
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KASSERT(pins != NULL);
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const int pincaps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT
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| GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN;
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gpio_pin_t *pin = pins;
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for (u_int i = 0; i < __arraycount(pin_groups); i++) {
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struct awin_gpio_pin_group * const grp = &pin_groups[i];
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uint32_t mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask;
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/*
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* If this group has no bits to provide, skip it.
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*/
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if (mask == 0)
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continue;
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struct gpiobus_attach_args gba = {
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.gba_gc = &grp->grp_gc_tag,
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.gba_pins = pin,
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};
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uint32_t data = bus_space_read_4(sc->sc_bst, grp->grp_bsh,
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AWIN_PIO_DAT_REG);
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for (int num = 0; mask != 0; mask >>= 1, data >>= 1, num++) {
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if (mask & 1) {
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pin->pin_num = num + (i << 5);
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pin->pin_caps = pincaps;
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pin->pin_flags = pincaps;
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pin->pin_state = (data & 1) != 0;
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pin++;
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}
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}
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gba.gba_npins = pin - gba.gba_pins;
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config_found_ia(self, "gpiobus", &gba, gpiobus_print);
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}
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}
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#endif /* NGPIO > 0 */
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static void
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awin_gpio_attach(device_t parent, device_t self, void *aux)
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{
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struct awin_gpio_softc * const sc = &awin_gpio_sc;
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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prop_dictionary_t dict = device_properties(self);
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sc->sc_dev = self;
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aprint_naive("\n");
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aprint_normal("\n");
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for (u_int i = 0; i < __arraycount(pin_groups); i++) {
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struct awin_gpio_pin_group * const grp = &pin_groups[i];
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/*
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* See if this group has any unconnected pins and make sure
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* we won't use them.
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*/
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uint32_t nc;
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if (prop_dictionary_get_uint32(dict, grp->grp_nc_name, &nc)) {
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KASSERT((~grp->grp_pin_mask & nc) == 0);
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KASSERT((grp->grp_pin_inuse_mask & ~nc) == 0);
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grp->grp_pin_mask &= ~nc;
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}
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}
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#if NGPIO > 0
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config_defer(self, awin_gpio_config_pins);
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#endif
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}
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static u_int
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awin_gpio_get_pin_func(const struct awin_gpio_pin_cfg *cfg, u_int pin)
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{
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const u_int shift = (pin & 7) << 2;
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const u_int i = pin >> 3;
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return (cfg->val[i] >> shift) & 0x0f;
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const u_int i = (pin >> 3) & 3;
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return (cfg->cfg[i] >> shift) & 0x0f;
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}
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static void
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awin_gpio_set_pin_func(struct awin_gpio_pin_cfg *cfg, u_int pin, u_int func)
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{
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const u_int shift = (pin & 7) << 2;
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const u_int i = pin >> 3;
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const u_int i = (pin >> 3) & 3;
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cfg->val[i] &= ~(0x0f << shift);
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cfg->val[i] |= func << shift;
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cfg->cfg[i] &= ~(0x0f << shift);
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cfg->cfg[i] |= func << shift;
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}
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static void
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awin_gpio_set_pin_pull(struct awin_gpio_pin_cfg *cfg, u_int pin, u_int pull)
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{
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const u_int shift = (pin & 15) << 1;
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const u_int i = (pin >> 4) & 1;
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cfg->pul[i] &= ~(0x03 << shift);
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cfg->pul[i] |= pull << shift;
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}
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static void
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@ -148,10 +328,22 @@ awin_gpio_update_cfg_regs(bus_space_tag_t bst, struct awin_gpio_pin_group *grp,
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const struct awin_gpio_pin_cfg *ncfg)
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{
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for (u_int i = 0; i < 4; i++) {
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if (grp->grp_cfg.val[i] != ncfg->val[i]) {
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if (grp->grp_cfg.cfg[i] != ncfg->cfg[i]) {
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bus_space_write_4(bst, grp->grp_bsh,
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AWIN_PIO_CFG0_REG + 4 * i, ncfg->val[i]);
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grp->grp_cfg.val[i] = ncfg->val[i];
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AWIN_PIO_CFG0_REG + 4 * i, ncfg->cfg[i]);
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grp->grp_cfg.cfg[i] = ncfg->cfg[i];
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}
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}
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for (u_int i = 0; i < 2; i++) {
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if (grp->grp_cfg.drv[i] != ncfg->drv[i]) {
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bus_space_write_4(bst, grp->grp_bsh,
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AWIN_PIO_DRV0_REG + 4 * i, ncfg->drv[i]);
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grp->grp_cfg.drv[i] = ncfg->drv[i];
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}
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if (grp->grp_cfg.pul[i] != ncfg->pul[i]) {
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bus_space_write_4(bst, grp->grp_bsh,
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AWIN_PIO_PUL0_REG + 4 * i, ncfg->pul[i]);
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grp->grp_cfg.pul[i] = ncfg->pul[i];
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}
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}
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}
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@ -173,9 +365,17 @@ awin_gpio_init(void)
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offset, AWIN_PIO_GRP_SIZE, &grp->grp_bsh);
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for (u_int j = 0; j < 4; j++) {
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grp->grp_cfg.val[j] = bus_space_read_4(sc->sc_bst,
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grp->grp_cfg.cfg[j] = bus_space_read_4(sc->sc_bst,
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grp->grp_bsh, AWIN_PIO_CFG0_REG + j * 4);
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}
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grp->grp_cfg.drv[0] = bus_space_read_4(sc->sc_bst,
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grp->grp_bsh, AWIN_PIO_DRV0_REG);
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grp->grp_cfg.drv[1] = bus_space_read_4(sc->sc_bst,
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grp->grp_bsh, AWIN_PIO_DRV1_REG);
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grp->grp_cfg.pul[0] = bus_space_read_4(sc->sc_bst,
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grp->grp_bsh, AWIN_PIO_PUL0_REG);
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grp->grp_cfg.pul[1] = bus_space_read_4(sc->sc_bst,
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grp->grp_bsh, AWIN_PIO_PUL1_REG);
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for (uint32_t j = 0, mask = 1;
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(mask & grp->grp_pin_mask) != 0;
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@ -329,3 +529,89 @@ awin_gpio_pinset_release(const struct awin_gpio_pinset *req)
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*/
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grp->grp_pin_inuse_mask &= ~req->pinset_mask;
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}
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static int
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awin_gpio_pin_read(void *cookie, int pin)
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{
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struct awin_gpio_pin_group * const grp = cookie;
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KASSERT(pin < 32);
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return (bus_space_read_4(awin_gpio_sc.sc_bst, grp->grp_bsh,
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AWIN_PIO_DAT_REG) >> pin) & 1;
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}
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static void
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awin_gpio_pin_write(void *cookie, int pin, int value)
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{
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struct awin_gpio_pin_group * const grp = cookie;
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KASSERT(pin < 32);
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awin_reg_set_clear(awin_gpio_sc.sc_bst, grp->grp_bsh,
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AWIN_PIO_DAT_REG, value ? __BIT(pin) : 0, __BIT(pin));
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}
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static void
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awin_gpio_pin_ctl(void *cookie, int pin, int flags)
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{
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struct awin_gpio_pin_group * const grp = cookie;
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struct awin_gpio_pin_cfg ncfg = grp->grp_cfg;
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u_int pull_value = AWIN_PIO_PULL_NONE;
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if (flags & GPIO_PIN_PULLUP) {
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pull_value = AWIN_PIO_PULL_UP;
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} else if (flags & GPIO_PIN_PULLDOWN) {
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pull_value = AWIN_PIO_PULL_DOWN;
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}
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awin_gpio_set_pin_pull(&ncfg, pin, pull_value);
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if (flags & GPIO_PIN_INPUT) {
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awin_gpio_set_pin_func(&ncfg, pin, AWIN_PIO_FUNC_INPUT);
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} else if (flags & GPIO_PIN_OUTPUT) {
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awin_gpio_set_pin_func(&ncfg, pin, AWIN_PIO_FUNC_INPUT);
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}
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/*
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* Now update any config register that changed.
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*/
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awin_gpio_update_cfg_regs(&awin_bs_tag, grp, &ncfg);
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}
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bool
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awin_gpio_pin_reserve(const char *name, struct awin_gpio_pindata *pd)
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{
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struct awin_gpio_softc * const sc = &awin_gpio_sc;
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prop_dictionary_t dict = device_properties(sc->sc_dev);
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const char *pin_data;
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if (!prop_dictionary_get_cstring_nocopy(dict, name, &pin_data))
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return false;
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KASSERT(pin_data[0] == '>' || pin_data[0] == '<');
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KASSERT(pin_data[1] == 'P');
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KASSERT('A' <= pin_data[2] && pin_data[2] <= 'I');
|
||||
struct awin_gpio_pin_group * const grp = &pin_groups[pin_data[2] - 'A'];
|
||||
|
||||
u_int pin = pin_data[3] - '0';
|
||||
KASSERT(pin < 10);
|
||||
if (pin_data[4] != 0) {
|
||||
KASSERT(pin_data[5] == 0);
|
||||
pin = pin * 10 + pin_data[4] - '0';
|
||||
}
|
||||
|
||||
KASSERT(pin < 32);
|
||||
KASSERT(grp->grp_pin_mask & __BIT(pin));
|
||||
KASSERT((grp->grp_pin_inuse_mask & __BIT(pin)) == 0);
|
||||
|
||||
struct awin_gpio_pin_cfg ncfg = grp->grp_cfg;
|
||||
awin_gpio_set_pin_func(&ncfg, pin,
|
||||
pin_data[0] == '<' ? AWIN_PIO_FUNC_INPUT : AWIN_PIO_FUNC_OUTPUT);
|
||||
|
||||
grp->grp_pin_inuse_mask &= ~__BIT(pin);
|
||||
|
||||
pd->pd_gc = &grp->grp_gc_tag;
|
||||
pd->pd_pin = pin;
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -197,25 +197,25 @@
|
|||
#define AWIN_DRAM_PLDTR_REG 0x023C
|
||||
#define AWIN_DRAM_HPCR0_REG 0x0240
|
||||
#define AWIN_DRAM_HPCRn_REG(n) (0x0240+4*(n))
|
||||
#define AWIN_DRAM_HPCR_USB1 AWIN_DRAM_HPCRn_REG(4)
|
||||
#define AWIN_DRAM_HPCR_USB2 AWIN_DRAM_HPCRn_REG(5)
|
||||
#define AWIN_DRAM_HPCR_USB1_REG AWIN_DRAM_HPCRn_REG(4)
|
||||
#define AWIN_DRAM_HPCR_USB2_REG AWIN_DRAM_HPCRn_REG(5)
|
||||
#define AWIN_DRAM_CSEL_REG 0x02E0
|
||||
|
||||
#define AWIN_DRAM_DCR_IO_WIDTH __BITS(2,1)
|
||||
#define AWIN_DRAM_DCR_IO_WIDTH_16BIT 2
|
||||
#define AWIN_DRAM_DCR_IO_WIDTH_8BIT 1
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY __BITS(5,3)
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_256M 0
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_512M 1
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_1G 2
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_2G 3
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_4G 4
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_8G 5
|
||||
#define AWIN_DRAM_DCR_BUS_WIDTH __BITS(8,6)
|
||||
#define AWIN_DRAM_DCR_IO_WIDTH __BITS(2,1)
|
||||
#define AWIN_DRAM_DCR_IO_WIDTH_16BIT 2
|
||||
#define AWIN_DRAM_DCR_IO_WIDTH_8BIT 1
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY __BITS(5,3)
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_256M 0
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_512M 1
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_1G 2
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_2G 3
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_4G 4
|
||||
#define AWIN_DRAM_DCR_CHIP_DENSITY_8G 5
|
||||
#define AWIN_DRAM_DCR_BUS_WIDTH __BITS(8,6)
|
||||
#define AWIN_DRAM_DCR_BUS_WIDTH_32BIT 3
|
||||
#define AWIN_DRAM_DCR_BUS_WIDTH_16BIT 1
|
||||
#define AWIN_DRAM_DCR_BUS_WIDTH_8BIT 0
|
||||
#define AWIN_DRAM_DCR_RANK_SEL __BITS(11,10)
|
||||
#define AWIN_DRAM_DCR_RANK_SEL __BITS(11,10)
|
||||
|
||||
#define AWIN_DRAM_HPCR_READ_CNT_EN __BIT(31)
|
||||
#define AWIN_DRAM_HPCR_RWRITE_CNT_EN __BIT(30)
|
||||
|
|
@ -299,23 +299,23 @@
|
|||
#define AWIN_AHCI_P0PHYSR_REG 0x017C
|
||||
|
||||
|
||||
#define AWIN_PLL1_CFG_REG 0x0000
|
||||
#define AWIN_PLL1_TUN_REG 0x0004
|
||||
#define AWIN_PLL2_CFG_REG 0x0008
|
||||
#define AWIN_PLL2_TUN_REG 0x000C
|
||||
#define AWIN_PLL3_CFG_REG 0x0010
|
||||
#define AWIN_PLL4_CFG_REG 0x0018
|
||||
#define AWIN_PLL5_CFG_REG 0x0020
|
||||
#define AWIN_PLL5_TUN_REG 0x0024
|
||||
#define AWIN_PLL6_CFG_REG 0x0028
|
||||
#define AWIN_PLL6_TUN_REG 0x002C
|
||||
#define AWIN_PLL7_CFG_REG 0x0030
|
||||
#define AWIN_PLL1_TUN2_REG 0x0038
|
||||
#define AWIN_PLL6_TUN2_REG 0x003C
|
||||
#define AWIN_PLL8_CFG_REG 0x0040
|
||||
#define AWIN_OSC24M_CFG_REG 0x0050
|
||||
#define AWIN_CPU_AHB_APB0_CFG_REG 0x0054
|
||||
#define AWIN_APB1_CLK_DIV_REG 0x0058
|
||||
#define AWIN_PLL1_CFG_REG 0x0000
|
||||
#define AWIN_PLL1_TUN_REG 0x0004
|
||||
#define AWIN_PLL2_CFG_REG 0x0008
|
||||
#define AWIN_PLL2_TUN_REG 0x000C
|
||||
#define AWIN_PLL3_CFG_REG 0x0010
|
||||
#define AWIN_PLL4_CFG_REG 0x0018
|
||||
#define AWIN_PLL5_CFG_REG 0x0020
|
||||
#define AWIN_PLL5_TUN_REG 0x0024
|
||||
#define AWIN_PLL6_CFG_REG 0x0028
|
||||
#define AWIN_PLL6_TUN_REG 0x002C
|
||||
#define AWIN_PLL7_CFG_REG 0x0030
|
||||
#define AWIN_PLL1_TUN2_REG 0x0038
|
||||
#define AWIN_PLL6_TUN2_REG 0x003C
|
||||
#define AWIN_PLL8_CFG_REG 0x0040
|
||||
#define AWIN_OSC24M_CFG_REG 0x0050
|
||||
#define AWIN_CPU_AHB_APB0_CFG_REG 0x0054
|
||||
#define AWIN_APB1_CLK_DIV_REG 0x0058
|
||||
#define AWIN_AXI_GATING_REG 0x005C
|
||||
#define AWIN_AHB_GATING0_REG 0x0060
|
||||
#define AWIN_AHB_GATING1_REG 0x0064
|
||||
|
|
@ -373,19 +373,19 @@
|
|||
|
||||
#define AWIN_OSC24M_CFG_ENABLE __BIT(0)
|
||||
|
||||
#define AWIN_PLL_CFG_ENABLE __BIT(31)
|
||||
#define AWIN_PLL_CFG_BYPASS __BIT(30)
|
||||
#define AWIN_PLL_CFG_ENABLE __BIT(31)
|
||||
#define AWIN_PLL_CFG_BYPASS __BIT(30)
|
||||
#define AWIN_PLL5_CFG_DDR_CLK_EN __BIT(29)
|
||||
#define AWIN_PLL_CFG_EXG_MODE __BIT(25)
|
||||
#define AWIN_PLL_CFG_OUT_EXP_DIVP __BITS(17,16)
|
||||
#define AWIN_PLL_CFG_EXG_MODE __BIT(25)
|
||||
#define AWIN_PLL_CFG_OUT_EXP_DIVP __BITS(17,16)
|
||||
#define AWIN_PLL6_CFG_SATA_CLK_EN __BIT(14)
|
||||
#define AWIN_PLL_CFG_FACTOR_N __BITS(12,8)
|
||||
#define AWIN_PLL_CFG_FACTOR_N __BITS(12,8)
|
||||
#define AWIN_PLL5_CFG_LDO_EN __BIT(7)
|
||||
#define AWIN_PLL_CFG_FACTOR_K __BITS(5,4)
|
||||
#define AWIN_PLL5_CFG_FACTOR_M1 __BITS(3,2)
|
||||
#define AWIN_PLL_CFG_FACTOR_K __BITS(5,4)
|
||||
#define AWIN_PLL5_CFG_FACTOR_M1 __BITS(3,2)
|
||||
#define AWIN_PLL1_SIG_DELT_PAT_IN __BIT(3)
|
||||
#define AWIN_PLL1_SIG_DELT_PAT_EN __BIT(2)
|
||||
#define AWIN_PLL_CFG_FACTOR_M __BITS(1,0)
|
||||
#define AWIN_PLL_CFG_FACTOR_M __BITS(1,0)
|
||||
|
||||
#define AWIN_CPU_CLK_SRC_SEL __BITS(17,16)
|
||||
#define AWIN_CPU_CLK_SRC_SEL_LOSC 0
|
||||
|
|
@ -394,48 +394,48 @@
|
|||
#define AWIN_CPU_CLK_SRC_SEL_200MHZ 3
|
||||
#define AWIN_APB0_CLK_RATIO __BITS(9,8)
|
||||
|
||||
#define AWIN_AHB_GATING0_STIMER __BIT(28)
|
||||
#define AWIN_AHB_GATING0_SATA __BIT(25)
|
||||
#define AWIN_AHB_GATING0_PATA __BIT(24)
|
||||
#define AWIN_AHB_GATING0_SPI3 __BIT(23)
|
||||
#define AWIN_AHB_GATING0_SPI2 __BIT(22)
|
||||
#define AWIN_AHB_GATING0_SPI1 __BIT(21)
|
||||
#define AWIN_AHB_GATING0_SPI0 __BIT(20)
|
||||
#define AWIN_AHB_GATING0_TS __BIT(18)
|
||||
#define AWIN_AHB_GATING0_EMAC __BIT(17)
|
||||
#define AWIN_AHB_GATING0_ACE __BIT(16)
|
||||
#define AWIN_AHB_GATING0_SDRAM __BIT(14)
|
||||
#define AWIN_AHB_GATING0_NAND __BIT(13)
|
||||
#define AWIN_AHB_GATING0_NC12 __BIT(12)
|
||||
#define AWIN_AHB_GATING0_SDMMC3 __BIT(11)
|
||||
#define AWIN_AHB_GATING0_SDMMC2 __BIT(10)
|
||||
#define AWIN_AHB_GATING0_SDMMC1 __BIT(9)
|
||||
#define AWIN_AHB_GATING0_SDMMC0 __BIT(8)
|
||||
#define AWIN_AHB_GATING0_BIST __BIT(7)
|
||||
#define AWIN_AHB_GATING0_DMA __BIT(6)
|
||||
#define AWIN_AHB_GATING0_SS __BIT(5)
|
||||
#define AWIN_AHB_GATING0_USB_OHCI1 __BIT(4)
|
||||
#define AWIN_AHB_GATING0_USB_EHCI1 __BIT(3)
|
||||
#define AWIN_AHB_GATING0_USB_OHCI0 __BIT(1)
|
||||
#define AWIN_AHB_GATING0_USB_EHCI0 __BIT(1)
|
||||
#define AWIN_AHB_GATING0_USB0 __BIT(0)
|
||||
#define AWIN_AHB_GATING0_STIMER __BIT(28)
|
||||
#define AWIN_AHB_GATING0_SATA __BIT(25)
|
||||
#define AWIN_AHB_GATING0_PATA __BIT(24)
|
||||
#define AWIN_AHB_GATING0_SPI3 __BIT(23)
|
||||
#define AWIN_AHB_GATING0_SPI2 __BIT(22)
|
||||
#define AWIN_AHB_GATING0_SPI1 __BIT(21)
|
||||
#define AWIN_AHB_GATING0_SPI0 __BIT(20)
|
||||
#define AWIN_AHB_GATING0_TS __BIT(18)
|
||||
#define AWIN_AHB_GATING0_EMAC __BIT(17)
|
||||
#define AWIN_AHB_GATING0_ACE __BIT(16)
|
||||
#define AWIN_AHB_GATING0_SDRAM __BIT(14)
|
||||
#define AWIN_AHB_GATING0_NAND __BIT(13)
|
||||
#define AWIN_AHB_GATING0_NC12 __BIT(12)
|
||||
#define AWIN_AHB_GATING0_SDMMC3 __BIT(11)
|
||||
#define AWIN_AHB_GATING0_SDMMC2 __BIT(10)
|
||||
#define AWIN_AHB_GATING0_SDMMC1 __BIT(9)
|
||||
#define AWIN_AHB_GATING0_SDMMC0 __BIT(8)
|
||||
#define AWIN_AHB_GATING0_BIST __BIT(7)
|
||||
#define AWIN_AHB_GATING0_DMA __BIT(6)
|
||||
#define AWIN_AHB_GATING0_SS __BIT(5)
|
||||
#define AWIN_AHB_GATING0_USB_OHCI1 __BIT(4)
|
||||
#define AWIN_AHB_GATING0_USB_EHCI1 __BIT(3)
|
||||
#define AWIN_AHB_GATING0_USB_OHCI0 __BIT(1)
|
||||
#define AWIN_AHB_GATING0_USB_EHCI0 __BIT(1)
|
||||
#define AWIN_AHB_GATING0_USB0 __BIT(0)
|
||||
|
||||
#define AWIN_AHB_GATING1_MALI400 __BIT(20)
|
||||
#define AWIN_AHB_GATING1_MP __BIT(18)
|
||||
#define AWIN_AHB_GATING1_GMAC __BIT(17)
|
||||
#define AWIN_AHB_GATING1_DE_FE1 __BIT(15)
|
||||
#define AWIN_AHB_GATING1_DE_FE0 __BIT(14)
|
||||
#define AWIN_AHB_GATING1_DE_BE1 __BIT(13)
|
||||
#define AWIN_AHB_GATING1_DE_BE0 __BIT(12)
|
||||
#define AWIN_AHB_GATING1_HDMI __BIT(11)
|
||||
#define AWIN_AHB_GATING1_CSI1 __BIT(9)
|
||||
#define AWIN_AHB_GATING1_CSI0 __BIT(8)
|
||||
#define AWIN_AHB_GATING1_LCD1 __BIT(5)
|
||||
#define AWIN_AHB_GATING1_LCD0 __BIT(4)
|
||||
#define AWIN_AHB_GATING1_TVE1 __BIT(3)
|
||||
#define AWIN_AHB_GATING1_TVE0 __BIT(2)
|
||||
#define AWIN_AHB_GATING1_TVD __BIT(1)
|
||||
#define AWIN_AHB_GATING1_VE __BIT(0)
|
||||
#define AWIN_AHB_GATING1_MALI400 __BIT(20)
|
||||
#define AWIN_AHB_GATING1_MP __BIT(18)
|
||||
#define AWIN_AHB_GATING1_GMAC __BIT(17)
|
||||
#define AWIN_AHB_GATING1_DE_FE1 __BIT(15)
|
||||
#define AWIN_AHB_GATING1_DE_FE0 __BIT(14)
|
||||
#define AWIN_AHB_GATING1_DE_BE1 __BIT(13)
|
||||
#define AWIN_AHB_GATING1_DE_BE0 __BIT(12)
|
||||
#define AWIN_AHB_GATING1_HDMI __BIT(11)
|
||||
#define AWIN_AHB_GATING1_CSI1 __BIT(9)
|
||||
#define AWIN_AHB_GATING1_CSI0 __BIT(8)
|
||||
#define AWIN_AHB_GATING1_LCD1 __BIT(5)
|
||||
#define AWIN_AHB_GATING1_LCD0 __BIT(4)
|
||||
#define AWIN_AHB_GATING1_TVE1 __BIT(3)
|
||||
#define AWIN_AHB_GATING1_TVE0 __BIT(2)
|
||||
#define AWIN_AHB_GATING1_TVD __BIT(1)
|
||||
#define AWIN_AHB_GATING1_VE __BIT(0)
|
||||
|
||||
#define AWIN_APB_GATING0_KEYPAD __BIT(10)
|
||||
#define AWIN_APB_GATING0_IIS2 __BIT(8)
|
||||
|
|
@ -505,35 +505,48 @@
|
|||
#define AWIN_DRAM_CLK_CSI0_DCLK_ENABLE __BIT(1)
|
||||
#define AWIN_DRAM_CLK_VE_DCLK_ENABLE __BIT(0)
|
||||
|
||||
#define AWIN_GMAC_CLK_TXC_DIV __BITS(9,8)
|
||||
#define AWIN_GMAC_CLK_TXC_DIV_1000 0
|
||||
#define AWIN_GMAC_CLK_TXC_DIV_100 1
|
||||
#define AWIN_GMAC_CLK_TXC_DIV_10 2
|
||||
#define AWIN_GMAC_CLK_RXDC __BITS(7,5)
|
||||
#define AWIN_GMAC_CLK_RXIE __BIT(4)
|
||||
#define AWIN_GMAC_CLK_TXIE __BIT(3)
|
||||
#define AWIN_GMAC_CLK_PIT __BIT(2)
|
||||
#define AWIN_GMAC_CLK_TCS __BITS(1,0)
|
||||
#define AWIN_GMAC_CLK_TCS_MII 0
|
||||
#define AWIN_GMAC_CLK_TCS_EXT_125 1
|
||||
#define AWIN_GMAC_CLK_TCS_INT_RGMII 2
|
||||
#define AWIN_GMAC_CLK_TXC_DIV __BITS(9,8)
|
||||
#define AWIN_GMAC_CLK_TXC_DIV_1000 0
|
||||
#define AWIN_GMAC_CLK_TXC_DIV_100 1
|
||||
#define AWIN_GMAC_CLK_TXC_DIV_10 2
|
||||
#define AWIN_GMAC_CLK_RXDC __BITS(7,5)
|
||||
#define AWIN_GMAC_CLK_RXIE __BIT(4)
|
||||
#define AWIN_GMAC_CLK_TXIE __BIT(3)
|
||||
#define AWIN_GMAC_CLK_PIT __BIT(2)
|
||||
#define AWIN_GMAC_CLK_TCS __BITS(1,0)
|
||||
#define AWIN_GMAC_CLK_TCS_MII 0
|
||||
#define AWIN_GMAC_CLK_TCS_EXT_125 1
|
||||
#define AWIN_GMAC_CLK_TCS_INT_RGMII 2
|
||||
|
||||
#define AWIN_CLK_OUT_ENABLE __BIT(31)
|
||||
#define AWIN_CLK_OUT_SRC_SEL __BITS(25,24)
|
||||
#define AWIN_CLK_OUT_SRC_SEL_32K 0
|
||||
#define AWIN_CLK_OUT_SRC_SEL_LOSC 1
|
||||
#define AWIN_CLK_OUT_SRC_SEL_OSC24M 2
|
||||
#define AWIN_CLK_OUT_SRC_FACTOR_N __BITS(21,20)
|
||||
#define AWIN_CLK_OUT_SRC_FACTOR_M __BITS(12,8)
|
||||
#define AWIN_CLK_OUT_ENABLE __BIT(31)
|
||||
#define AWIN_CLK_OUT_SRC_SEL __BITS(25,24)
|
||||
#define AWIN_CLK_OUT_SRC_SEL_32K 0
|
||||
#define AWIN_CLK_OUT_SRC_SEL_LOSC 1
|
||||
#define AWIN_CLK_OUT_SRC_SEL_OSC24M 2
|
||||
#define AWIN_CLK_OUT_SRC_FACTOR_N __BITS(21,20)
|
||||
#define AWIN_CLK_OUT_SRC_FACTOR_M __BITS(12,8)
|
||||
|
||||
/* USB device offsets */
|
||||
#define AWIN_EHCI_OFFSET 0x0000
|
||||
#define AWIN_EHCI_SIZE 0x0400
|
||||
#define AWIN_OHCI_OFFSET 0x0400
|
||||
#define AWIN_OHCI_SIZE 0x0400
|
||||
#define AWIN_USB0_PHY_CSR_REG 0x0404
|
||||
#define AWIN_EHCI_OFFSET 0x0000
|
||||
#define AWIN_EHCI_SIZE 0x0400
|
||||
#define AWIN_OHCI_OFFSET 0x0400
|
||||
#define AWIN_OHCI_SIZE 0x0400
|
||||
#define AWIN_USB_PMU_IRQ_REG 0x0800
|
||||
|
||||
#define AWIN_USB0_PHY_CSR_ADDR __BITS(15,8)
|
||||
#define AWIN_USB0_PHY_CSR_DAT __BIT(7)
|
||||
#define AWIN_USB0_PHY_CSR_CLK2 __BIT(2)
|
||||
#define AWIN_USB0_PHY_CSR_CLK1 __BIT(1)
|
||||
#define AWIN_USB0_PHY_CSR_CLK0 __BIT(0)
|
||||
|
||||
#define AWIN_USB_PMU_IRQ_AHB_INCR8 __BIT(10)
|
||||
#define AWIN_USB_PMU_IRQ_AHB_INCR4 __BIT(9)
|
||||
#define AWIN_USB_PMU_IRQ_AHB_INCRX __BIT(8)
|
||||
#define AWIN_USB_PMU_IRQ_ULPI_BYPASS __BIT(0)
|
||||
|
||||
/* PATA Definitions */
|
||||
#define AWIN_PATA_CTL_REG 0x0100 /* XXX Bogus */
|
||||
#define AWIN_PATA_CTL_REG 0x0100 /* XXX Bogus */
|
||||
|
||||
/* A10 Interrupt Register Definitions */
|
||||
#define AWIN_INTC_VECTOR_REG 0x0000
|
||||
|
|
@ -576,7 +589,7 @@
|
|||
#define AWIN_PIO_DRV1_REG 0x0018
|
||||
#define AWIN_PIO_PUL0_REG 0x001c
|
||||
#define AWIN_PIO_PUL1_REG 0x0020
|
||||
#define AWIN_PIO_GRP_SIZE 0x0024
|
||||
#define AWIN_PIO_GRP_SIZE 0x0024
|
||||
#define AWIN_PIO_INT_CFG0_REG 0x0200
|
||||
#define AWIN_PIO_INT_CFG1_REG 0x0204
|
||||
#define AWIN_PIO_INT_CFG2_REG 0x0208
|
||||
|
|
@ -588,10 +601,15 @@
|
|||
#define AWIN_PIO_SDR_PAD_PUL_REG 0x0224
|
||||
|
||||
#define AWIN_PIO_CFG_PINMASK(pin) (7 << (4*((pin) & 7)))
|
||||
#define AWIN_PIO_DRV_MASK(pin) ((x) << (2*((pin) & 15)))
|
||||
#define AWIN_PIO_DRV_MASK(pin) ((x) << (2*((pin) & 15)))
|
||||
#define AWIN_PIO_PULn(v, pin) ((v) << (2*((pin) & 15)))
|
||||
|
||||
#define AWIN_PIO_FUNC_INPUT 0x0
|
||||
#define AWIN_PIO_FUNC_OUTPUT 0x0
|
||||
#define AWIN_PIO_FUNC_OUTPUT 0x1
|
||||
|
||||
#define AWIN_PIO_PULL_NONE 0x0
|
||||
#define AWIN_PIO_PULL_UP 0x1
|
||||
#define AWIN_PIO_PULL_DOWN 0x2
|
||||
|
||||
#define AWIN_PIO_EINT_POSITIVE_EDGE 0x0
|
||||
#define AWIN_PIO_EINT_NEGATIVE_EDGE 0x1
|
||||
|
|
@ -893,8 +911,8 @@
|
|||
#define AWIN_LOSC_CNT64_LOW_REG 0x0294
|
||||
#define AWIN_LOSC_CNT64_HIGH_REG 0x0298
|
||||
|
||||
#define AWIN_CPU_CORE_RESET __BIT(1)
|
||||
#define AWIN_CPU_RESET __BIT(0)
|
||||
#define AWIN_CPU_CORE_RESET __BIT(1)
|
||||
#define AWIN_CPU_RESET __BIT(0)
|
||||
|
||||
/* High Speed Timer (A20) */
|
||||
#define AWIN_HSTMR_IRQ_EN_REG 0x0000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: awin_var.h,v 1.5 2013/09/07 02:10:02 matt Exp $ */
|
||||
/* $NetBSD: awin_var.h,v 1.6 2013/09/07 19:47:28 matt Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2013 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
|
|
@ -33,6 +33,9 @@
|
|||
|
||||
#include <sys/types.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/gpio.h>
|
||||
|
||||
#include <dev/gpio/gpiovar.h>
|
||||
|
||||
struct awin_locators {
|
||||
const char *loc_name;
|
||||
|
|
@ -63,6 +66,11 @@ struct awin_gpio_pinset {
|
|||
uint32_t pinset_mask;
|
||||
};
|
||||
|
||||
struct awin_gpio_pindata {
|
||||
gpio_chipset_tag_t pd_gc;
|
||||
int pd_pin;
|
||||
};
|
||||
|
||||
extern struct bus_space awin_bs_tag;
|
||||
extern struct bus_space awin_a4x_bs_tag;
|
||||
extern bus_space_handle_t awin_core_bsh;
|
||||
|
|
@ -76,9 +84,16 @@ void awin_gpio_init(void);
|
|||
bool awin_gpio_pinset_available(const struct awin_gpio_pinset *);
|
||||
void awin_gpio_pinset_acquire(const struct awin_gpio_pinset *);
|
||||
void awin_gpio_pinset_release(const struct awin_gpio_pinset *);
|
||||
bool awin_gpio_pin_reserve(const char *, struct awin_gpio_pindata *);
|
||||
|
||||
void awin_wdog_reset(void);
|
||||
|
||||
static inline void
|
||||
awin_gpio_pindata_write(const struct awin_gpio_pindata *pd, int value)
|
||||
{
|
||||
gpiobus_pin_write(pd->pd_gc, pd->pd_pin, value);
|
||||
}
|
||||
|
||||
static void inline
|
||||
awin_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh,
|
||||
bus_size_t o, uint32_t set_mask, uint32_t clr_mask)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: cubie_machdep.c,v 1.5 2013/09/07 03:34:20 matt Exp $ */
|
||||
/* $NetBSD: cubie_machdep.c,v 1.6 2013/09/07 19:47:28 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Machine dependent functions for kernel setup for TI OSK5912 board.
|
||||
|
|
@ -125,7 +125,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: cubie_machdep.c,v 1.5 2013/09/07 03:34:20 matt Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: cubie_machdep.c,v 1.6 2013/09/07 19:47:28 matt Exp $");
|
||||
|
||||
#include "opt_machdep.h"
|
||||
#include "opt_ddb.h"
|
||||
|
|
@ -517,14 +517,16 @@ cubie_device_register(device_t self, void *aux)
|
|||
/*
|
||||
* These are GPIOs being used for various functions.
|
||||
*/
|
||||
prop_dictionary_set_cstring(dict, "out-satapwren", "PB8");
|
||||
prop_dictionary_set_cstring(dict, "out-usb0drv", "PB9");
|
||||
prop_dictionary_set_cstring(dict, "out-usb1drv", "PH6");
|
||||
prop_dictionary_set_cstring(dict, "out-usb2drv", "PH3");
|
||||
prop_dictionary_set_cstring(dict, "out-hdd5ven", "PH17");
|
||||
prop_dictionary_set_cstring(dict, "out-emacpwren", "PH19");
|
||||
prop_dictionary_set_cstring(dict, "out-status-led1", "PH21");
|
||||
prop_dictionary_set_cstring(dict, "out-status-led2", "PH20");
|
||||
prop_dictionary_set_cstring(dict, "satapwren", ">PB8");
|
||||
prop_dictionary_set_cstring(dict, "usb0drv", ">PB9");
|
||||
prop_dictionary_set_cstring(dict, "usb2drv", ">PH3");
|
||||
prop_dictionary_set_cstring(dict, "usb0iddet", "<PH4");
|
||||
prop_dictionary_set_cstring(dict, "usb0vbusdet", "<PH5");
|
||||
prop_dictionary_set_cstring(dict, "usb1drv", ">PH6");
|
||||
prop_dictionary_set_cstring(dict, "hdd5ven", ">PH17");
|
||||
prop_dictionary_set_cstring(dict, "emacpwren", ">PH19");
|
||||
prop_dictionary_set_cstring(dict, "status-led1", ">PH21");
|
||||
prop_dictionary_set_cstring(dict, "status-led2", ">PH20");
|
||||
|
||||
/*
|
||||
* These pins have no connections.
|
||||
|
|
|
|||
Loading…
Reference in New Issue