Add driver for Zynq GPIO controller.
This commit is contained in:
jmcneill
parent
7b82144285
commit
c5633092fc
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@ -1,4 +1,4 @@
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# $NetBSD: files.zynq,v 1.3 2022/10/26 10:55:23 jmcneill Exp $
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# $NetBSD: files.zynq,v 1.4 2022/10/27 09:41:28 jmcneill Exp $
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#
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# Configuration info for Xilinx Zynq-7000 SoC
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#
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@ -10,16 +10,16 @@ file arch/arm/xilinx/zynq_platform.c soc_zynq
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defflag opt_soc.h SOC_ZYNQ
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defflag opt_soc.h SOC_ZYNQ7000: SOC_ZYNQ
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# System Level Control Module
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#device zynqslcr
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#attach zynqslcr at fdt
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#file arch/arm/xilinx/zynq_slcr.c zynqslcr needs-flag
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# PS clock subsystem
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device zynqclk
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attach zynqclk at fdt with zynq7000_clkc
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file arch/arm/xilinx/zynq7000_clkc.c zynq7000_clkc
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# GPIO
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device zynqgpio: gpiobus
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attach zynqgpio at fdt
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file arch/arm/xilinx/zynq_gpio.c zynqgpio
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# UART
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device zynquart
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attach zynquart at fdt
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@ -0,0 +1,292 @@
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/* $NetBSD: zynq_gpio.c,v 1.1 2022/10/27 09:41:28 jmcneill Exp $ */
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/*-
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* Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: zynq_gpio.c,v 1.1 2022/10/27 09:41:28 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bitops.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/gpio.h>
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#include <sys/intr.h>
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#include <sys/kmem.h>
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#include <sys/lwp.h>
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#include <sys/mutex.h>
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#include <sys/systm.h>
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#include <dev/fdt/fdtvar.h>
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#include <dev/gpio/gpiovar.h>
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#define ZYNQ_GPIO_NPINS (4 * 32)
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#define MASK_DATA_REG(pin) (0x000 + 0x4 * ((pin) / 16))
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#define MASK_DATA_SET(pin, val) ((((pin) % 16) << 16) | ((val) << ((pin) % 16)))
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#define DATA_RO_REG(pin) (0x060 + 0x4 * ((pin) / 32))
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#define DATA_RO_BIT(pin) ((pin) % 32)
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#define DIRM_REG(pin) (0x204 + 0x40 * ((pin) / 32))
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#define DIRM_BIT(pin) ((pin) % 32)
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#define OEN_REG(pin) (0x208 + 0x40 * ((pin) / 32))
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#define OEN_BIT(pin) ((pin) % 32)
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static const struct device_compatible_entry compat_data[] = {
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{ .compat = "xlnx,zynq-gpio-1.0" },
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DEVICE_COMPAT_EOL
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};
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struct zynq_gpio_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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kmutex_t sc_lock;
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struct gpio_chipset_tag sc_gp;
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gpio_pin_t sc_pins[ZYNQ_GPIO_NPINS];
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device_t sc_gpiodev;
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};
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struct zynq_gpio_pin {
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struct zynq_gpio_softc *pin_sc;
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u_int pin_nr;
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int pin_flags;
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bool pin_actlo;
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};
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#define RD4(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define WR4(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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static int zynq_gpio_match(device_t, cfdata_t, void *);
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static void zynq_gpio_attach(device_t, device_t, void *);
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static int zynq_gpio_pin_read(void *, int);
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static void zynq_gpio_pin_write(void *, int, int);
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CFATTACH_DECL_NEW(zynqgpio, sizeof(struct zynq_gpio_softc),
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zynq_gpio_match, zynq_gpio_attach, NULL, NULL);
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static int
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zynq_gpio_ctl(struct zynq_gpio_softc *sc, u_int pin, int flags)
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{
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uint32_t val;
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KASSERT(mutex_owned(&sc->sc_lock));
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val = RD4(sc, OEN_REG(pin));
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if ((flags & GPIO_PIN_INPUT) != 0) {
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val &= ~OEN_BIT(pin);
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} else if ((flags & GPIO_PIN_OUTPUT) != 0) {
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val |= OEN_BIT(pin);
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}
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WR4(sc, OEN_REG(pin), val);
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return 0;
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}
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static void *
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zynq_gpio_acquire(device_t dev, const void *data, size_t len, int flags)
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{
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struct zynq_gpio_softc * const sc = device_private(dev);
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struct zynq_gpio_pin *gpin;
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const u_int *gpio = data;
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int error;
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if (len != 12)
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return NULL;
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const uint8_t pin = be32toh(gpio[1]) & 0xff;
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const bool actlo = be32toh(gpio[2]) & 1;
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if (pin >= __arraycount(sc->sc_pins))
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return NULL;
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mutex_enter(&sc->sc_lock);
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error = zynq_gpio_ctl(sc, pin, flags);
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mutex_exit(&sc->sc_lock);
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if (error != 0)
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return NULL;
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gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP);
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gpin->pin_sc = sc;
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gpin->pin_nr = pin;
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gpin->pin_flags = flags;
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gpin->pin_actlo = actlo;
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return gpin;
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}
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static void
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zynq_gpio_release(device_t dev, void *priv)
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{
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struct zynq_gpio_softc * const sc = device_private(dev);
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struct zynq_gpio_pin *pin = priv;
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mutex_enter(&sc->sc_lock);
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zynq_gpio_ctl(pin->pin_sc, pin->pin_nr, GPIO_PIN_INPUT);
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mutex_exit(&sc->sc_lock);
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kmem_free(pin, sizeof(*pin));
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}
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static int
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zynq_gpio_read(device_t dev, void *priv, bool raw)
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{
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struct zynq_gpio_softc * const sc = device_private(dev);
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struct zynq_gpio_pin *pin = priv;
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int val;
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KASSERT(sc == pin->pin_sc);
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val = zynq_gpio_pin_read(sc, pin->pin_nr);
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if (!raw && pin->pin_actlo)
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val = !val;
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return val;
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}
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static void
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zynq_gpio_write(device_t dev, void *priv, int val, bool raw)
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{
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struct zynq_gpio_softc * const sc = device_private(dev);
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struct zynq_gpio_pin *pin = priv;
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KASSERT(sc == pin->pin_sc);
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if (!raw && pin->pin_actlo)
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val = !val;
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zynq_gpio_pin_write(sc, pin->pin_nr, val);
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}
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static struct fdtbus_gpio_controller_func zynq_gpio_funcs = {
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.acquire = zynq_gpio_acquire,
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.release = zynq_gpio_release,
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.read = zynq_gpio_read,
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.write = zynq_gpio_write,
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};
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static int
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zynq_gpio_pin_read(void *priv, int pin)
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{
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struct zynq_gpio_softc * const sc = priv;
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uint32_t data;
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int val;
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KASSERT(pin < __arraycount(sc->sc_pins));
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data = RD4(sc, DATA_RO_REG(pin));
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val = __SHIFTOUT(data, DATA_RO_BIT(pin));
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return val;
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}
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static void
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zynq_gpio_pin_write(void *priv, int pin, int val)
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{
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struct zynq_gpio_softc * const sc = priv;
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KASSERT(pin < __arraycount(sc->sc_pins));
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WR4(sc, MASK_DATA_REG(pin), MASK_DATA_SET(pin, val));
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}
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static void
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zynq_gpio_pin_ctl(void *priv, int pin, int flags)
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{
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struct zynq_gpio_softc * const sc = priv;
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KASSERT(pin < __arraycount(sc->sc_pins));
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mutex_enter(&sc->sc_lock);
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zynq_gpio_ctl(sc, pin, flags);
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mutex_exit(&sc->sc_lock);
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}
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static void
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zynq_gpio_attach_ports(struct zynq_gpio_softc *sc)
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{
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struct gpio_chipset_tag *gp = &sc->sc_gp;
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struct gpiobus_attach_args gba;
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u_int pin;
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gp->gp_cookie = sc;
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gp->gp_pin_read = zynq_gpio_pin_read;
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gp->gp_pin_write = zynq_gpio_pin_write;
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gp->gp_pin_ctl = zynq_gpio_pin_ctl;
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for (pin = 0; pin < __arraycount(sc->sc_pins); pin++) {
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sc->sc_pins[pin].pin_num = pin;
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sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
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sc->sc_pins[pin].pin_state = zynq_gpio_pin_read(sc, pin);
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}
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memset(&gba, 0, sizeof(gba));
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gba.gba_gc = gp;
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gba.gba_pins = sc->sc_pins;
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gba.gba_npins = __arraycount(sc->sc_pins);
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sc->sc_gpiodev = config_found(sc->sc_dev, &gba, NULL, CFARGS_NONE);
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}
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static int
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zynq_gpio_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_compatible_match(faa->faa_phandle, compat_data);
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}
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static void
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zynq_gpio_attach(device_t parent, device_t self, void *aux)
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{
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struct zynq_gpio_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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const int phandle = faa->faa_phandle;
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bus_addr_t addr;
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bus_size_t size;
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if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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return;
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}
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sc->sc_dev = self;
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sc->sc_bst = faa->faa_bst;
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if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
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aprint_error(": couldn't map registers\n");
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return;
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}
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mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
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aprint_naive("\n");
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aprint_normal(": XGPIOPS\n");
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fdtbus_register_gpio_controller(self, phandle, &zynq_gpio_funcs);
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zynq_gpio_attach_ports(sc);
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}
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@ -1,5 +1,5 @@
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#
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# $NetBSD: GENERIC,v 1.109 2022/10/25 22:27:49 jmcneill Exp $
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# $NetBSD: GENERIC,v 1.110 2022/10/27 09:41:28 jmcneill Exp $
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#
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# GENERIC ARM (aarch32) kernel
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#
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@ -270,6 +270,7 @@ sunxigpio* at fdt? pass 3 # Allwinner GPIO
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rkgpio* at rkiomux? # Rockchip GPIO
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tegragpio* at fdt? pass 2 # NVIDIA Tegra GPIO
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tigpio* at fdt? pass 2 # TI GPIO
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zynqgpio* at fdt? pass 2 # Xilinx Zynq GPIO
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gpio* at gpiobus?
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# IOMUX / MPIO / Pinmux
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