diff --git a/sys/arch/x86/include/specialreg.h b/sys/arch/x86/include/specialreg.h index 371e66fcdeac..b3a1b9f06f8a 100644 --- a/sys/arch/x86/include/specialreg.h +++ b/sys/arch/x86/include/specialreg.h @@ -1,6 +1,32 @@ -/* $NetBSD: specialreg.h,v 1.145 2019/05/14 18:11:34 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.146 2019/05/18 08:17:39 maxv Exp $ */ -/*- +/* + * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* * Copyright (c) 1991 The Regents of the University of California. * All rights reserved. * @@ -32,28 +58,24 @@ */ /* - * Bits in 386 special registers: + * CR0 */ #define CR0_PE 0x00000001 /* Protected mode Enable */ #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ -#define CR0_PG 0x80000000 /* PaGing enable */ - -/* - * Bits in 486 special registers: - */ #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ #define CR0_WP 0x00010000 /* Write Protect (honor PTE_W in all modes) */ #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ #define CR0_NW 0x20000000 /* Not Write-through */ #define CR0_CD 0x40000000 /* Cache Disable */ +#define CR0_PG 0x80000000 /* PaGing enable */ /* - * Cyrix 486 DLC special registers, accessible as IO ports. + * Cyrix 486 DLC special registers, accessible as IO ports */ -#define CCR0 0xc0 /* configuration control register 0 */ +#define CCR0 0xc0 /* configuration control register 0 */ #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ #define CCR0_A20M 0x04 /* enables A20M# input pin */ @@ -62,13 +84,11 @@ #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ - -#define CCR1 0xc1 /* configuration control register 1 */ +#define CCR1 0xc1 /* configuration control register 1 */ #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ -/* the remaining 7 bits of this register are reserved */ /* - * bits in the %cr4 control register: + * CR4 */ #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ @@ -102,21 +122,22 @@ #define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */ #define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */ #define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */ - -/* - * Known fpu bits - only these get enabled. The save area is sized for all the - * fields below (max 2680 bytes). - */ -#define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ - XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) - -#define XCR0_BND (XCR0_BNDREGS | XCR0_BNDCSR) +#define XCR0_PT 0x00000100 /* Processor Trace state */ +#define XCR0_PKRU 0x00000200 /* Protection Key state */ +#define XCR0_HDC 0x00002000 /* Hardware Duty Cycle state */ #define XCR0_FLAGS1 "\20" \ - "\1" "x87" "\2" "SSE" "\3" "AVX" \ - "\4" "BNDREGS" "\5" "BNDCSR" \ - "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" + "\1" "x87" "\2" "SSE" "\3" "AVX" \ + "\4" "BNDREGS" "\5" "BNDCSR" "\6" "Opmask" \ + "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" "\11" "PT" \ + "\12" "PKRU" "\16" "HDC" +/* + * Known FPU bits, only these get enabled. The save area is sized for all the + * fields below. + */ +#define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ + XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) /* * CPUID "features" bits @@ -168,11 +189,10 @@ /* Blacklists of CPUID flags - used to mask certain features */ #ifdef XENPV -/* Not on Xen */ #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) #else #define CPUID_FEAT_BLACKLIST 0 -#endif /* XENPV */ +#endif /* * CPUID "features" bits in Fn00000001 %ecx @@ -351,12 +371,12 @@ /* %ebx */ #define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */ #define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */ -#define CPUID_SEF_SGX __BIT(2) /* Software Guard Extentions */ +#define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */ #define CPUID_SEF_BMI1 __BIT(3) /* advanced bit manipulation ext. 1st grp */ #define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */ #define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */ #define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */ -#define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Excecution Prevention */ +#define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */ #define CPUID_SEF_BMI2 __BIT(8) /* advanced bit manipulation ext. 2nd grp */ #define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */ #define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */ @@ -703,14 +723,9 @@ "\15" "RSA" /* - * Model-specific registers for the i386 family + * Model-Specific Registers */ -#define MSR_P5_MC_ADDR 0x000 /* P5 only */ -#define MSR_P5_MC_TYPE 0x001 /* P5 only */ #define MSR_TSC 0x010 -#define MSR_CESR 0x011 /* P5 only (trap on P6) */ -#define MSR_CTR0 0x012 /* P5 only (trap on P6) */ -#define MSR_CTR1 0x013 /* P5 only (trap on P6) */ #define MSR_IA32_PLATFORM_ID 0x017 #define MSR_APICBASE 0x01b #define APICBASE_BSP 0x00000100 /* boot processor */ @@ -724,7 +739,6 @@ #define APICBASE_PHYSADDR 0xfffff000 /* physical address */ #define MSR_EBL_CR_POWERON 0x02a #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ -#define MSR_TEST_CTL 0x033 #define MSR_IA32_SPEC_CTRL 0x048 #define IA32_SPEC_CTRL_IBRS 0x01 #define IA32_SPEC_CTRL_STIBP 0x02 @@ -732,9 +746,6 @@ #define MSR_IA32_PRED_CMD 0x049 #define IA32_PRED_CMD_IBPB 0x01 #define MSR_BIOS_UPDT_TRIG 0x079 -#define MSR_BBL_CR_D0 0x088 /* PII+ only */ -#define MSR_BBL_CR_D1 0x089 /* PII+ only */ -#define MSR_BBL_CR_D2 0x08a /* PII+ only */ #define MSR_BIOS_SIGN 0x08b #define MSR_PERFCTR0 0x0c1 #define MSR_PERFCTR1 0x0c2 @@ -753,12 +764,6 @@ #define MSR_IA32_FLUSH_CMD 0x10b #define IA32_FLUSH_CMD_L1D_FLUSH 0x01 #define MSR_TSX_FORCE_ABORT 0x10f -#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ -#define MSR_BBL_CR_DECC 0x118 /* PII+ only */ -#define MSR_BBL_CR_CTL 0x119 /* PII+ only */ -#define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ -#define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ -#define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ #define MSR_SYSENTER_CS 0x174 /* PII+ only */ #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ #define MSR_SYSENTER_EIP 0x176 /* PII+ only */