From c3f116d3b1d1361648b6d84df8396a28d850c63f Mon Sep 17 00:00:00 2001 From: jmcneill Date: Thu, 12 Dec 2019 00:45:59 +0000 Subject: [PATCH] Add support for snps,dis-tx-ipgap-linecheck-quirk quirk --- sys/dev/fdt/dwc3_fdt.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/sys/dev/fdt/dwc3_fdt.c b/sys/dev/fdt/dwc3_fdt.c index ef64f0ab2466..1e48765ad1fd 100644 --- a/sys/dev/fdt/dwc3_fdt.c +++ b/sys/dev/fdt/dwc3_fdt.c @@ -1,4 +1,4 @@ -/* $NetBSD: dwc3_fdt.c,v 1.7 2019/04/19 19:05:56 jmcneill Exp $ */ +/* $NetBSD: dwc3_fdt.c,v 1.8 2019/12/12 00:45:59 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: dwc3_fdt.c,v 1.7 2019/04/19 19:05:56 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dwc3_fdt.c,v 1.8 2019/12/12 00:45:59 jmcneill Exp $"); #include #include @@ -52,6 +52,9 @@ __KERNEL_RCSID(0, "$NetBSD: dwc3_fdt.c,v 1.7 2019/04/19 19:05:56 jmcneill Exp $" #define GCTL_PRTCAP_OTG 3 #define GCTL_CORESOFTRESET __BIT(11) +#define DWC3_GUCTL1 0xc11c +#define GUCTL1_TX_IPGAP_LINECHECK_DIS __BIT(28) + #define DWC3_SNPSID 0xc120 #define DWC3_SNPSID_REV __BITS(15,0) @@ -120,7 +123,7 @@ dwc3_fdt_soft_reset(struct xhci_softc *sc) } static void -dwc3_fdt_enable_phy(struct xhci_softc *sc, const int phandle) +dwc3_fdt_enable_phy(struct xhci_softc *sc, const int phandle, u_int rev) { const char *max_speed, *phy_type; u_int phyif_utmi_bits; @@ -162,6 +165,13 @@ dwc3_fdt_enable_phy(struct xhci_softc *sc, const int phandle) val &= ~GUSB3PIPECTL_DEPOCHANGE; WR4(sc, DWC3_GUSB3PIPECTL(0), val); + if (rev >= 0x250a) { + val = RD4(sc, DWC3_GUCTL1); + if (of_hasprop(phandle, "snps,dis-tx-ipgap-linecheck-quirk")) + val |= GUCTL1_TX_IPGAP_LINECHECK_DIS; + WR4(sc, DWC3_GUCTL1, val); + } + max_speed = fdtbus_get_string(phandle, "maximum-speed"); if (max_speed == NULL) max_speed = "super-speed"; @@ -279,7 +289,7 @@ dwc3_fdt_attach(device_t parent, device_t self, void *aux) } dwc3_fdt_soft_reset(sc); - dwc3_fdt_enable_phy(sc, dwc3_phandle); + dwc3_fdt_enable_phy(sc, dwc3_phandle, rev); dwc3_fdt_set_mode(sc, GCTL_PRTCAP_HOST); if (!fdtbus_intr_str(dwc3_phandle, 0, intrstr, sizeof(intrstr))) {