Add support for the AMD 756 DMA/UDMA IDE controller, provided in
PR kern/9536 by Dave Sainty.
This commit is contained in:
bouyer
parent
1d15b87bc1
commit
c34cce88c4
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@ -1,4 +1,4 @@
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/* $NetBSD: pciide.c,v 1.52 2000/01/18 13:58:07 bouyer Exp $ */
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/* $NetBSD: pciide.c,v 1.53 2000/03/06 18:02:26 bouyer Exp $ */
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/*
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@ -109,6 +109,7 @@ int wdcdebug_pciide_mask = 0;
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_piix_reg.h>
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#include <dev/pci/pciide_amd_reg.h>
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#include <dev/pci/pciide_apollo_reg.h>
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#include <dev/pci/pciide_cmd_reg.h>
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#include <dev/pci/pciide_cy693_reg.h>
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@ -157,6 +158,9 @@ static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t));
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static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*));
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static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t));
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void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
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void amd756_setup_channel __P((struct channel_softc*));
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void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
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void apollo_setup_channel __P((struct channel_softc*));
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@ -244,6 +248,18 @@ const struct pciide_product_desc pciide_intel_products[] = {
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}
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};
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const struct pciide_product_desc pciide_amd_products[] = {
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{ PCI_PRODUCT_AMD_PBC756_IDE,
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0,
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"Advanced Micro Devices AMD756 IDE Controller",
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amd756_chip_map
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},
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{ 0,
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0,
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NULL,
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}
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};
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const struct pciide_product_desc pciide_cmd_products[] = {
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{ PCI_PRODUCT_CMDTECH_640,
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0,
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@ -349,6 +365,7 @@ const struct pciide_vendor_desc pciide_vendors[] = {
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{ PCI_VENDOR_SIS, pciide_sis_products },
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{ PCI_VENDOR_ALI, pciide_acer_products },
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{ PCI_VENDOR_PROMISE, pciide_promise_products },
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{ PCI_VENDOR_AMD, pciide_amd_products },
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{ 0, NULL }
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};
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@ -1603,6 +1620,142 @@ piix_setup_sidetim_timings(mode, dma, channel)
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PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel);
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}
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void
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amd756_chip_map(sc, pa)
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struct pciide_softc *sc;
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struct pci_attach_args *pa;
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{
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struct pciide_channel *cp;
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pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc,
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sc->sc_tag, PCI_CLASS_REG));
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int channel;
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pcireg_t chanenable;
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bus_size_t cmdsize, ctlsize;
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if (pciide_chipen(sc, pa) == 0)
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return;
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printf("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_dev.dv_xname);
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pciide_mapreg_dma(sc, pa);
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printf("\n");
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if (sc->sc_dma_ok)
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
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WDC_CAPABILITY_MODE;
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sc->sc_wdcdev.PIO_cap = 4;
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sc->sc_wdcdev.DMA_cap = 2;
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sc->sc_wdcdev.UDMA_cap = 4;
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sc->sc_wdcdev.set_modes = amd756_setup_channel;
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sc->sc_wdcdev.channels = sc->wdc_chanarray;
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sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
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chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN);
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WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable),
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DEBUG_PROBE);
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for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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if ((chanenable & AMD756_CHAN_EN(channel)) == 0) {
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printf("%s: %s channel ignored (disabled)\n",
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sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
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continue;
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}
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pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
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pciide_pci_intr);
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if (pciiide_chan_candisable(cp))
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chanenable &= ~AMD756_CHAN_EN(channel);
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pciide_map_compat_intr(pa, cp, channel, interface);
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if (cp->hw_ok == 0)
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continue;
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amd756_setup_channel(&cp->wdc_channel);
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}
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pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN,
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chanenable);
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return;
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}
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void
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amd756_setup_channel(chp)
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struct channel_softc *chp;
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{
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u_int32_t udmatim_reg, datatim_reg;
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u_int8_t idedma_ctl;
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int mode, drive;
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struct ata_drive_datas *drvp;
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struct pciide_channel *cp = (struct pciide_channel*)chp;
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struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
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idedma_ctl = 0;
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datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM);
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udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA);
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datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel);
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udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel);
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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/* add timing values, setup DMA if needed */
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if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
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(drvp->drive_flags & DRIVE_UDMA) == 0)) {
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mode = drvp->PIO_mode;
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goto pio;
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}
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if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) &&
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(drvp->drive_flags & DRIVE_UDMA)) {
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/* use Ultra/DMA */
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drvp->drive_flags &= ~DRIVE_DMA;
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udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) |
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AMD756_UDMA_EN_MTH(chp->channel, drive) |
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AMD756_UDMA_TIME(chp->channel, drive,
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amd756_udma_tim[drvp->UDMA_mode]);
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/* can use PIO timings, MW DMA unused */
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mode = drvp->PIO_mode;
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} else {
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/* use Multiword DMA */
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drvp->drive_flags &= ~DRIVE_UDMA;
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/* mode = min(pio, dma+2) */
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if (drvp->PIO_mode <= (drvp->DMA_mode +2))
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mode = drvp->PIO_mode;
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else
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mode = drvp->DMA_mode + 2;
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}
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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pio: /* setup PIO mode */
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if (mode <= 2) {
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drvp->DMA_mode = 0;
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drvp->PIO_mode = 0;
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mode = 0;
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} else {
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drvp->PIO_mode = mode;
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drvp->DMA_mode = mode - 2;
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}
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datatim_reg |=
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AMD756_DATATIM_PULSE(chp->channel, drive,
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amd756_pio_set[mode]) |
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AMD756_DATATIM_RECOV(chp->channel, drive,
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amd756_pio_rec[mode]);
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}
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if (idedma_ctl != 0) {
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/* Add software bits in status register */
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bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
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IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel),
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idedma_ctl);
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}
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pciide_print_modes(cp);
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pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg);
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pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg);
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}
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void
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apollo_chip_map(sc, pa)
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struct pciide_softc *sc;
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@ -0,0 +1,66 @@
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/* $NetBSD: pciide_amd_reg.h,v 1.1 2000/03/06 18:02:27 bouyer Exp $ */
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/*
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* Copyright (c) 2000 David Sainty.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Registers definitions for AMD 756 PCI IDE controller. Documentation
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* available at: http://www.amd.com/products/cpg/athlon/techdocs/pdf/22548.pdf
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*/
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/* Channel enable */
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#define AMD756_CHANSTATUS_EN 0x40
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#define AMD756_CHAN_EN(chan) (0x01 << (1 - (chan)))
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/* Data port timing controls */
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#define AMD756_DATATIM 0x48
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#define AMD756_DATATIM_MASK(channel) (0xffff << ((1 - (channel)) << 4))
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#define AMD756_DATATIM_RECOV(channel, drive, x) (((x) & 0xf) << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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#define AMD756_DATATIM_PULSE(channel, drive, x) (((x) & 0xf) << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3) + 4))
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static const int8_t amd756_pio_set[] = {0x0a, 0x0a, 0x0a, 0x02, 0x02};
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static const int8_t amd756_pio_rec[] = {0x08, 0x08, 0x08, 0x02, 0x00};
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/* Ultra-DMA/33 control */
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#define AMD756_UDMA 0x50
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#define AMD756_UDMA_MASK(channel) (0xffff << ((1 - (channel)) << 4))
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#define AMD756_UDMA_TIME(channel, drive, x) (((x) & 0x7) << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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#define AMD756_UDMA_EN(channel, drive) (0x40 << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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#define AMD756_UDMA_EN_MTH(channel, drive) (0x80 << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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static const int8_t amd756_udma_tim[] = {0x02, 0x01, 0x00, 0x04, 0x05};
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