- Sweep machdep.c; mostly imported from a development branch. Little
exposure of TC device any more. Correct comments which are no longer feasible. Reorder declarations and definitions. Introduce 'clkread' pointer to pull up model dependent high resolution timer value. Have prom_systype() call. - Place routines for model dependent high resolution timer. - Program IOASIC registers inside os_init() call and nuke ioasic_init().
This commit is contained in:
nisimura
parent
c2e396b2c7
commit
c33ad91e49
@ -1,4 +1,4 @@
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/* $NetBSD: dec_3100.c,v 1.9 1999/04/24 08:01:11 simonb Exp $ */
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/* $NetBSD: dec_3100.c,v 1.10 1999/04/26 09:23:21 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -119,6 +119,8 @@ dec_3100_intr_establish __P((void* cookie, int level,
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int (*handler) __P((intr_arg_t)), intr_arg_t arg));
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void dec_3100_intr_disestablish __P((struct ibus_attach_args *ia));
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extern unsigned nullclkread __P((void));
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extern unsigned (*clkread) __P((void));
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/*
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* Fill in platform struct.
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@ -158,6 +160,9 @@ dec_3100_os_init()
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mcclock_addr = (volatile struct chiptime *)
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MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK);
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);
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/* no high resolution timer circuit; possibly never called */
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clkread = nullclkread;
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}
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@ -239,7 +244,7 @@ dec_3100_intr(mask, pc, statusReg, causeReg)
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}
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/* If clock interrupts were enabled, re-enable them ASAP. */
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splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_3));
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splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_3));
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#if NSII > 0
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if (mask & MIPS_INT_MASK_0) {
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@ -272,8 +277,7 @@ dec_3100_intr(mask, pc, statusReg, causeReg)
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dec_3100_errintr();
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intrcnt[ERROR_INTR]++;
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}
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return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
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MIPS_SR_INT_ENA_CUR);
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return(MIPS_SR_INT_IE | (statusReg & ~causeReg & MIPS_HARD_INT_MASK));
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}
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void
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3max.c,v 1.9 1999/04/24 08:01:11 simonb Exp $ */
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/* $NetBSD: dec_3max.c,v 1.10 1999/04/26 09:23:22 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.9 1999/04/24 08:01:11 simonb Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.10 1999/04/26 09:23:22 nisimura Exp $");
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#include <sys/types.h>
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#include <sys/systm.h>
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@ -114,6 +114,8 @@ void dec_3max_device_register __P((struct device *, void *));
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static void dec_3max_errintr __P((void));
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extern unsigned nullclkread __P((void));
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extern unsigned (*clkread) __P((void));
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/*
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* Fill in platform struct.
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@ -166,8 +168,10 @@ dec_3max_os_init()
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MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK);
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
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}
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/* no high resolution timer circuit; possibly never called */
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clkread = nullclkread;
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}
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/*
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* Initalize the memory system and I/O buses.
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@ -284,7 +288,7 @@ dec_3max_intr(mask, pc, statusReg, causeReg)
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}
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/* If clock interrups were enabled, re-enable them ASAP. */
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splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_1));
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splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_1));
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if (mask & MIPS_INT_MASK_0) {
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static int intr_map[8] = { SLOT0_INTR, SLOT1_INTR, SLOT2_INTR,
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@ -319,8 +323,7 @@ dec_3max_intr(mask, pc, statusReg, causeReg)
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dec_3max_errintr();
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}
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return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
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MIPS_SR_INT_ENA_CUR);
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return(MIPS_SR_INT_IE | (statusReg & ~causeReg & MIPS_HARD_INT_MASK));
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3maxplus.c,v 1.15 1999/04/24 08:01:11 simonb Exp $ */
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/* $NetBSD: dec_3maxplus.c,v 1.16 1999/04/26 09:23:23 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.15 1999/04/24 08:01:11 simonb Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.16 1999/04/26 09:23:23 nisimura Exp $");
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#include <sys/types.h>
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#include <sys/systm.h>
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@ -82,7 +82,6 @@ __KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.15 1999/04/24 08:01:11 simonb Exp
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#include <machine/reg.h>
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#include <machine/intr.h>
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#include <machine/psl.h>
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#include <machine/locore.h> /* wbflush() */
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#include <machine/autoconf.h> /* intr_arg_t */
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#include <machine/sysconf.h>
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@ -121,6 +120,9 @@ void dec_3maxplus_device_register __P((struct device *, void *));
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static void dec_3maxplus_errintr __P ((void));
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void kn03_wbflush __P((void));
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unsigned kn03_clkread __P((void));
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extern unsigned (*clkread) __P((void));
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/*
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* Local declarations
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@ -170,7 +172,7 @@ dec_3maxplus_os_init()
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/* clear any pending memory errors. */
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*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
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wbflush();
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kn03_wbflush();
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/*
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* Reset interrupts.
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@ -189,7 +191,6 @@ dec_3maxplus_os_init()
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MIPS_PHYS_TO_KSEG1(KN03_SYS_CLOCK);
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
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ioasic_init(0);
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/*
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* Initialize interrupts.
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*/
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@ -197,13 +198,24 @@ dec_3maxplus_os_init()
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~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2);
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*(u_int *)IOASIC_REG_IMSK(ioasic_base) = kn03_tc3_imask;
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*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
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wbflush();
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kn03_wbflush();
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*(volatile u_int *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
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*(volatile u_int *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
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#if 0
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*(volatile u_int *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
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*(volatile u_int *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6);
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*(volatile u_int *)(ioasic_base + IOASIC_CSR) = 0x00000f00;
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#endif
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/* XXX hard-reset LANCE */
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*(u_int *)IOASIC_REG_CSR(ioasic_base) |= 0x100;
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*(u_int *)IOASIC_REG_CSR(ioasic_base) |= 0x100;
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/* clear any memory errors from probes */
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*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
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wbflush();
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kn03_wbflush();
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/* 3MAX+ has IOASIC free-running high resolution timer */
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clkread = kn03_clkread;
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}
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@ -501,3 +513,22 @@ dec_3maxplus_errintr()
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/* Send to kn02/kn03 memory subsystem handler */
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dec_mtasic_err(erradr, errsyn);
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}
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void
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kn03_wbflush()
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{
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/* read once IOASIC_INTR */
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__asm __volatile("lw $0,0xbf840000");
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}
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/*
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* TURBOchannel bus-cycle counter provided by IOASIC;
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* Interpolate micro-seconds since the last RTC clock tick. The
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* interpolation base is the copy of the bus cycle-counter taken by
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* the RTC interrupt handler.
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*/
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unsigned
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kn03_clkread()
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{
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return *(u_int32_t *)(ioasic_base + IOASIC_CTR);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3min.c,v 1.13 1999/04/24 08:01:11 simonb Exp $ */
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/* $NetBSD: dec_3min.c,v 1.14 1999/04/26 09:23:23 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.13 1999/04/24 08:01:11 simonb Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.14 1999/04/26 09:23:23 nisimura Exp $");
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#include <sys/types.h>
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@ -83,7 +83,6 @@ __KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.13 1999/04/24 08:01:11 simonb Exp $")
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#include <machine/intr.h>
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#include <machine/reg.h>
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#include <machine/psl.h>
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#include <machine/locore.h> /* wbflush() */
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#include <machine/autoconf.h> /* intr_arg_t */
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#include <machine/sysconf.h>
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@ -131,6 +130,9 @@ void dec_3min_mcclock_cpuspeed __P((volatile struct chiptime *mcclock_addr,
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int clockmask));
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u_long kmin_tc3_imask;
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void kn02ba_wbflush __P((void));
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unsigned kn02ba_clkread __P((void));
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extern unsigned (*clkread) __P((void));
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/*
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* Fill in platform struct.
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@ -164,10 +166,10 @@ dec_3min_bus_reset()
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*/
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*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
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wbflush();
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kn02ba_wbflush();
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*(volatile u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
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wbflush();
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kn02ba_wbflush();
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}
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@ -197,6 +199,13 @@ dec_3min_os_init()
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MIPS_PHYS_TO_KSEG1(KMIN_SYS_CLOCK);
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dec_3min_mcclock_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);
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*(volatile u_int *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
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*(volatile u_int *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
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#if 0
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*(volatile u_int *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
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*(volatile u_int *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6);
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*(volatile u_int *)(ioasic_base + IOASIC_CSR) = 0x00000f00;
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#endif
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/*
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* Initialize interrupts.
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*/
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@ -206,7 +215,7 @@ dec_3min_os_init()
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/* clear any memory errors from probes */
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*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
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wbflush();
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kn02ba_wbflush();
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/*
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* The kmin memory hardware seems to wrap memory addresses
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@ -223,6 +232,9 @@ dec_3min_os_init()
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* (volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK) =
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kmin_tc3_imask |
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(KMIN_IM0 & ~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2));
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/* R4000 3MIN can ultilize on-chip counter */
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clkread = kn02ba_clkread;
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}
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@ -403,8 +415,8 @@ dec_3min_intr(mask, pc, statusReg, causeReg)
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*imaskp = old_mask &
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~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 |
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IOASIC_INTR_LANCE|IOASIC_INTR_SCSI);
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wbflush();
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splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_3));
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kn02ba_wbflush();
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splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_3));
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}
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if (intr_depth > 1)
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@ -431,7 +443,7 @@ dec_3min_intr(mask, pc, statusReg, causeReg)
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*imaskp = old_mask &
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~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 |
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IOASIC_INTR_LANCE|IOASIC_INTR_SCSI);
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wbflush();
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kn02ba_wbflush();
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}
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/* XXX until we know about SPLs of TC options. */
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@ -481,8 +493,8 @@ done:
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intr_depth--;
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*imaskp = old_mask;
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return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
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MIPS_SR_INT_ENA_CUR);
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return(MIPS_SR_INT_IE | (statusReg & ~causeReg & MIPS_HARD_INT_MASK));
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}
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@ -515,10 +527,40 @@ dec_3min_mcclock_cpuspeed(mcclock_addr, clockmask)
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/* Allow only clock interrupts through ioasic. */
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*ioasic_intrmaskp = KMIN_INTR_CLOCK;
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wbflush();
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kn02ba_wbflush();
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mc_cpuspeed(mcclock_addr, clockmask);
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*ioasic_intrmaskp = saved_imask;
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wbflush();
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kn02ba_wbflush();
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}
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void
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kn02ba_wbflush()
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{
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/* read twice IOASIC_INTR register */
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__asm __volatile("lw $0,0xbc040120; lw $0,0xbc040120");
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}
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unsigned
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kn02ba_clkread()
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{
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#ifdef MIPS3
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extern u_int32_t mips3_cycle_count __P((void));
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extern u_long latched_cycle_cnt;
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if (CPUISMIPS3) {
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u_int32_t mips3_cycles;
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mips3_cycles = mips3_cycle_count() - latched_cycle_cnt;
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#if 0
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/* XXX divides take 78 cycles: approximate with * 41/2048 */
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return (mips3_cycles / cpu_mhz);
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#else
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return((mips3_cycles >> 6) + (mips3_cycles >> 8) +
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(mips3_cycles >> 11));
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#endif
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}
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#endif
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return 0;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_5100.c,v 1.5 1999/04/24 08:01:11 simonb Exp $ */
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/* $NetBSD: dec_5100.c,v 1.6 1999/04/26 09:23:22 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -88,6 +88,9 @@ void dec_5100_intr_disestablish __P((struct ibus_attach_args *ia));
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extern void dec_mips1_wbflush __P((void));
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extern unsigned nullclkread __P((void));
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extern unsigned (*clkread) __P((void));
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/*
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* Fill in platform struct.
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@ -132,6 +135,9 @@ dec_5100_os_init()
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mcclock_addr = (volatile struct chiptime *)
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MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK);
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_2);
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/* no high resolution timer circuit; possibly never called */
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clkread = nullclkread;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.138 1999/04/25 03:20:45 simonb Exp $ */
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/* $NetBSD: machdep.c,v 1.139 1999/04/26 09:23:26 nisimura Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -43,12 +43,13 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.138 1999/04/25 03:20:45 simonb Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.139 1999/04/26 09:23:26 nisimura Exp $");
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/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
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#include "fs_mfs.h"
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#include "opt_ddb.h"
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#include "le_ioasic.h" /* XXX will go XXX */
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -65,23 +66,19 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.138 1999/04/25 03:20:45 simonb Exp $")
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#include <sys/mbuf.h>
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#include <sys/msgbuf.h>
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#include <sys/ioctl.h>
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#include <sys/tty.h>
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#include <sys/device.h>
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#include <sys/user.h>
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#include <vm/vm.h>
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#include <sys/sysctl.h>
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#include <sys/mount.h>
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#include <sys/syscallargs.h>
|
||||
#include <sys/kcore.h>
|
||||
|
||||
#include <dev/cons.h>
|
||||
|
||||
#include <vm/vm.h>
|
||||
#include <vm/vm_kern.h>
|
||||
|
||||
#include <uvm/uvm_extern.h>
|
||||
|
||||
#include <ufs/mfs/mfs_extern.h> /* mfs_initminiroot() */
|
||||
#include <sys/sysctl.h>
|
||||
#include <dev/cons.h>
|
||||
|
||||
#include <ufs/mfs/mfs_extern.h> /* mfs_initminiroot() */
|
||||
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/reg.h>
|
||||
@ -91,8 +88,7 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.138 1999/04/25 03:20:45 simonb Exp $")
|
||||
#include <machine/dec_prom.h>
|
||||
#include <machine/sysconf.h>
|
||||
#include <machine/bootinfo.h>
|
||||
#include <mips/locore.h> /* wbflush() */
|
||||
#include <mips/mips/mips_mcclock.h> /* mclock CPU setimation */
|
||||
#include <machine/locore.h>
|
||||
|
||||
#ifdef DDB
|
||||
#include <sys/exec_aout.h> /* XXX backwards compatilbity for DDB */
|
||||
@ -100,20 +96,12 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.138 1999/04/25 03:20:45 simonb Exp $")
|
||||
#include <ddb/db_access.h>
|
||||
#include <ddb/db_sym.h>
|
||||
#include <ddb/db_extern.h>
|
||||
#include <ddb/db_extern.h>
|
||||
#endif
|
||||
|
||||
#include <pmax/pmax/clockreg.h>
|
||||
#include <pmax/pmax/pmaxtype.h>
|
||||
#include <pmax/pmax/maxine.h>
|
||||
#include <dev/tc/tcvar.h>
|
||||
#include <dev/tc/ioasicreg.h> /* cycl-counter on kn03 stepping */
|
||||
#include <dev/tc/ioasicvar.h>
|
||||
#include <pmax/dev/promiovar.h> /* prom console I/O vector */
|
||||
|
||||
#include <pmax/pmax/machdep.h> /* splXXX() function pointer hack */
|
||||
|
||||
#include "le_ioasic.h"
|
||||
#include <pmax/pmax/machdep.h> /* splXXX() function pointer hack */
|
||||
|
||||
/* Motherboard or system-specific initialization vector */
|
||||
void unimpl_os_init __P((void));
|
||||
@ -132,7 +120,6 @@ void unimpl_iointr __P ((void *, u_long));
|
||||
void unimpl_clockintr __P ((void *));
|
||||
void unimpl_errintr __P ((void));
|
||||
|
||||
|
||||
struct platform platform = {
|
||||
"iobus not set",
|
||||
unimpl_os_init,
|
||||
@ -143,29 +130,50 @@ struct platform platform = {
|
||||
unimpl_clockintr
|
||||
};
|
||||
|
||||
|
||||
/* the following is used externally (sysctl_hw) */
|
||||
char machine[] = MACHINE; /* from <machine/param.h> */
|
||||
char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */
|
||||
char cpu_model[40];
|
||||
|
||||
char *bootinfo = NULL; /* pointer to bootinfo structure */
|
||||
|
||||
/* maps for VM objects */
|
||||
|
||||
/* maps for VM objects */
|
||||
vm_map_t exec_map = NULL;
|
||||
vm_map_t mb_map = NULL;
|
||||
vm_map_t phys_map = NULL;
|
||||
|
||||
char *bootinfo = NULL; /* pointer to bootinfo structure */
|
||||
int systype; /* Mother board type */
|
||||
int maxmem; /* max memory per process */
|
||||
int physmem; /* max supported memory, changes to actual */
|
||||
int physmem_boardmax; /* {model,simm}-specific bound on physmem */
|
||||
int systype; /* Mother board type */
|
||||
u_long le_iomem; /* 128K for lance chip via. ASIC */
|
||||
|
||||
|
||||
int mem_cluster_cnt;
|
||||
phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
|
||||
int mem_cluster_cnt;
|
||||
|
||||
/*
|
||||
* safepri is a safe priority for sleep to set for a spin-wait
|
||||
* during autoconfiguration or after a panic.
|
||||
* Used as an argument to splx().
|
||||
* XXX disables interrupt 5 to disable mips3 on-chip clock, which also
|
||||
* disables mips1 FPU interrupts.
|
||||
*/
|
||||
int safepri = MIPS3_PSL_LOWIPL; /* XXX */
|
||||
|
||||
unsigned (*clkread) __P((void)); /* high resolution timer if available */
|
||||
|
||||
void mach_init __P((int, char *[], int, int, u_int, char *));
|
||||
int initcpu __P((void));
|
||||
unsigned nullclkread __P((void));
|
||||
int atoi __P((const char *cp));
|
||||
void prom_haltbutton __P((void));
|
||||
void prom_halt __P((int, char *)) __attribute__((__noreturn__));
|
||||
int prom_systype __P((void));
|
||||
|
||||
extern caddr_t esym;
|
||||
|
||||
/* locore callback-vector setup */
|
||||
extern void mips_vector_init __P((void));
|
||||
|
||||
/* XXX XXX XXX */
|
||||
u_long le_iomem; /* 128K for lance chip via. ASIC */
|
||||
|
||||
/* Old 4.4bsd/pmax-derived interrupt-enable method */
|
||||
|
||||
@ -173,7 +181,6 @@ void (*tc_enable_interrupt)
|
||||
__P ((u_int slotno, int (*handler) __P((void *sc)),
|
||||
void *sc, int onoff));
|
||||
|
||||
|
||||
/*
|
||||
* pmax still doesnt have code to build spl masks for both CPU hard-interrupt
|
||||
* register and baseboard interrupt-control registers at runtime.
|
||||
@ -188,46 +195,15 @@ int (*Mach_splimp)__P((void)) = splhigh;
|
||||
int (*Mach_splclock)__P((void)) = splhigh;
|
||||
int (*Mach_splstatclock)__P((void)) = splhigh;
|
||||
volatile struct chiptime *mcclock_addr;
|
||||
|
||||
|
||||
/*XXXjrs*/
|
||||
const struct callback *callv; /* pointer to PROM entry points */
|
||||
|
||||
|
||||
/*
|
||||
* Local functions.
|
||||
*/
|
||||
extern int atoi __P((const char *cp));
|
||||
int initcpu __P((void));
|
||||
|
||||
|
||||
/* initialize bss, etc. from kernel start, before main() is called. */
|
||||
extern void
|
||||
mach_init __P((int argc, char *argv[], u_int code,
|
||||
const struct callback *cv, u_int bim, char *bip));
|
||||
|
||||
|
||||
void prom_halt __P((int, char *)) __attribute__((__noreturn__));
|
||||
/* XXX XXX XXX */
|
||||
|
||||
#ifdef DEBUG
|
||||
/* stacktrace code violates prototypes to get callee's registers */
|
||||
extern void stacktrace __P((void)); /*XXX*/
|
||||
#endif
|
||||
|
||||
extern caddr_t esym;
|
||||
|
||||
/*
|
||||
* safepri is a safe priority for sleep to set for a spin-wait
|
||||
* during autoconfiguration or after a panic. Used as an argument to splx().
|
||||
* XXX disables interrupt 5 to disable mips3 on-chip clock, which also
|
||||
* disables mips1 FPU interrupts.
|
||||
*/
|
||||
int safepri = MIPS3_PSL_LOWIPL; /* XXX */
|
||||
|
||||
/* locore callback-vector setup */
|
||||
extern void mips_vector_init __P((void));
|
||||
|
||||
|
||||
/*
|
||||
* Do all the stuff that locore normally does before calling main().
|
||||
* Process arguments passed to us by the prom monitor.
|
||||
@ -237,8 +213,7 @@ void
|
||||
mach_init(argc, argv, code, cv, bim, bip)
|
||||
int argc;
|
||||
char *argv[];
|
||||
u_int code;
|
||||
const struct callback *cv;
|
||||
int code, cv;
|
||||
u_int bim;
|
||||
char *bip;
|
||||
{
|
||||
@ -282,7 +257,7 @@ mach_init(argc, argv, code, cv, bim, bip)
|
||||
ssym = (caddr_t)bi_syms->ssym;
|
||||
esym = (caddr_t)bi_syms->esym;
|
||||
kernend = (caddr_t)mips_round_page(esym);
|
||||
bzero(edata, end - edata);
|
||||
memset(edata, 0, end - edata);
|
||||
}
|
||||
/* XXX: Backwards compatibility with old bootblocks - this should
|
||||
* go soon...
|
||||
@ -294,20 +269,16 @@ mach_init(argc, argv, code, cv, bim, bip)
|
||||
i += (*(long *)(end + i + 4) + 3) & ~3; /* strings */
|
||||
esym = end + i + 4;
|
||||
kernend = (caddr_t)mips_round_page(esym);
|
||||
bzero(edata, end - edata);
|
||||
memset(edata, 0, end - edata);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
kernend = (caddr_t)mips_round_page(end);
|
||||
bzero(edata, kernend - edata);
|
||||
memset(edata, 0, kernend - edata);
|
||||
}
|
||||
|
||||
/* Initialize callv so we can do PROM output... */
|
||||
if (code == DEC_PROM_MAGIC) {
|
||||
callv = cv;
|
||||
} else {
|
||||
callv = &callvec;
|
||||
}
|
||||
callv = (code == DEC_PROM_MAGIC) ? (void *)cv : &callvec;
|
||||
|
||||
/* Use PROM console output until we initialize a console driver. */
|
||||
cn_tab = &promcd;
|
||||
@ -404,23 +375,12 @@ mach_init(argc, argv, code, cv, bim, bip)
|
||||
/*
|
||||
* Determine what model of computer we are running on.
|
||||
*/
|
||||
if (code == DEC_PROM_MAGIC) {
|
||||
i = (*cv->_getsysid)();
|
||||
cp = "";
|
||||
} else {
|
||||
cp = (*callv->_getenv)("systype");
|
||||
if (cp)
|
||||
i = atoi(cp);
|
||||
else {
|
||||
cp = "";
|
||||
i = 0;
|
||||
}
|
||||
}
|
||||
i = prom_systype();
|
||||
|
||||
/* Check for MIPS based platform */
|
||||
/* 0x82 -> MIPS1, 0x84 -> MIPS3 */
|
||||
if (((i >> 24) & 0xFF) != 0x82 && ((i >> 24) & 0xff) != 0x84) {
|
||||
printf("Unknown System type '%s' 0x%x\n", cp, i);
|
||||
printf("Unknown system type '%08x'\n", i);
|
||||
cpu_reboot(RB_HALT | RB_NOSYNC, NULL);
|
||||
}
|
||||
|
||||
@ -430,13 +390,10 @@ mach_init(argc, argv, code, cv, bim, bip)
|
||||
*/
|
||||
physmem_boardmax = MIPS_MAX_MEM_ADDR;
|
||||
|
||||
/* check what model platform we are running on */
|
||||
systype = ((i >> 16) & 0xff);
|
||||
|
||||
|
||||
/*
|
||||
* Find out what hardware we're on, and do basic initialization.
|
||||
*/
|
||||
systype = ((i >> 16) & 0xff);
|
||||
if (systype >= nsysinit) {
|
||||
platform_not_supported();
|
||||
/* NOTREACHED */
|
||||
@ -512,8 +469,8 @@ mach_init(argc, argv, code, cv, bim, bip)
|
||||
|
||||
|
||||
/*
|
||||
* cpu_startup: allocate memory for variable-sized tables,
|
||||
* initialize cpu, and do autoconfiguration.
|
||||
* Machine-dependent startup code.
|
||||
* allocate memory for variable-sized tables, initialize cpu.
|
||||
*/
|
||||
void
|
||||
cpu_startup()
|
||||
@ -533,9 +490,7 @@ cpu_startup()
|
||||
* Good {morning,afternoon,evening,night}.
|
||||
*/
|
||||
printf(version);
|
||||
|
||||
printf("%s\n", cpu_model);
|
||||
|
||||
printf("real mem = %d\n", ctob(physmem));
|
||||
|
||||
/*
|
||||
@ -660,7 +615,7 @@ cpu_startup()
|
||||
|
||||
|
||||
/*
|
||||
* machine dependent system variables.
|
||||
* Machine dependent system variables.
|
||||
*/
|
||||
int
|
||||
cpu_sysctl(name, namelen, oldp, oldlenp, newp, newlen, p)
|
||||
@ -685,7 +640,7 @@ cpu_sysctl(name, namelen, oldp, oldlenp, newp, newlen, p)
|
||||
case CPU_BOOTED_KERNEL:
|
||||
bibp = lookup_bootinfo(BTINFO_BOOTPATH);
|
||||
if(!bibp)
|
||||
return(ENOENT); /* ??? */
|
||||
return (ENOENT); /* ??? */
|
||||
return (sysctl_rdstring(oldp, oldlenp, newp, bibp->bootpath));
|
||||
default:
|
||||
return (EOPNOTSUPP);
|
||||
@ -729,9 +684,8 @@ prom_haltbutton()
|
||||
(*callv->_halt)((int *)0, 0);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* call PROM to halt or reboot.
|
||||
* Call PROM to halt or reboot.
|
||||
*/
|
||||
volatile void
|
||||
prom_halt(howto, bootstr)
|
||||
@ -739,27 +693,37 @@ prom_halt(howto, bootstr)
|
||||
char *bootstr;
|
||||
|
||||
{
|
||||
if (callv != &callvec) {
|
||||
if (howto & RB_HALT)
|
||||
(*callv->_rex)('h');
|
||||
else {
|
||||
(*callv->_rex)('b');
|
||||
}
|
||||
} else if (howto & RB_HALT) {
|
||||
volatile void (*f) __P((void)) =
|
||||
(volatile void (*) __P((void))) DEC_PROM_REINIT;
|
||||
if (callv != &callvec)
|
||||
(*callv->_rex)((howto & RB_HALT) ? 'h' : 'b');
|
||||
else {
|
||||
volatile void (*f) __P((void));
|
||||
|
||||
(*f)(); /* jump back to prom monitor */
|
||||
} else {
|
||||
volatile void (*f) __P((void)) =
|
||||
(volatile void (*) __P((void)))DEC_PROM_AUTOBOOT;
|
||||
(*f)(); /* jump back to prom monitor and do 'auto' cmd */
|
||||
f = (howto & RB_HALT)
|
||||
? (void *)DEC_PROM_REINIT
|
||||
: (void *)DEC_PROM_AUTOBOOT;
|
||||
(*f)();
|
||||
}
|
||||
|
||||
while(1) ; /* fool gcc */
|
||||
/*NOTREACHED*/
|
||||
}
|
||||
|
||||
/*
|
||||
* Get 32bit system type of Digital hardware.
|
||||
* From highest order byte to lowest;
|
||||
* 'cputype,' 'systype,' 'firmware revision' and 'hardware revision.'
|
||||
*/
|
||||
int
|
||||
prom_systype()
|
||||
{
|
||||
char *cp;
|
||||
|
||||
if (callv != &callvec)
|
||||
return (*callv->_getsysid)();
|
||||
cp = (*callv->_getenv)("systype");
|
||||
return (cp != NULL) ? atoi(cp) : 0;
|
||||
}
|
||||
|
||||
void
|
||||
cpu_reboot(howto, bootstr)
|
||||
volatile int howto; /* XXX volatile to keep gcc happy */
|
||||
@ -816,129 +780,21 @@ haltsys:
|
||||
/* run any shutdown hooks */
|
||||
doshutdownhooks();
|
||||
|
||||
|
||||
/* Finally, halt/reboot the system. */
|
||||
printf("%s\n\n", howto & RB_HALT ? "halted." : "rebooting...");
|
||||
prom_halt(howto & RB_HALT, bootstr);
|
||||
/*NOTREACHED*/
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Read a high-resolution clock, if one is available, and return
|
||||
* the current microsecond offset from time-of-day.
|
||||
*/
|
||||
|
||||
/* XXX clock hacks */
|
||||
#include "opt_dec_3maxplus.h"
|
||||
#include "opt_dec_3min.h"
|
||||
#include "opt_dec_maxine.h"
|
||||
|
||||
#if !(defined(DEC_3MAXPLUS) || defined(DEC_MAXINE) ||defined(DEC_3MIN))
|
||||
#define clkread() (0)
|
||||
#else /* (defined(DEC_3MAXPLUS) || defined(DEC_MAXINE)) */
|
||||
|
||||
static __inline u_long clkread __P((void)); /* get usec-resolution clock */
|
||||
#include "opt_dec_3maxplus.h"
|
||||
|
||||
/*
|
||||
* IOASIC TC cycle counter, latched on every interrupt from RTC chip.
|
||||
* [Or free-running microsecond counter on Maxine.]
|
||||
*
|
||||
* XXXjrs needs better MI hardware tier support.
|
||||
*/
|
||||
u_long latched_cycle_cnt;
|
||||
|
||||
/*
|
||||
* On a Decstation 5000/240, use the turbochannel bus-cycle counter
|
||||
* to interpolate micro-seconds since the last RTC clock tick.
|
||||
* The interpolation base is the copy of the bus cycle-counter taken
|
||||
* by the RTC interrupt handler.
|
||||
* On XINE, use the microsecond free-running counter.
|
||||
*
|
||||
*/
|
||||
static __inline u_long
|
||||
clkread()
|
||||
{
|
||||
|
||||
#ifdef DEC_3MAXPLUS
|
||||
u_long usec, cycles; /* really 32 bits? */
|
||||
#endif
|
||||
|
||||
#if defined(DEC_3MIN)
|
||||
if (systype == DS_3MIN && CPUISMIPS3) {
|
||||
extern u_int32_t mips3_cycle_count __P((void));
|
||||
u_int32_t mips3_cycles =
|
||||
mips3_cycle_count() - (u_int32_t)latched_cycle_cnt;
|
||||
/* XXX divides take 78 cycles: approximate with * 41/2048 */
|
||||
#if 0
|
||||
return (mips3_cycles / cpu_mhz);
|
||||
#else
|
||||
return((mips3_cycles >> 6) + (mips3_cycles >> 8) +
|
||||
(mips3_cycles >> 11));
|
||||
#endif
|
||||
} else
|
||||
#endif
|
||||
#ifdef DEC_MAXINE
|
||||
if (systype == DS_MAXINE)
|
||||
return (*(u_long*)(MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR)) -
|
||||
latched_cycle_cnt);
|
||||
else
|
||||
#endif
|
||||
#ifdef DEC_3MAXPLUS
|
||||
if (systype == DS_3MAXPLUS)
|
||||
/* 5k/240 TC bus counter */
|
||||
cycles = *(u_long*)IOASIC_REG_CTR(ioasic_base);
|
||||
else
|
||||
#endif
|
||||
return (0);
|
||||
|
||||
#ifdef DEC_3MAXPLUS
|
||||
/* Compute difference in cycle count from last hardclock() to now */
|
||||
#if 1
|
||||
/* my code, using u_ints */
|
||||
cycles = cycles - latched_cycle_cnt;
|
||||
#else
|
||||
/* Mills code, using (signed) ints */
|
||||
if (cycles >= latched_cycle_cnt)
|
||||
cycles = cycles - latched_cycle_cnt;
|
||||
else
|
||||
cycles = latched_cycle_cnt - cycles;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Scale from 40ns to microseconds.
|
||||
* Avoid a kernel FP divide (by 25) using the approximation
|
||||
* 1/25 = 40/1000 =~ 41/ 1024, which is good to 0.0975 %
|
||||
*/
|
||||
usec = cycles + (cycles << 3) + (cycles << 5);
|
||||
usec = usec >> 10;
|
||||
|
||||
#ifdef CLOCK_DEBUG
|
||||
if (usec > 3906 +4) {
|
||||
addlog("clkread: usec %d, counter=%lx\n",
|
||||
usec, latched_cycle_cnt);
|
||||
stacktrace();
|
||||
}
|
||||
#endif /*CLOCK_DEBUG*/
|
||||
return usec;
|
||||
#endif /* DEC_3MAXPLUS */
|
||||
}
|
||||
|
||||
#if 0
|
||||
void
|
||||
microset()
|
||||
{
|
||||
latched_cycle_cnt = *(u_long*)(IOASIC_REG_CTR(ioasic_base));
|
||||
}
|
||||
#endif /* 0 */
|
||||
#endif /* (defined(DEC_3MAXPLUS) || defined(DEC_MAXINE)) */
|
||||
|
||||
|
||||
/*
|
||||
* Return the best possible estimate of the time in the timeval
|
||||
* to which tvp points. Unfortunately, we can't read the hardware registers.
|
||||
* We guarantee that the time will be greater than the value obtained by a
|
||||
* previous call.
|
||||
* Return the best possible estimate of the time in the timeval to
|
||||
* which tvp points. We guarantee that the time will be greater than
|
||||
* the value obtained by a previous call. Some models of DECstations
|
||||
* provide a high resolution timer circuit.
|
||||
*/
|
||||
void
|
||||
microtime(tvp)
|
||||
@ -948,7 +804,9 @@ microtime(tvp)
|
||||
static struct timeval lasttime;
|
||||
|
||||
*tvp = time;
|
||||
tvp->tv_usec += clkread();
|
||||
#if (DEC_3MIN + DEC_3MAXPLUS + DEC_MAXINE) > 1
|
||||
tvp->tv_usec += (*clkread)();
|
||||
#endif
|
||||
if (tvp->tv_usec >= 1000000) {
|
||||
tvp->tv_usec -= 1000000;
|
||||
tvp->tv_sec++;
|
||||
@ -1069,7 +927,6 @@ out:
|
||||
/*
|
||||
* Ensure all platform vectors are always initialized.
|
||||
*/
|
||||
|
||||
void
|
||||
unimpl_os_init()
|
||||
{
|
||||
@ -1144,3 +1001,9 @@ unimpl_errintr()
|
||||
{
|
||||
panic("sysconf.init didnt set errintr_name\n");
|
||||
}
|
||||
|
||||
unsigned
|
||||
nullclkread()
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: machdep.h,v 1.2 1998/03/25 06:22:20 jonathan Exp $ */
|
||||
/* $NetBSD: machdep.h,v 1.3 1999/04/26 09:23:23 nisimura Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
|
||||
@ -34,11 +34,6 @@
|
||||
extern char machine[];
|
||||
extern char cpu_model[];
|
||||
|
||||
|
||||
/* XXX ioasic hardware initialization. */
|
||||
void ioasic_init __P((int flags)); /* chip revision flag */
|
||||
|
||||
|
||||
/*
|
||||
* Interrupt-blocking functions defined in locore. These names aren't used
|
||||
* directly except here and in interrupt handlers.
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user