Contribution from Petri Laakso: Initial support for SD card controller.
iMX233-OLinuXino can now boot and run from its own SD card.
This commit is contained in:
jkunz
parent
8a7d722d8b
commit
c332c3c01b
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@ -1,4 +1,4 @@
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/* $Id: imx23_ssp.c,v 1.1 2012/11/20 19:06:14 jkunz Exp $ */
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/* $Id: imx23_ssp.c,v 1.2 2012/12/16 19:45:52 jkunz Exp $ */
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/*
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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@ -33,15 +33,10 @@
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#include <sys/types.h>
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#include <sys/bus.h>
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#include <sys/cdefs.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/systm.h>
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#include <arm/pic/picvar.h>
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#include <arm/imx/imx23_apbdma.h>
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#include <arm/imx/imx23_icollreg.h>
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#include <arm/imx/imx23_sspreg.h>
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#include <arm/imx/imx23var.h>
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@ -50,7 +45,7 @@
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#include <dev/sdmmc/sdmmcvar.h>
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/*
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* SD/MMC host controller driver for i.MX233.
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* SD/MMC host controller driver for i.MX23.
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*/
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struct issp_softc {
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@ -65,7 +60,11 @@ static int issp_match(device_t, cfdata_t, void *);
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static void issp_attach(device_t, device_t, void *);
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static int issp_activate(device_t, enum devact);
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/* sdmmc chip function prototypes. */
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static void issp_reset(struct issp_softc *);
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static void issp_init(struct issp_softc *);
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static uint32_t issp_set_sck(struct issp_softc *, uint32_t target);
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/* sdmmc(4) driver chip function prototypes. */
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static int issp_host_reset(sdmmc_chipset_handle_t);
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static uint32_t issp_host_ocr(sdmmc_chipset_handle_t);
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static int issp_host_maxblklen(sdmmc_chipset_handle_t);
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@ -80,23 +79,6 @@ static void issp_exec_command(sdmmc_chipset_handle_t,
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static void issp_card_enable_intr(sdmmc_chipset_handle_t, int);
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static void issp_card_intr_ack(sdmmc_chipset_handle_t);
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/* Used from the above callbacks. */
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static void issp_reset(struct issp_softc *);
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static void issp_init(struct issp_softc *);
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static uint32_t issp_set_sck(struct issp_softc *, uint32_t target);
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#define SSP_SOFT_RST_LOOP 455 /* At least 1 us ... */
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CFATTACH_DECL3_NEW(ssp,
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sizeof(struct issp_softc),
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issp_match,
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issp_attach,
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NULL,
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issp_activate,
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NULL,
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NULL,
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0);
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static struct sdmmc_chip_functions issp_functions = {
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.host_reset = issp_host_reset,
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.host_ocr = issp_host_ocr,
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@ -112,22 +94,45 @@ static struct sdmmc_chip_functions issp_functions = {
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.card_intr_ack = issp_card_intr_ack
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};
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#define SSP_READ(sc, reg) \
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CFATTACH_DECL3_NEW(ssp,
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sizeof(struct issp_softc),
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issp_match,
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issp_attach,
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NULL,
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issp_activate,
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NULL,
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NULL,
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0);
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#define SSP_SOFT_RST_LOOP 455 /* At least 1 us ... */
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#define SSP_RD(sc, reg) \
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bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg))
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#define SSP_WRITE(sc, reg, val) \
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#define SSP_WR(sc, reg, val) \
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bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))
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#define SSP_CLK 96000000 /* CLK_SSP from PLL is 96 MHz */
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#define SSP_CLK_MIN 2 /* 2 kHz */
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#define SSP_CLK_MAX 48000 /* 48 MHz */
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/* SSP_CMD_TIMEOUT is calculated as (1.0/SSP_SCK)*(SSP_CMD_TIMEOUT*4096) */
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#define SSP_CMD_TIMEOUT 0xffff /* 2.8 seconds. */
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#define SSP_STATUS_ERR (HW_SSP_STATUS_RESP_CRC_ERR | \
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#define SSP_CLK 96000000 /* CLK_SSP from PLL is 96 MHz */
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#define SSP_CLK_MIN 400 /* 400 kHz */
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#define SSP_CLK_MAX 48000 /* 48 MHz */
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#define SSP_BUSY (HW_SSP_STATUS_CMD_BUSY | \
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HW_SSP_STATUS_DATA_BUSY | \
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HW_SSP_STATUS_BUSY)
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#define SSP_RUN_ERR (HW_SSP_STATUS_RESP_CRC_ERR | \
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HW_SSP_STATUS_RESP_ERR | \
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HW_SSP_STATUS_RESP_TIMEOUT | \
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HW_SSP_STATUS_DATA_CRC_ERR | \
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HW_SSP_STATUS_TIMEOUT)
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#define BLKIO_NONE 0
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#define BLKIO_RD 1
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#define BLKIO_WR 2
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#define BUS_WIDTH_1_BIT 0x0
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#define BUS_WIDTH_4_BIT 0x1
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#define BUS_WIDTH_8_BIT 0x2
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static int
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issp_match(device_t parent, cfdata_t match, void *aux)
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{
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@ -145,25 +150,18 @@ issp_match(device_t parent, cfdata_t match, void *aux)
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static void
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issp_attach(device_t parent, device_t self, void *aux)
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{
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static int issp_attached = 0;
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struct issp_softc *sc = device_private(self);
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struct apb_softc *scp = device_private(parent);
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struct apb_softc *sc_parent = device_private(parent);
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struct apb_attach_args *aa = aux;
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struct sdmmcbus_attach_args saa;
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static int issp_attached = 0;
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if (issp_attached)
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return;
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//XXX:
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if (scp == NULL)
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printf("ISSP_ATTACH: scp == NULL\n");
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if (scp->dmac == NULL)
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printf("ISSP_ATTACH: scp->dmac == NULL\n");
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sc->sc_dev = self;
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sc->sc_iot = aa->aa_iot;
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sc->dmac = scp->dmac;
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sc->dmac = sc_parent->dmac;
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if (bus_space_map(sc->sc_iot,
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aa->aa_addr, aa->aa_size, 0, &(sc->sc_hdl))) {
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@ -172,9 +170,9 @@ issp_attach(device_t parent, device_t self, void *aux)
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}
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issp_reset(sc);
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issp_init(sc);
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issp_init(sc);
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uint32_t issp_vers = SSP_READ(sc, HW_SSP_VERSION);
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uint32_t issp_vers = SSP_RD(sc, HW_SSP_VERSION);
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aprint_normal(": SSP Block v%" __PRIuBIT ".%" __PRIuBIT "\n",
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__SHIFTOUT(issp_vers, HW_SSP_VERSION_MAJOR),
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__SHIFTOUT(issp_vers, HW_SSP_VERSION_MINOR));
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@ -186,7 +184,8 @@ issp_attach(device_t parent, device_t self, void *aux)
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saa.saa_dmat = aa->aa_dmat;
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saa.saa_clkmin = SSP_CLK_MIN;
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saa.saa_clkmax = SSP_CLK_MAX;
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saa.saa_caps = SMC_CAPS_4BIT_MODE | SMC_CAPS_DMA;
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/* Add SMC_CAPS_DMA capability when DMA funtionality is implemented. */
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saa.saa_caps = SMC_CAPS_4BIT_MODE | SMC_CAPS_SINGLE_ONLY;
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sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL);
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if (sc->sc_sdmmc == NULL) {
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@ -228,7 +227,6 @@ issp_host_ocr(sdmmc_chipset_handle_t sch)
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static int
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issp_host_maxblklen(sdmmc_chipset_handle_t sch)
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{
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/* XXX: This value was made up. */
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return 512;
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}
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@ -242,10 +240,10 @@ issp_card_detect(sdmmc_chipset_handle_t sch)
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/* struct issp_softc *sc = sch;
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*
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* In the perfect world I'll just:
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* return SSP_READ(sc, HW_SSP_STATUS) & HW_SSP_STATUS_CARD_DETECT;
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* return SSP_RD(sc, HW_SSP_STATUS) & HW_SSP_STATUS_CARD_DETECT;
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* and call it a day.
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*
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* But on i.MX233 OLinuXino MAXI, SSP1_DETECT is not used for the SD
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* But on i.MX23 OLinuXino MAXI, SSP1_DETECT is not used for the SD
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* card detection but SSP1_DATA3 is, as Tsvetan put it:
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*
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* < Tsvetan> if you want to know if SD card is inserted watch
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@ -258,7 +256,7 @@ issp_card_detect(sdmmc_chipset_handle_t sch)
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* #if BOARDTYPE == MAXI (Possibly MINI & MICRO)
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* return GPIO_READ(PIN_125) & PIN_125
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* #else
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* return SSP_READ(sc, STATUS) & CARD_DETECT;
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* return SSP_RD(sc, STATUS) & CARD_DETECT;
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* #endif
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* Until GPIO functionality is not present I am just going to */
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@ -273,9 +271,9 @@ issp_write_protect(sdmmc_chipset_handle_t sch)
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}
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static int
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issp_bus_power(sdmmc_chipset_handle_t sch, uint32_t power)
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issp_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
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{
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/* i.MX233 does not support setting bus power. */
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/* i.MX23 SSP does not support setting bus power. */
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return 0;
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}
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@ -285,9 +283,13 @@ issp_bus_clock(sdmmc_chipset_handle_t sch, int clock)
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struct issp_softc *sc = sch;
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uint32_t sck;
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aprint_normal_dev(sc->sc_dev, "requested clock %d Hz", clock * 1000);
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sck = issp_set_sck(sc, clock * 1000);
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aprint_normal(", got %d Hz\n", sck);
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/* Notify user if we didn't get exact clock rate from SSP that was
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* requested. */
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if (sck != clock * 1000)
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aprint_normal_dev(sc->sc_dev, "requested clock %dHz, "
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"but got %dHz\n", clock * 1000, sck);
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return 0;
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}
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@ -295,8 +297,29 @@ issp_bus_clock(sdmmc_chipset_handle_t sch, int clock)
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static int
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issp_bus_width(sdmmc_chipset_handle_t sch, int width)
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{
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/* Return error if other than 4-bit width is requested. */
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return width - 4;
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struct issp_softc *sc = sch;
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uint32_t reg;
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reg = SSP_RD(sc, HW_SSP_CTRL0);
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reg &= ~(HW_SSP_CTRL0_BUS_WIDTH);
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switch(width) {
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case(1):
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reg |= __SHIFTIN(BUS_WIDTH_1_BIT, HW_SSP_CTRL0_BUS_WIDTH);
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break;
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case(4):
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reg |= __SHIFTIN(BUS_WIDTH_4_BIT, HW_SSP_CTRL0_BUS_WIDTH);
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break;
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case(8):
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reg |= __SHIFTIN(BUS_WIDTH_8_BIT, HW_SSP_CTRL0_BUS_WIDTH);
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break;
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default:
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return 1;
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}
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SSP_WR(sc, HW_SSP_CTRL0, reg);
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return 0;
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}
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static int
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@ -311,60 +334,130 @@ issp_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
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{
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struct issp_softc *sc = sch;
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uint32_t reg;
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uint32_t do_blkio;
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uint32_t i;
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/* Set excepted response type. */
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SSP_WRITE(sc, HW_SSP_CTRL0_CLR,
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do_blkio = 0;
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/* Wait until SSP done. (data I/O error + retry...) */
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while (SSP_RD(sc, HW_SSP_STATUS) & SSP_BUSY)
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;
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/* Set expected response type. */
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SSP_WR(sc, HW_SSP_CTRL0_CLR,
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HW_SSP_CTRL0_GET_RESP | HW_SSP_CTRL0_LONG_RESP);
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if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) {
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SSP_WRITE(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_GET_RESP);
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SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_GET_RESP);
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if (ISSET(cmd->c_flags, SCF_RSP_136))
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SSP_WRITE(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_LONG_RESP);
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SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_LONG_RESP);
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}
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/* If CMD does not need CRC validation, tell it to SSP. */
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if (ISSET(cmd->c_flags, SCF_RSP_CRC))
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SSP_WRITE(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_IGNORE_CRC);
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SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_IGNORE_CRC);
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else
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SSP_WRITE(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_IGNORE_CRC);
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SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_IGNORE_CRC);
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/* Set command. */
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SSP_WRITE(sc, HW_SSP_CMD0_CLR, HW_SSP_CMD0_CMD);
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SSP_WRITE(sc, HW_SSP_CMD0_SET,
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SSP_WR(sc, HW_SSP_CMD0_CLR, HW_SSP_CMD0_CMD);
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SSP_WR(sc, HW_SSP_CMD0_SET,
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__SHIFTIN(cmd->c_opcode, HW_SSP_CMD0_CMD));
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/* Set command argument. */
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SSP_WRITE(sc, HW_SSP_CMD1, cmd->c_arg);
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SSP_WR(sc, HW_SSP_CMD1, cmd->c_arg);
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/* Is data to be transferred? */
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if (cmd->c_datalen > 0 && cmd->c_data != NULL) {
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SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_DATA_XFER);
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/* Transfer XFER_COUNT of 8-bit words. */
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SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_XFER_COUNT);
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SSP_WR(sc, HW_SSP_CTRL0_SET,
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__SHIFTIN(cmd->c_datalen, HW_SSP_CTRL0_XFER_COUNT));
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/* XXX: why 8CYC? Bit is never cleaned. */
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SSP_WR(sc, HW_SSP_CMD0_SET, HW_SSP_CMD0_APPEND_8CYC);
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if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
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/* Read mode. */
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do_blkio |= BLKIO_RD;
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SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_READ);
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} else {
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/* Write mode. */
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do_blkio |= BLKIO_WR;
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SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_READ);
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}
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} else {
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/* No data to be transferred. */
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SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_DATA_XFER);
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}
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/* Run the command. */
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SSP_WRITE(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_RUN);
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SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_RUN);
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/* Wait until SSP has processed the command. */
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while (SSP_READ(sc, HW_SSP_STATUS) &
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(HW_SSP_STATUS_CMD_BUSY | HW_SSP_STATUS_BUSY))
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;
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/* Check if the command ran without errors. */
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reg = SSP_READ(sc, HW_SSP_STATUS);
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if (reg & SSP_STATUS_ERR)
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cmd->c_error = reg & SSP_STATUS_ERR;
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/* Read response if such was requested. */
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if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) {
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cmd->c_resp[0] = SSP_READ(sc, HW_SSP_SDRESP0);
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if (ISSET(cmd->c_flags, SCF_RSP_136)) {
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cmd->c_resp[1] = SSP_READ(sc, HW_SSP_SDRESP1);
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cmd->c_resp[2] = SSP_READ(sc, HW_SSP_SDRESP2);
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cmd->c_resp[3] = SSP_READ(sc, HW_SSP_SDRESP3);
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if (ISSET(do_blkio, BLKIO_RD)) {
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for (i = 0; i < cmd->c_datalen / 4; i++) {
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/* Wait until data arrives to FIFO. */
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while (SSP_RD(sc, HW_SSP_STATUS)
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& HW_SSP_STATUS_FIFO_EMPTY) {
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/* Abort if error while waiting. */
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if (SSP_RD(sc, HW_SSP_STATUS) & SSP_RUN_ERR) {
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aprint_normal_dev(sc->sc_dev,
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"RD_ERR: %x\n",
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SSP_RD(sc, HW_SSP_STATUS));
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cmd->c_error = 1;
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goto pioerr;
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}
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}
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*((uint32_t *)cmd->c_data+i) = SSP_RD(sc, HW_SSP_DATA);
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}
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} else if (ISSET(do_blkio, BLKIO_WR)) {
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for (i = 0; i < (cmd->c_datalen / 4); i++) {
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while (SSP_RD(sc, HW_SSP_STATUS)
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& HW_SSP_STATUS_FIFO_FULL) {
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/* Abort if error while waiting. */
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if (SSP_RD(sc, HW_SSP_STATUS) & SSP_RUN_ERR) {
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aprint_normal_dev(sc->sc_dev,
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"WR_ERR: %x\n",
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SSP_RD(sc, HW_SSP_STATUS));
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cmd->c_error = 1;
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goto pioerr;
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}
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}
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SSP_WR(sc, HW_SSP_DATA, *((uint32_t *)cmd->c_data+i));
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}
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}
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||||
|
||||
/*
|
||||
apbdma_dmamem_alloc()
|
||||
apbdma_do_dma()
|
||||
wait_until_done()
|
||||
*/
|
||||
/* Wait until SSP is done. */
|
||||
while (SSP_RD(sc, HW_SSP_STATUS) & SSP_BUSY)
|
||||
;
|
||||
|
||||
/* Check if the command ran successfully. */
|
||||
reg = SSP_RD(sc, HW_SSP_STATUS);
|
||||
if (reg & SSP_RUN_ERR)
|
||||
cmd->c_error = reg & SSP_RUN_ERR;
|
||||
|
||||
/* Read response if such was requested. */
|
||||
if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) {
|
||||
cmd->c_resp[0] = SSP_RD(sc, HW_SSP_SDRESP0);
|
||||
if (ISSET(cmd->c_flags, SCF_RSP_136)) {
|
||||
cmd->c_resp[1] = SSP_RD(sc, HW_SSP_SDRESP1);
|
||||
cmd->c_resp[2] = SSP_RD(sc, HW_SSP_SDRESP2);
|
||||
cmd->c_resp[3] = SSP_RD(sc, HW_SSP_SDRESP3);
|
||||
/*
|
||||
* Remove CRC7 + LSB by rotating all bits right by 8 to
|
||||
* make sdmmc __bitfield() happy.
|
||||
*/
|
||||
cmd->c_resp[0] >>= 8; /* Remove CRC7 + LSB. */
|
||||
cmd->c_resp[0] |= (0x000000FF & cmd->c_resp[1]) << 24;
|
||||
cmd->c_resp[1] >>= 8;
|
||||
cmd->c_resp[1] |= (0x000000FF & cmd->c_resp[2]) << 24;
|
||||
cmd->c_resp[2] >>= 8;
|
||||
cmd->c_resp[2] |= (0x000000FF & cmd->c_resp[3]) << 24;
|
||||
cmd->c_resp[3] >>= 8;
|
||||
}
|
||||
}
|
||||
pioerr:
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -374,7 +467,7 @@ issp_card_enable_intr(sdmmc_chipset_handle_t sch, int irq)
|
|||
struct issp_softc *sc = sch;
|
||||
|
||||
aprint_normal_dev(sc->sc_dev,
|
||||
"issp_card_enable_intr NOT IMPLEMENTED!\n");
|
||||
"issp_card_enable_intr NOT IMPLEMENTED!\n");
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -392,7 +485,7 @@ issp_card_intr_ack(sdmmc_chipset_handle_t sch)
|
|||
/*
|
||||
* Reset the SSP block.
|
||||
*
|
||||
* Inspired by i.MX233 RM "39.3.10 Correct Way to Soft Reset a Block"
|
||||
* Inspired by i.MX23 RM "39.3.10 Correct Way to Soft Reset a Block"
|
||||
*/
|
||||
static void
|
||||
issp_reset(struct issp_softc *sc)
|
||||
|
|
@ -402,65 +495,77 @@ issp_reset(struct issp_softc *sc)
|
|||
/* Prepare for soft-reset by making sure that SFTRST is not currently
|
||||
* asserted. Also clear CLKGATE so we can wait for its assertion below.
|
||||
*/
|
||||
SSP_WRITE(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_SFTRST);
|
||||
SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_SFTRST);
|
||||
|
||||
/* Wait at least a microsecond for SFTRST to deassert. */
|
||||
loop = 0;
|
||||
while ((SSP_READ(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_SFTRST) ||
|
||||
while ((SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_SFTRST) ||
|
||||
(loop < SSP_SOFT_RST_LOOP))
|
||||
loop++;
|
||||
|
||||
/* Clear CLKGATE so we can wait for its assertion below. */
|
||||
SSP_WRITE(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_CLKGATE);
|
||||
SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_CLKGATE);
|
||||
|
||||
/* Soft-reset the block. */
|
||||
SSP_WRITE(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_SFTRST);
|
||||
SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_SFTRST);
|
||||
|
||||
/* Wait until clock is in the gated state. */
|
||||
while (!(SSP_READ(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_CLKGATE));
|
||||
while (!(SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_CLKGATE));
|
||||
|
||||
/* Bring block out of reset. */
|
||||
SSP_WRITE(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_SFTRST);
|
||||
SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_SFTRST);
|
||||
|
||||
loop = 0;
|
||||
while ((SSP_READ(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_SFTRST) ||
|
||||
while ((SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_SFTRST) ||
|
||||
(loop < SSP_SOFT_RST_LOOP))
|
||||
loop++;
|
||||
|
||||
SSP_WRITE(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_CLKGATE);
|
||||
|
||||
SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_CLKGATE);
|
||||
|
||||
/* Wait until clock is in the NON-gated state. */
|
||||
while (SSP_READ(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_CLKGATE);
|
||||
while (SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_CLKGATE);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialize common options.
|
||||
* DATA_TIMEOUT is calculated as:
|
||||
* (1 / SSP_CLK) * (DATA_TIMEOUT * 4096)
|
||||
*/
|
||||
#define DATA_TIMEOUT 0x4240 /* 723ms */
|
||||
|
||||
/*
|
||||
* Initialize SSP controller to SD/MMC mode.
|
||||
*/
|
||||
static void
|
||||
issp_init(struct issp_softc *sc)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
/* Initialize SD/MMC controller. */
|
||||
reg = SSP_READ(sc, HW_SSP_CTRL0);
|
||||
/* Initial data bus width is 1-bit. */
|
||||
reg = SSP_RD(sc, HW_SSP_CTRL0);
|
||||
reg &= ~(HW_SSP_CTRL0_BUS_WIDTH);
|
||||
reg |= __SHIFTIN(0x1, HW_SSP_CTRL0_BUS_WIDTH) | HW_SSP_CTRL0_ENABLE;
|
||||
SSP_WRITE(sc, HW_SSP_CTRL0, reg);
|
||||
reg |= __SHIFTIN(BUS_WIDTH_1_BIT, HW_SSP_CTRL0_BUS_WIDTH) |
|
||||
HW_SSP_CTRL0_WAIT_FOR_IRQ | HW_SSP_CTRL0_ENABLE;
|
||||
SSP_WR(sc, HW_SSP_CTRL0, reg);
|
||||
|
||||
reg = SSP_READ(sc, HW_SSP_CTRL1);
|
||||
/* Set data timeout. */
|
||||
reg = SSP_RD(sc, HW_SSP_TIMING);
|
||||
reg &= ~(HW_SSP_TIMING_TIMEOUT);
|
||||
reg |= __SHIFTIN(DATA_TIMEOUT, HW_SSP_TIMING_TIMEOUT);
|
||||
|
||||
/* Set initial clock rate to minimum. */
|
||||
issp_set_sck(sc, SSP_CLK_MIN * 1000);
|
||||
|
||||
SSP_WR(sc, HW_SSP_TIMING, reg);
|
||||
/* Enable SD/MMC mode and use use 8-bits per word. */
|
||||
reg = SSP_RD(sc, HW_SSP_CTRL1);
|
||||
reg &= ~(HW_SSP_CTRL1_WORD_LENGTH | HW_SSP_CTRL1_SSP_MODE);
|
||||
reg |= HW_SSP_CTRL1_POLARITY |
|
||||
__SHIFTIN(0x7, HW_SSP_CTRL1_WORD_LENGTH) |
|
||||
__SHIFTIN(0x3, HW_SSP_CTRL1_SSP_MODE);
|
||||
SSP_WRITE(sc, HW_SSP_CTRL1, reg);
|
||||
|
||||
/* Set command timeout. */
|
||||
reg = SSP_READ(sc, HW_SSP_TIMING);
|
||||
reg &= ~(HW_SSP_TIMING_TIMEOUT);
|
||||
reg |= __SHIFTIN(SSP_CMD_TIMEOUT, HW_SSP_TIMING_TIMEOUT);
|
||||
SSP_WRITE(sc, HW_SSP_TIMING, reg);
|
||||
SSP_WR(sc, HW_SSP_CTRL1, reg);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -499,11 +604,11 @@ issp_set_sck(struct issp_softc *sc, uint32_t target)
|
|||
}
|
||||
}
|
||||
out:
|
||||
reg = SSP_READ(sc, HW_SSP_TIMING);
|
||||
reg = SSP_RD(sc, HW_SSP_TIMING);
|
||||
reg &= ~(HW_SSP_TIMING_CLOCK_DIVIDE | HW_SSP_TIMING_CLOCK_RATE);
|
||||
reg |= __SHIFTIN(div, HW_SSP_TIMING_CLOCK_DIVIDE) |
|
||||
__SHIFTIN(rate, HW_SSP_TIMING_CLOCK_RATE);
|
||||
SSP_WRITE(sc, HW_SSP_TIMING, reg);
|
||||
SSP_WR(sc, HW_SSP_TIMING, reg);
|
||||
|
||||
return SSP_CLK / (d * (1 + r));
|
||||
return SSP_CLK / (div * (1 + rate));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# $Id: IMX23_OLINUXINO,v 1.1 2012/11/20 19:08:45 jkunz Exp $
|
||||
# $Id: IMX23_OLINUXINO,v 1.2 2012/12/16 19:45:52 jkunz Exp $
|
||||
#
|
||||
# IMX23_OLINUXINO -- Olimex i.MX23 OLinuXino kernel configuration file.
|
||||
#
|
||||
|
|
@ -7,7 +7,7 @@ include "arch/evbarm/conf/std.imx23_olinuxino"
|
|||
|
||||
maxusers 8
|
||||
|
||||
config netbsd root on ? type ?
|
||||
config netbsd root on ld0a type ?
|
||||
|
||||
# The main bus device
|
||||
mainbus0 at root
|
||||
|
|
@ -25,9 +25,9 @@ apbh0 at mainbus? base 0x80000000 size 0x00040000
|
|||
icoll0 at apbh? addr 0x80000000 size 0x2000 irq -1
|
||||
|
||||
# Synchronous serial port for SD/MMC
|
||||
#ssp0 at apbh? addr 0x80010000 size 0x2000 irq 15
|
||||
#sdmmc* at ssp?
|
||||
#ld* at sdmmc?
|
||||
ssp0 at apbh? addr 0x80010000 size 0x2000 irq 15
|
||||
sdmmc* at ssp?
|
||||
ld* at sdmmc?
|
||||
|
||||
# APBX bus
|
||||
apbx0 at mainbus? base 0x80040000 size 0x00040000
|
||||
|
|
@ -47,11 +47,7 @@ options MEMSIZE=64
|
|||
options DDB
|
||||
options HZ=100
|
||||
|
||||
options MEMORY_DISK_HOOKS
|
||||
options MEMORY_DISK_IS_ROOT
|
||||
options MEMORY_DISK_ROOT_SIZE=12288 # 6 megs
|
||||
options MEMORY_DISK_RBFLAGS=RB_SINGLE
|
||||
|
||||
pseudo-device md
|
||||
|
||||
file-system FFS
|
||||
file-system EXT2FS
|
||||
file-system MSDOSFS
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue