- check whether tv_usec == 1000000, too.
- set the reload count of the timer unit 1 correctly (Timer unit counts from TCOR to 0 (i.e. the length of the counts equals to TCOR + 1)). - use macros.
This commit is contained in:
parent
8cf5a56c3f
commit
c330a893d5
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@ -1,4 +1,4 @@
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/* $NetBSD: clock.c,v 1.6 2000/01/15 02:46:30 msaitoh Exp $ */
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/* $NetBSD: clock.c,v 1.7 2000/01/17 21:54:32 msaitoh Exp $ */
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/*-
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/*-
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* Copyright (c) 1993, 1994 Charles Hannum.
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* Copyright (c) 1993, 1994 Charles Hannum.
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@ -161,14 +161,14 @@ microtime(tvp)
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#endif
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#endif
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tvp->tv_usec += ticks;
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tvp->tv_usec += ticks;
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while (tvp->tv_usec > 1000000) {
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while (tvp->tv_usec >= 1000000) {
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tvp->tv_usec -= 1000000;
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tvp->tv_usec -= 1000000;
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tvp->tv_sec++;
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tvp->tv_sec++;
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}
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}
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#endif
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#endif
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if (tvp->tv_sec == lasttime.tv_sec &&
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if (tvp->tv_sec == lasttime.tv_sec &&
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tvp->tv_usec <= lasttime.tv_usec &&
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tvp->tv_usec <= lasttime.tv_usec &&
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(tvp->tv_usec = lasttime.tv_usec + 1) > 1000000) {
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(tvp->tv_usec = lasttime.tv_usec + 1) >= 1000000) {
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tvp->tv_sec++;
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tvp->tv_sec++;
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tvp->tv_usec -= 1000000;
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tvp->tv_usec -= 1000000;
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}
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}
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@ -269,7 +269,7 @@ findcpuspeed()
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unsigned int remainder;
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unsigned int remainder;
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/* using clock = Internal RTC */
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/* using clock = Internal RTC */
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SHREG_TOCR = 0x01;
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SHREG_TOCR = TOCR_TCOE;
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/* disable Under Flow int,up rising edge, 1/4 Cys */
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/* disable Under Flow int,up rising edge, 1/4 Cys */
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SHREG_TCR0 = 0;
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SHREG_TCR0 = 0;
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@ -279,8 +279,8 @@ findcpuspeed()
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/* set counter */
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/* set counter */
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SHREG_TCNT0 = 0xffffffff;
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SHREG_TCNT0 = 0xffffffff;
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/* start counter */
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/* start counter 0 */
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SHREG_TSTR = 0x01;
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SHREG_TSTR |= TSTR_STR0;
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/* Timer counter is decremented at every 0.5 uSec */
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/* Timer counter is decremented at every 0.5 uSec */
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for (i = FIRST_GUESS; i; i--)
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for (i = FIRST_GUESS; i; i--)
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@ -300,18 +300,18 @@ cpu_initclocks()
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#ifdef USE_RTCCLK
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#ifdef USE_RTCCLK
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/* enable under flow interrupt, up rising edge, RTCCLK */
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/* enable under flow interrupt, up rising edge, RTCCLK */
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/* RTCCLK == 16kHz */
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/* RTCCLK == 16kHz */
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SHREG_TCR1 = 0x0024;
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SHREG_TCR1 = TCR_UNIE | TCR_TPSC_RTC;
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SHREG_TCOR1 = 16000 / hz; /* about 1/HZ Sec */
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SHREG_TCOR1 = 16000 / hz - 1; /* about 1/HZ Sec */
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SHREG_TCNT1 = 16000 / hz; /* about 1/HZ Sec */
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SHREG_TCNT1 = 16000 / hz - 1; /* about 1/HZ Sec */
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#else
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#else
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/* enable under flow interrupt, up rising edge, 1/16 Pcyc */
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/* enable under flow interrupt, up rising edge, 1/16 Pcyc */
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SHREG_TCR1 = 0x0021;
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SHREG_TCR1 = TCR_UNIE | TCR_TPSC_P16;
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SHREG_TCOR1 = PCLOCK / 16 / hz; /* about 1/HZ Sec */
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SHREG_TCOR1 = PCLOCK / 16 / hz - 1; /* about 1/HZ Sec */
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SHREG_TCNT1 = PCLOCK / 16 / hz; /* about 1/HZ Sec */
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SHREG_TCNT1 = PCLOCK / 16 / hz - 1; /* about 1/HZ Sec */
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#endif
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#endif
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/* start timer counter 1 */
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/* start timer counter 1 */
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SHREG_TSTR |= 0x02;
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SHREG_TSTR |= TSTR_STR1;
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(void)shb_intr_establish(TMU1_IRQ, IST_EDGE, IPL_CLOCK, clockintr, 0);
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(void)shb_intr_establish(TMU1_IRQ, IST_EDGE, IPL_CLOCK, clockintr, 0);
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}
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}
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