Add a workaround for jumbo frame on PCH2 and newer. Tested by chs@.
- Add wm_lv_jumbo_workaround_ich8lan() and use it. From FreeBSD. XXX For KUMCTRLSTA_OFFSET_HD_CTRL register modification, it's doubtful. FreeBSD and Linux do the same thing that they set the same value on both jumbo frame's enable case and the disable case. It seems the default value is 0x0b0c and it's not changed on the enable case, so it might be a bug on the enable case or the modification is not required. - Rename I219_UNKNOWN1 to I82579_UNKNOWN1.
This commit is contained in:
msaitoh
parent
d5e1a6b065
commit
c30bad5e0d
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@ -1,4 +1,4 @@
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/* $NetBSD: inbmphyreg.h,v 1.19 2019/12/11 07:33:55 msaitoh Exp $ */
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/* $NetBSD: inbmphyreg.h,v 1.20 2020/09/16 15:04:01 msaitoh Exp $ */
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/*******************************************************************************
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Copyright (c) 2001-2015, Intel Corporation
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All rights reserved.
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@ -136,6 +136,8 @@ POSSIBILITY OF SUCH DAMAGE.
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#define BM_PORT_GEN_CFG BME1000_REG(BM_PORT_CTRL_PAGE, 17)
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#define I82579_DFT_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 20)
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#define CV_SMB_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 23)
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#define CV_SMB_CTRL_FORCE_SMBUS __BIT(0)
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@ -180,7 +182,8 @@ POSSIBILITY OF SUCH DAMAGE.
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#define HV_MUX_DATA_CTRL_FORCE_SPEED (1 << 2)
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#define HV_MUX_DATA_CTRL_GEN_TO_MAC (1 << 10)
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#define I219_UNKNOWN1 BME1000_REG(776, 20)
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#define I82579_UNKNOWN1 BME1000_REG(776, 20)
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#define I82579_TX_PTR_GAP 0x1f
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#define I218_ULP_CONFIG1 BME1000_REG(779, 16)
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#define I218_ULP_CONFIG1_START __BIT(0)
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wm.c,v 1.687 2020/09/15 08:39:04 msaitoh Exp $ */
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/* $NetBSD: if_wm.c,v 1.688 2020/09/16 15:04:01 msaitoh Exp $ */
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/*
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* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
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@ -82,7 +82,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.687 2020/09/15 08:39:04 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.688 2020/09/16 15:04:01 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_net_mpsafe.h"
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@ -1016,6 +1016,8 @@ static int wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
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static void wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
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static int wm_hv_phy_workarounds_ich8lan(struct wm_softc *);
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static void wm_copy_rx_addrs_to_phy_ich8lan(struct wm_softc *);
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static void wm_copy_rx_addrs_to_phy_ich8lan_locked(struct wm_softc *);
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static int wm_lv_jumbo_workaround_ich8lan(struct wm_softc *, bool);
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static int wm_lv_phy_workarounds_ich8lan(struct wm_softc *);
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static int wm_k1_workaround_lpt_lp(struct wm_softc *, bool);
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static int wm_k1_gig_workaround_hv(struct wm_softc *, int);
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@ -3802,7 +3804,7 @@ wm_set_filter(struct wm_softc *sc)
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struct ether_multistep step;
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bus_addr_t mta_reg;
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uint32_t hash, reg, bit;
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int i, size, ralmax;
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int i, size, ralmax, rv;
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DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
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device_xname(sc->sc_dev), __func__));
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@ -3928,6 +3930,17 @@ wm_set_filter(struct wm_softc *sc)
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sc->sc_rctl |= RCTL_MPE;
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setit:
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if (sc->sc_type >= WM_T_PCH2) {
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if (((ec->ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
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&& (ifp->if_mtu > ETHERMTU))
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rv = wm_lv_jumbo_workaround_ich8lan(sc, true);
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else
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rv = wm_lv_jumbo_workaround_ich8lan(sc, false);
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if (rv != 0)
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device_printf(sc->sc_dev,
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"Failed to do workaround for jumbo frame.\n");
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}
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CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
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}
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@ -9312,7 +9325,7 @@ wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr)
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return;
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rv = sc->phy.readreg_locked(dev, 2,
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I219_UNKNOWN1, &data);
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I82579_UNKNOWN1, &data);
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if (rv) {
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sc->phy.release(sc);
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return;
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@ -9323,7 +9336,7 @@ wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr)
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data &= ~(0x3ff << 2);
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data |= (0x18 << 2);
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rv = sc->phy.writereg_locked(dev,
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2, I219_UNKNOWN1, data);
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2, I82579_UNKNOWN1, data);
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}
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sc->phy.release(sc);
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if (rv)
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@ -9334,7 +9347,7 @@ wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr)
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return;
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rv = sc->phy.writereg_locked(dev, 2,
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I219_UNKNOWN1, 0xc023);
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I82579_UNKNOWN1, 0xc023);
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sc->phy.release(sc);
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if (rv)
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return;
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@ -15882,18 +15895,31 @@ release:
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static void
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wm_copy_rx_addrs_to_phy_ich8lan(struct wm_softc *sc)
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{
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device_t dev = sc->sc_dev;
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uint32_t mac_reg;
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uint16_t i, wuce;
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int count;
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DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
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device_xname(sc->sc_dev), __func__));
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if (sc->phy.acquire(sc) != 0)
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return;
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wm_copy_rx_addrs_to_phy_ich8lan_locked(sc);
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sc->phy.release(sc);
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}
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static void
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wm_copy_rx_addrs_to_phy_ich8lan_locked(struct wm_softc *sc)
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{
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device_t dev = sc->sc_dev;
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uint32_t mac_reg;
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uint16_t i, wuce;
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int count;
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DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
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device_xname(dev), __func__));
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if (wm_enable_phy_wakeup_reg_access_bm(dev, &wuce) != 0)
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goto release;
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return;
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/* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
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count = wm_rar_count(sc);
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@ -15913,9 +15939,182 @@ wm_copy_rx_addrs_to_phy_ich8lan(struct wm_softc *sc)
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}
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wm_disable_phy_wakeup_reg_access_bm(dev, &wuce);
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}
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release:
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/*
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* wm_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
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* with 82579 PHY
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* @enable: flag to enable/disable workaround when enabling/disabling jumbos
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*/
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static int
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wm_lv_jumbo_workaround_ich8lan(struct wm_softc *sc, bool enable)
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{
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device_t dev = sc->sc_dev;
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int rar_count;
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int rv;
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uint32_t mac_reg;
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uint16_t dft_ctrl, data;
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uint16_t i;
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DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
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device_xname(dev), __func__));
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if (sc->sc_type < WM_T_PCH2)
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return 0;
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/* Acquire PHY semaphore */
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rv = sc->phy.acquire(sc);
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if (rv != 0)
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return rv;
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/* Disable Rx path while enabling/disabling workaround */
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sc->phy.readreg_locked(dev, 2, I82579_DFT_CTRL, &dft_ctrl);
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if (rv != 0)
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goto out;
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rv = sc->phy.writereg_locked(dev, 2, I82579_DFT_CTRL,
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dft_ctrl | (1 << 14));
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if (rv != 0)
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goto out;
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if (enable) {
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/* Write Rx addresses (rar_entry_count for RAL/H, and
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* SHRAL/H) and initial CRC values to the MAC
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*/
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rar_count = wm_rar_count(sc);
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for (i = 0; i < rar_count; i++) {
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uint8_t mac_addr[ETHER_ADDR_LEN] = {0};
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uint32_t addr_high, addr_low;
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addr_high = CSR_READ(sc, WMREG_CORDOVA_RAH(i));
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if (!(addr_high & RAL_AV))
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continue;
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addr_low = CSR_READ(sc, WMREG_CORDOVA_RAL(i));
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mac_addr[0] = (addr_low & 0xFF);
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mac_addr[1] = ((addr_low >> 8) & 0xFF);
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mac_addr[2] = ((addr_low >> 16) & 0xFF);
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mac_addr[3] = ((addr_low >> 24) & 0xFF);
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mac_addr[4] = (addr_high & 0xFF);
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mac_addr[5] = ((addr_high >> 8) & 0xFF);
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CSR_WRITE(sc, WMREG_PCH_RAICC(i),
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~ether_crc32_le(mac_addr, ETHER_ADDR_LEN));
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}
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/* Write Rx addresses to the PHY */
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wm_copy_rx_addrs_to_phy_ich8lan_locked(sc);
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}
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/*
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* If enable ==
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* true: Enable jumbo frame workaround in the MAC.
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* false: Write MAC register values back to h/w defaults.
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*/
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mac_reg = CSR_READ(sc, WMREG_FFLT_DBG);
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if (enable) {
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mac_reg &= ~(1 << 14);
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mac_reg |= (7 << 15);
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} else
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mac_reg &= ~(0xf << 14);
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CSR_WRITE(sc, WMREG_FFLT_DBG, mac_reg);
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mac_reg = CSR_READ(sc, WMREG_RCTL);
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if (enable) {
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mac_reg |= RCTL_SECRC;
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sc->sc_rctl |= RCTL_SECRC;
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sc->sc_flags |= WM_F_CRC_STRIP;
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} else {
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mac_reg &= ~RCTL_SECRC;
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sc->sc_rctl &= ~RCTL_SECRC;
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sc->sc_flags &= ~WM_F_CRC_STRIP;
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}
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CSR_WRITE(sc, WMREG_RCTL, mac_reg);
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rv = wm_kmrn_readreg_locked(sc, KUMCTRLSTA_OFFSET_CTRL, &data);
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if (rv != 0)
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goto out;
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if (enable)
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data |= 1 << 0;
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else
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data &= ~(1 << 0);
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rv = wm_kmrn_writereg_locked(sc, KUMCTRLSTA_OFFSET_CTRL, data);
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if (rv != 0)
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goto out;
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rv = wm_kmrn_readreg_locked(sc, KUMCTRLSTA_OFFSET_HD_CTRL, &data);
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if (rv != 0)
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goto out;
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/*
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* XXX FreeBSD and Linux do the same thing that they set the same value
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* on both the enable case and the disable case. Is it correct?
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*/
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data &= ~(0xf << 8);
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data |= (0xb << 8);
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rv = wm_kmrn_writereg_locked(sc, KUMCTRLSTA_OFFSET_HD_CTRL, data);
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if (rv != 0)
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goto out;
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/*
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* If enable ==
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* true: Enable jumbo frame workaround in the PHY.
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* false: Write PHY register values back to h/w defaults.
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*/
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rv = sc->phy.readreg_locked(dev, 2, BME1000_REG(769, 23), &data);
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if (rv != 0)
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goto out;
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data &= ~(0x7F << 5);
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if (enable)
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data |= (0x37 << 5);
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rv = sc->phy.writereg_locked(dev, 2, BME1000_REG(769, 23), data);
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if (rv != 0)
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goto out;
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rv = sc->phy.readreg_locked(dev, 2, BME1000_REG(769, 16), &data);
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if (rv != 0)
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goto out;
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if (enable)
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data &= ~(1 << 13);
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else
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data |= (1 << 13);
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rv = sc->phy.writereg_locked(dev, 2, BME1000_REG(769, 16), data);
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if (rv != 0)
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goto out;
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rv = sc->phy.readreg_locked(dev, 2, I82579_UNKNOWN1, &data);
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if (rv != 0)
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goto out;
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data &= ~(0x3FF << 2);
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if (enable)
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data |= (I82579_TX_PTR_GAP << 2);
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else
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data |= (0x8 << 2);
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rv = sc->phy.writereg_locked(dev, 2, I82579_UNKNOWN1, data);
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if (rv != 0)
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goto out;
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rv = sc->phy.writereg_locked(dev, 2, BME1000_REG(776, 23),
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enable ? 0xf100 : 0x7e00);
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if (rv != 0)
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goto out;
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rv = sc->phy.readreg_locked(dev, 2, HV_PM_CTRL, &data);
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if (rv != 0)
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goto out;
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if (enable)
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data |= 1 << 10;
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else
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data &= ~(1 << 10);
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rv = sc->phy.writereg_locked(dev, 2, HV_PM_CTRL, data);
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if (rv != 0)
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goto out;
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/* Re-enable Rx path after enabling/disabling workaround */
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rv = sc->phy.writereg_locked(dev, 2, I82579_DFT_CTRL,
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dft_ctrl & ~(1 << 14));
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out:
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sc->phy.release(sc);
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return rv;
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}
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wmreg.h,v 1.119 2020/01/08 03:51:37 msaitoh Exp $ */
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/* $NetBSD: if_wmreg.h,v 1.120 2020/09/16 15:04:02 msaitoh Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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@ -1379,7 +1379,10 @@ struct livengood_tcpip_ctxdesc {
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#define WMREG_FEXTNVM11 0x5bbc /* Future Extended NVM 11 */
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#define FEXTNVM11_DIS_MULRFIX __BIT(13) /* Disable MULR fix */
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#define WMREG_FFLT_DBG 0x05F04 /* Debug Register */
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#define WMREG_CRC_OFFSET 0x5f50
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#define WMREG_PCH_RAICC(x) (WMREG_CRC_OFFSET + (x) * 4)
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#define WMREG_EEC 0x12010
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#define EEC_FLASH_DETECTED (1U << 19) /* FLASH */
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Reference in New Issue