Add a driver for Realtek RTS5209/RTS5229 Card Reader.
Ported from OpenBSD.
This commit is contained in:
nonaka
parent
4ae43925ec
commit
c3077021ad
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@ -1,4 +1,4 @@
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# $NetBSD: mi,v 1.1464 2014/03/16 09:28:58 martin Exp $
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# $NetBSD: mi,v 1.1465 2014/03/19 15:26:41 nonaka Exp $
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#
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# Note: don't delete entries from here - mark them as "obsolete" instead.
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#
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@ -1564,6 +1564,7 @@
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./usr/share/man/cat4/rtii.0 man-sys-catman .cat
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./usr/share/man/cat4/rtk.0 man-sys-catman .cat
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./usr/share/man/cat4/rtpphy.0 man-obsolete obsolete
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./usr/share/man/cat4/rtsx.0 man-sys-catman .cat
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./usr/share/man/cat4/rtw.0 man-sys-catman .cat
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./usr/share/man/cat4/rum.0 man-sys-catman .cat
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./usr/share/man/cat4/rumpfs.0 man-sys-catman .cat,rump
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@ -4530,6 +4531,7 @@
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./usr/share/man/html4/rtfps.html man-sys-htmlman html
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./usr/share/man/html4/rtii.html man-sys-htmlman html
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./usr/share/man/html4/rtk.html man-sys-htmlman html
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./usr/share/man/html4/rtsx.html man-sys-htmlman html
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./usr/share/man/html4/rtw.html man-sys-htmlman html
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./usr/share/man/html4/rum.html man-sys-htmlman html
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./usr/share/man/html4/rumpfs.html man-sys-htmlman html,rump
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@ -7400,6 +7402,7 @@
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./usr/share/man/man4/rtii.4 man-sys-man .man
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./usr/share/man/man4/rtk.4 man-sys-man .man
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./usr/share/man/man4/rtpphy.4 man-obsolete obsolete
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./usr/share/man/man4/rtsx.4 man-sys-man .man
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./usr/share/man/man4/rtw.4 man-sys-man .man
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./usr/share/man/man4/rum.4 man-sys-man .man
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./usr/share/man/man4/rumpfs.4 man-sys-man .man,rump
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@ -1,4 +1,4 @@
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# $NetBSD: Makefile,v 1.610 2014/03/16 09:28:43 martin Exp $
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# $NetBSD: Makefile,v 1.611 2014/03/19 15:26:41 nonaka Exp $
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# @(#)Makefile 8.1 (Berkeley) 6/18/93
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MAN= aac.4 ac97.4 acardide.4 aceride.4 acphy.4 \
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@ -49,7 +49,7 @@ MAN= aac.4 ac97.4 acardide.4 aceride.4 acphy.4 \
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pseye.4 ptcd.4 ptm.4 pty.4 puc.4 pud.4 puffs.4 pwdog.4 px.4 pxg.4 \
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qe.4 qec.4 qsphy.4 \
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raid.4 ral.4 ray.4 rcons.4 rdcphy.4 re.4 rgephy.4 rlphy.4 \
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rnd.4 route.4 rs5c372rtc.4 rtk.4 rtw.4 rum.4 run.4 \
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rnd.4 route.4 rs5c372rtc.4 rtk.4 rtsx.4 rtw.4 rum.4 run.4 \
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s390rtc.4 satalink.4 sbus.4 scc.4 schide.4 \
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scsi.4 sd.4 se.4 seeprom.4 sem.4 \
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ses.4 sf.4 sfb.4 sgsmix.4 shb.4 shmif.4 \
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@ -0,0 +1,55 @@
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.\" $NetBSD: rtsx.4,v 1.1 2014/03/19 15:26:41 nonaka Exp $
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.\" $OpenBSD: rtsx.4,v 1.4 2013/11/06 13:51:02 stsp Exp $
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.\"
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.\" Theo de Raadt, 2006. Public Domain.
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.\" Stefan Sperling, 2012. Public Domain.
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.\"
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.Dd March 19 2014
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.Dt RTSX 4
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.Os
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.Sh NAME
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.Nm rtsx
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.Nd Realtek SD card reader
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.Sh SYNOPSIS
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.Cd "rtsx* at pci?"
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.Cd "sdmmc* at rtsx?"
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.Sh DESCRIPTION
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The
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.Nm
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driver provides support for the Realtek RTS5209 and RTS5229 SD card readers.
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.Pp
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The
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.Xr sdmmc 4
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subsystem performs SD/MMC transactions to communicate with
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whatever MMC, SD or SDHC devices are inserted into the SD slot.
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.Sh SEE ALSO
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.Xr intro 4 ,
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.Xr sdmmc 4
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.Sh HISTORY
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The
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.Nm
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driver first appeared in
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.Ox 5.3
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and in
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.Nx 7.0 .
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.Sh AUTHORS
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.An -nosplit
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The
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.Nm
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driver was written by
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.An Stefan Sperling
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.Aq stsp@openbsd.org
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for
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.Ox
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and ported to
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.Nx
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by
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.An NONAKA Kimihiro
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.Aq nonaka@netbsd.org .
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.Sh BUGS
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The
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.Nm
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driver does not support MS (Memory Stick) and xD (Extreme Digital) devices
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even though the hardware supports them.
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.Pp
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Support for SDIO interrupts is not implemented.
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@ -1,4 +1,4 @@
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.\" $NetBSD: sdmmc.4,v 1.4 2009/10/01 05:42:22 wiz Exp $
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.\" $NetBSD: sdmmc.4,v 1.5 2014/03/19 15:26:41 nonaka Exp $
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.\" $OpenBSD: sdmmc.4,v 1.8 2009/03/25 19:33:06 mk Exp $
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.\"
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.\" Theo de Raadt, 2006. Public Domain.
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@ -13,6 +13,7 @@
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.Cd "# pxa2x0 specific"
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.Cd "sdmmc* at pxamci?"
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.Cd "# all architectures"
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.Cd "sdmmc* at rtsx?"
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.Cd "sdmmc* at sdhc?"
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.Cd "sdmmc* at wb?"
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.Cd "ld* at sdmmc?"
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@ -27,6 +28,7 @@ Standard SD/SDHC memory devices will show up as a logical disk, using
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.Sh SEE ALSO
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.Xr intro 4 ,
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.Xr ld 4 ,
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.Xr rtsx 4 ,
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.Xr sbt 4 ,
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.Xr sdhc 4 ,
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.Xr wb 4
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@ -1,4 +1,4 @@
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# $NetBSD: GENERIC,v 1.381 2013/10/26 09:16:20 nonaka Exp $
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# $NetBSD: GENERIC,v 1.382 2014/03/19 15:26:42 nonaka Exp $
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#
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# GENERIC machine description file
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#
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@ -22,7 +22,7 @@ include "arch/amd64/conf/std.amd64"
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options INCLUDE_CONFIG_FILE # embed config file in kernel binary
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#ident "GENERIC-$Revision: 1.381 $"
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#ident "GENERIC-$Revision: 1.382 $"
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maxusers 64 # estimated number of users
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@ -1146,8 +1146,10 @@ btsco* at bthub?
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# SD/MMC controller
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sdhc* at pci? # SD Host Controller
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rtsx* at pci? # Realtek RTS5209/RTS5229 Card Reader
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sdhc* at cardbus? # SD Host Controller
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sdmmc* at sdhc? # SD/MMC bus
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sdmmc* at rtsx? # SD/MMC bus
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ld* at sdmmc?
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@ -1,4 +1,4 @@
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# $NetBSD: ALL,v 1.368 2014/03/16 09:35:05 martin Exp $
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# $NetBSD: ALL,v 1.369 2014/03/19 15:26:42 nonaka Exp $
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# From NetBSD: GENERIC,v 1.787 2006/10/01 18:37:54 bouyer Exp
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#
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# ALL machine description file
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@ -17,7 +17,7 @@ include "arch/i386/conf/std.i386"
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options INCLUDE_CONFIG_FILE # embed config file in kernel binary
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#ident "ALL-$Revision: 1.368 $"
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#ident "ALL-$Revision: 1.369 $"
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maxusers 64 # estimated number of users
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@ -1415,11 +1415,13 @@ sbp* at ieee1394if? euihi ? euilo ? # SCSI over IEEE1394
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# PCI SD/MMC controller
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sdhc* at pci? # SD Host Controller
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rtsx* at pci? # Realtek RTS5209/RTS5229 Card Reader
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# CardBus SD/MMC controller
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sdhc* at cardbus? function ? # SD Host Controller
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sdmmc* at sdhc? # SD/MMC bus
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sdmmc* at rtsx? # SD/MMC bus
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ld* at sdmmc?
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@ -1,4 +1,4 @@
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# $NetBSD: GENERIC,v 1.1099 2014/01/26 19:16:16 dsl Exp $
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# $NetBSD: GENERIC,v 1.1100 2014/03/19 15:26:42 nonaka Exp $
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#
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# GENERIC machine description file
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#
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@ -22,7 +22,7 @@ include "arch/i386/conf/std.i386"
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options INCLUDE_CONFIG_FILE # embed config file in kernel binary
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#ident "GENERIC-$Revision: 1.1099 $"
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#ident "GENERIC-$Revision: 1.1100 $"
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maxusers 64 # estimated number of users
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@ -1340,11 +1340,13 @@ sbp* at ieee1394if? euihi ? euilo ? # SCSI over IEEE1394
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# PCI SD/MMC controller
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sdhc* at pci? # SD Host Controller
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rtsx* at pci? # Realtek RTS5209/RTS5229 Card Reader
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# CardBus SD/MMC controller
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sdhc* at cardbus? function ? # SD Host Controller
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sdmmc* at sdhc? # SD/MMC bus
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sdmmc* at rtsx? # SD/MMC bus
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ld* at sdmmc?
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@ -1,4 +1,4 @@
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# $NetBSD: files,v 1.1086 2014/03/18 18:20:41 riastradh Exp $
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# $NetBSD: files,v 1.1087 2014/03/19 15:26:42 nonaka Exp $
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# @(#)files.newconf 7.5 (Berkeley) 5/10/93
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version 20100430
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@ -1221,7 +1221,7 @@ define hid
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file dev/usb/hid.c hid
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# SD Host controller
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device sdhc: sdmmcbus
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device sdhc: sdmmcbus
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file dev/sdmmc/sdhc.c sdhc needs-flag
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# Winbond Integrated Media Reader
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@ -1229,6 +1229,10 @@ device wb: sdmmcbus
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file dev/ic/w83l518d.c wb
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file dev/ic/w83l518d_sdmmc.c wb
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# Realtek RTS5209/RTS5229 Card Reader
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device rtsx: sdmmcbus
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file dev/ic/rtsx.c rtsx
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# Myson MTD803 3-in-1 Fast Ethernet Controller
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device mtd: arp, ether, ifnet, mii
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file dev/ic/mtd803.c mtd
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@ -1,4 +1,4 @@
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# $NetBSD: DEVNAMES,v 1.287 2014/02/21 12:24:52 jdc Exp $
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# $NetBSD: DEVNAMES,v 1.288 2014/03/19 15:26:42 nonaka Exp $
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#
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# This file contains all used device names and defined attributes in
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# alphabetical order. New devices added to the system somewhere should first
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@ -1179,6 +1179,7 @@ rtfps MI
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rtii MI
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rtk MI
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rtl80x9 MI Attribute
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rtsx MI
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rum MI
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run MI
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rx MI
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@ -1223,6 +1224,8 @@ scsi MI Attribute
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scsibus MI
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scsirom x68k
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sd MI
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sdhc MI
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sdmmc MI
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sdtemp MI
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se MI
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sea MI
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,522 @@
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/* $NetBSD: rtsxreg.h,v 1.1 2014/03/19 15:26:41 nonaka Exp $ */
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/* $OpenBSD: rtsxreg.h,v 1.3 2013/11/26 20:33:16 deraadt Exp $ */
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/*
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* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
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* Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _RTSXREG_H_
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#define _RTSXREG_H_
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/* Host command buffer control register. */
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#define RTSX_HCBAR 0x00
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#define RTSX_HCBCTLR 0x04
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#define RTSX_START_CMD (1U << 31)
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#define RTSX_HW_AUTO_RSP (1U << 30)
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#define RTSX_STOP_CMD (1U << 28)
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/* Host data buffer control register. */
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#define RTSX_HDBAR 0x08
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#define RTSX_HDBCTLR 0x0C
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#define RTSX_TRIG_DMA (1U << 31)
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#define RTSX_DMA_READ (1U << 29)
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#define RTSX_STOP_DMA (1U << 28)
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#define RTSX_ADMA_MODE (2U << 26)
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/* Interrupt pending register. */
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#define RTSX_BIPR 0x14
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#define RTSX_CMD_DONE_INT (1U << 31)
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#define RTSX_DATA_DONE_INT (1U << 30)
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#define RTSX_TRANS_OK_INT (1U << 29)
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#define RTSX_TRANS_FAIL_INT (1U << 28)
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#define RTSX_XD_INT (1U << 27)
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#define RTSX_MS_INT (1U << 26)
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#define RTSX_SD_INT (1U << 25)
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#define RTSX_SD_WRITE_PROTECT (1U << 19)
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#define RTSX_XD_EXIST (1U << 18)
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#define RTSX_MS_EXIST (1U << 17)
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#define RTSX_SD_EXIST (1U << 16)
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#define RTSX_CARD_EXIST (RTSX_XD_EXIST|RTSX_MS_EXIST|RTSX_SD_EXIST)
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#define RTSX_CARD_INT (RTSX_XD_INT|RTSX_MS_INT|RTSX_SD_INT)
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/* Chip register access. */
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#define RTSX_HAIMR 0x10
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#define RTSX_HAIMR_WRITE 0x40000000
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#define RTSX_HAIMR_BUSY 0x80000000
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/* Interrupt enable register. */
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#define RTSX_BIER 0x18
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#define RTSX_CMD_DONE_INT_EN (1U << 31)
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#define RTSX_DATA_DONE_INT_EN (1U << 30)
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#define RTSX_TRANS_OK_INT_EN (1U << 29)
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#define RTSX_TRANS_FAIL_INT_EN (1U << 28)
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#define RTSX_XD_INT_EN (1U << 27)
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#define RTSX_MS_INT_EN (1U << 26)
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#define RTSX_SD_INT_EN (1U << 25)
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#define RTSX_GPIO0_INT_EN (1U << 24)
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#define RTSX_MS_OC_INT_EN (1U << 23)
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#define RTSX_SD_OC_INT_EN (1U << 22)
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/* Power on/off. */
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#define RTSX_FPDCTL 0xFC00
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#define RTSX_SSC_POWER_DOWN 0x01
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#define RTSX_SD_OC_POWER_DOWN 0x02
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#define RTSX_MS_OC_POWER_DOWN 0x04
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#define RTSX_ALL_POWER_DOWN 0x07
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#define RTSX_OC_POWER_DOWN 0x06
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/* Card power control register. */
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#define RTSX_CARD_PWR_CTL 0xFD50
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#define RTSX_SD_PWR_ON 0x00
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#define RTSX_SD_PARTIAL_PWR_ON 0x01
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#define RTSX_SD_PWR_OFF 0x03
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#define RTSX_SD_PWR_MASK 0x03
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#define RTSX_PMOS_STRG_MASK 0x10
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#define RTSX_PMOS_STRG_400mA 0x00
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#define RTSX_PMOS_STRG_800mA 0x10
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#define RTSX_MS_PWR_OFF 0x0C
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#define RTSX_MS_PWR_ON 0x00
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#define RTSX_MS_PARTIAL_PWR_ON 0x04
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#define RTSX_CARD_SHARE_MODE 0xFD52
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#define RTSX_CARD_SHARE_48_XD 0x02
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#define RTSX_CARD_SHARE_48_SD 0x04
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#define RTSX_CARD_SHARE_48_MS 0x08
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#define RTSX_CARD_DRIVE_SEL 0xFE53
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/* Card clock. */
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#define RTSX_CARD_CLK_EN 0xFD69
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#define RTSX_XD_CLK_EN 0x02
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#define RTSX_SD_CLK_EN 0x04
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#define RTSX_MS_CLK_EN 0x08
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#define RTSX_SPI_CLK_EN 0x10
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#define RTSX_CARD_CLK_EN_ALL \
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(RTSX_XD_CLK_EN|RTSX_SD_CLK_EN|RTSX_MS_CLK_EN|RTSX_SPI_CLK_EN)
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#define RTSX_SDIO_CTRL 0xFD6B
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#define RTSX_SDIO_BUS_CTRL 0x01
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#define RTSX_SDIO_CD_CTRL 0x02
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/* Internal clock. */
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#define RTSX_CLK_CTL 0xFC02
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#define RTSX_CLK_LOW_FREQ 0x01
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/* Internal clock divisor values. */
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#define RTSX_CLK_DIV 0xFC03
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#define RTSX_CLK_DIV_1 0x01
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#define RTSX_CLK_DIV_2 0x02
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#define RTSX_CLK_DIV_4 0x03
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#define RTSX_CLK_DIV_8 0x04
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/* Internal clock selection. */
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#define RTSX_CLK_SEL 0xFC04
|
||||
#define RTSX_SSC_80 0
|
||||
#define RTSX_SSC_100 1
|
||||
#define RTSX_SSC_120 2
|
||||
#define RTSX_SSC_150 3
|
||||
#define RTSX_SSC_200 4
|
||||
|
||||
#define RTSX_SSC_DIV_N_0 0xFC0F
|
||||
|
||||
#define RTSX_SSC_CTL1 0xFC11
|
||||
#define RTSX_RSTB 0x80
|
||||
#define RTSX_SSC_8X_EN 0x40
|
||||
#define RTSX_SSC_FIX_FRAC 0x20
|
||||
#define RTSX_SSC_SEL_1M 0x00
|
||||
#define RTSX_SSC_SEL_2M 0x08
|
||||
#define RTSX_SSC_SEL_2M 0x08
|
||||
#define RTSX_SSC_SEL_4M 0x10
|
||||
#define RTSX_SSC_SEL_8M 0x18
|
||||
#define RTSX_SSC_CTL2 0xFC12
|
||||
#define RTSX_SSC_DEPTH_MASK 0x07
|
||||
|
||||
/* RC oscillator, default is 2M */
|
||||
#define RTSX_RCCTL 0xFC14
|
||||
#define RTSX_RCCTL_F_400K 0x0
|
||||
#define RTSX_RCCTL_F_2M 0x1
|
||||
|
||||
/* RTS5229-only. */
|
||||
#define RTSX_OLT_LED_CTL 0xFC1E
|
||||
#define RTSX_OLT_LED_PERIOD 0x02
|
||||
#define RTSX_OLT_LED_AUTOBLINK 0x08
|
||||
|
||||
#define RTSX_GPIO_CTL 0xFC1F
|
||||
#define RTSX_GPIO_LED_ON 0x02
|
||||
|
||||
/* Host controller commands. */
|
||||
#define RTSX_READ_REG_CMD 0
|
||||
#define RTSX_WRITE_REG_CMD 1
|
||||
#define RTSX_CHECK_REG_CMD 2
|
||||
|
||||
|
||||
#define RTSX_OCPCTL 0xFC15
|
||||
#define RTSX_OCPSTAT 0xFC16
|
||||
#define RTSX_OCPGLITCH 0xFC17
|
||||
#define RTSX_OCPPARA1 0xFC18
|
||||
#define RTSX_OCPPARA2 0xFC19
|
||||
|
||||
/* FPGA */
|
||||
#define RTSX_FPGA_PULL_CTL 0xFC1D
|
||||
#define RTSX_FPGA_MS_PULL_CTL_BIT 0x10
|
||||
#define RTSX_FPGA_SD_PULL_CTL_BIT 0x08
|
||||
|
||||
/* Clock source configuration register. */
|
||||
#define RTSX_CARD_CLK_SOURCE 0xFC2E
|
||||
#define RTSX_CRC_FIX_CLK (0x00 << 0)
|
||||
#define RTSX_CRC_VAR_CLK0 (0x01 << 0)
|
||||
#define RTSX_CRC_VAR_CLK1 (0x02 << 0)
|
||||
#define RTSX_SD30_FIX_CLK (0x00 << 2)
|
||||
#define RTSX_SD30_VAR_CLK0 (0x01 << 2)
|
||||
#define RTSX_SD30_VAR_CLK1 (0x02 << 2)
|
||||
#define RTSX_SAMPLE_FIX_CLK (0x00 << 4)
|
||||
#define RTSX_SAMPLE_VAR_CLK0 (0x01 << 4)
|
||||
#define RTSX_SAMPLE_VAR_CLK1 (0x02 << 4)
|
||||
|
||||
|
||||
/* ASIC */
|
||||
#define RTSX_CARD_PULL_CTL1 0xFD60
|
||||
#define RTSX_CARD_PULL_CTL2 0xFD61
|
||||
#define RTSX_CARD_PULL_CTL3 0xFD62
|
||||
|
||||
#define RTSX_PULL_CTL_DISABLE12 0x55
|
||||
#define RTSX_PULL_CTL_DISABLE3 0xD5
|
||||
#define RTSX_PULL_CTL_DISABLE3_TYPE_C 0xE5
|
||||
#define RTSX_PULL_CTL_ENABLE12 0xAA
|
||||
#define RTSX_PULL_CTL_ENABLE3 0xE9
|
||||
#define RTSX_PULL_CTL_ENABLE3_TYPE_C 0xD9
|
||||
|
||||
/* SD configuration register 1 (clock divider, bus mode and width). */
|
||||
#define RTSX_SD_CFG1 0xFDA0
|
||||
#define RTSX_CLK_DIVIDE_0 0x00
|
||||
#define RTSX_CLK_DIVIDE_128 0x80
|
||||
#define RTSX_CLK_DIVIDE_256 0xC0
|
||||
#define RTSX_CLK_DIVIDE_MASK 0xC0
|
||||
#define RTSX_SD20_MODE 0x00
|
||||
#define RTSX_SDDDR_MODE 0x04
|
||||
#define RTSX_SD30_MODE 0x08
|
||||
#define RTSX_SD_MODE_MASK 0x0C
|
||||
#define RTSX_BUS_WIDTH_1 0x00
|
||||
#define RTSX_BUS_WIDTH_4 0x01
|
||||
#define RTSX_BUS_WIDTH_8 0x02
|
||||
#define RTSX_BUS_WIDTH_MASK 0x03
|
||||
|
||||
/* SD configuration register 2 (SD command response flags). */
|
||||
#define RTSX_SD_CFG2 0xFDA1
|
||||
#define RTSX_SD_CALCULATE_CRC7 0x00
|
||||
#define RTSX_SD_NO_CALCULATE_CRC7 0x80
|
||||
#define RTSX_SD_CHECK_CRC16 0x00
|
||||
#define RTSX_SD_NO_CHECK_CRC16 0x40
|
||||
#define RTSX_SD_NO_CHECK_WAIT_CRC_TO 0x20
|
||||
#define RTSX_SD_WAIT_BUSY_END 0x08
|
||||
#define RTSX_SD_NO_WAIT_BUSY_END 0x00
|
||||
#define RTSX_SD_CHECK_CRC7 0x00
|
||||
#define RTSX_SD_NO_CHECK_CRC7 0x04
|
||||
#define RTSX_SD_RSP_LEN_0 0x00
|
||||
#define RTSX_SD_RSP_LEN_6 0x01
|
||||
#define RTSX_SD_RSP_LEN_17 0x02
|
||||
/* SD command response types. */
|
||||
#define RTSX_SD_RSP_TYPE_R0 0x04
|
||||
#define RTSX_SD_RSP_TYPE_R1 0x01
|
||||
#define RTSX_SD_RSP_TYPE_R1B 0x09
|
||||
#define RTSX_SD_RSP_TYPE_R2 0x02
|
||||
#define RTSX_SD_RSP_TYPE_R3 0x05
|
||||
#define RTSX_SD_RSP_TYPE_R4 0x05
|
||||
#define RTSX_SD_RSP_TYPE_R5 0x01
|
||||
#define RTSX_SD_RSP_TYPE_R6 0x01
|
||||
#define RTSX_SD_RSP_TYPE_R7 0x01
|
||||
|
||||
#define RTSX_SD_STAT1 0xFDA3
|
||||
#define RTSX_SD_CRC7_ERR 0x80
|
||||
#define RTSX_SD_CRC16_ERR 0x40
|
||||
#define RTSX_SD_CRC_WRITE_ERR 0x20
|
||||
#define RTSX_SD_CRC_WRITE_ERR_MASK 0x1C
|
||||
#define RTSX_GET_CRC_TIME_OUT 0x02
|
||||
#define RTSX_SD_TUNING_COMPARE_ERR 0x01
|
||||
#define RTSX_SD_STAT2 0xFDA4
|
||||
#define RTSX_SD_RSP_80CLK_TIMEOUT 0x01
|
||||
|
||||
#define RTSX_SD_CRC_ERR (RTSX_SD_CRC7_ERR|RTSX_SD_CRC16_ERR|RTSX_SD_CRC_WRITE_ERR)
|
||||
|
||||
/* SD bus status register. */
|
||||
#define RTSX_SD_BUS_STAT 0xFDA5
|
||||
#define RTSX_SD_CLK_TOGGLE_EN 0x80
|
||||
#define RTSX_SD_CLK_FORCE_STOP 0x40
|
||||
#define RTSX_SD_DAT3_STATUS 0x10
|
||||
#define RTSX_SD_DAT2_STATUS 0x08
|
||||
#define RTSX_SD_DAT1_STATUS 0x04
|
||||
#define RTSX_SD_DAT0_STATUS 0x02
|
||||
#define RTSX_SD_CMD_STATUS 0x01
|
||||
|
||||
#define RTSX_SD_PAD_CTL 0xFDA6
|
||||
#define RTSX_SD_IO_USING_1V8 0x80
|
||||
|
||||
/* Sample point control register. */
|
||||
#define RTSX_SD_SAMPLE_POINT_CTL 0xFDA7
|
||||
#define RTSX_DDR_FIX_RX_DAT 0x00
|
||||
#define RTSX_DDR_VAR_RX_DAT 0x80
|
||||
#define RTSX_DDR_FIX_RX_DAT_EDGE 0x00
|
||||
#define RTSX_DDR_FIX_RX_DAT_14_DELAY 0x40
|
||||
#define RTSX_DDR_FIX_RX_CMD 0x00
|
||||
#define RTSX_DDR_VAR_RX_CMD 0x20
|
||||
#define RTSX_DDR_FIX_RX_CMD_POS_EDGE 0x00
|
||||
#define RTSX_DDR_FIX_RX_CMD_14_DELAY 0x10
|
||||
#define RTSX_SD20_RX_POS_EDGE 0x00
|
||||
#define RTSX_SD20_RX_14_DELAY 0x08
|
||||
#define RTSX_SD20_RX_SEL_MASK 0x08
|
||||
|
||||
#define RTSX_SD_PUSH_POINT_CTL 0xFDA8
|
||||
#define RTSX_SD20_TX_NEG_EDGE 0x00
|
||||
|
||||
#define RTSX_SD_CMD0 0xFDA9
|
||||
#define RTSX_SD_CMD1 0xFDAA
|
||||
#define RTSX_SD_CMD2 0xFDAB
|
||||
#define RTSX_SD_CMD3 0xFDAC
|
||||
#define RTSX_SD_CMD4 0xFDAD
|
||||
#define RTSX_SD_CMD5 0xFDAE
|
||||
#define RTSX_SD_BYTE_CNT_L 0xFDAF
|
||||
#define RTSX_SD_BYTE_CNT_H 0xFDB0
|
||||
#define RTSX_SD_BLOCK_CNT_L 0xFDB1
|
||||
#define RTSX_SD_BLOCK_CNT_H 0xFDB2
|
||||
|
||||
/*
|
||||
* Transfer modes.
|
||||
*/
|
||||
#define RTSX_SD_TRANSFER 0xFDB3
|
||||
|
||||
/* Write one or two bytes from SD_CMD2 and SD_CMD3 to the card. */
|
||||
#define RTSX_TM_NORMAL_WRITE 0x00
|
||||
|
||||
/* Write (SD_BYTE_CNT * SD_BLOCK_COUNTS) bytes from ring buffer to card. */
|
||||
#define RTSX_TM_AUTO_WRITE3 0x01
|
||||
|
||||
/* Like AUTO_WRITE3, plus automatically send CMD 12 when done.
|
||||
* The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */
|
||||
#define RTSX_TM_AUTO_WRITE4 0x02
|
||||
|
||||
/* Read (SD_BYTE_CNT * SD_BLOCK_CNT) bytes from card into ring buffer. */
|
||||
#define RTSX_TM_AUTO_READ3 0x05
|
||||
|
||||
/* Like AUTO_READ3, plus automatically send CMD 12 when done.
|
||||
* The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */
|
||||
#define RTSX_TM_AUTO_READ4 0x06
|
||||
|
||||
/* Send an SD command described in SD_CMD{0,1,2,3,4} to the card and put
|
||||
* the response into SD_CMD{0,1,2,3,4}. Long responses (17 byte) are put
|
||||
* into ping-pong buffer 2 instead. */
|
||||
#define RTSX_TM_CMD_RSP 0x08
|
||||
|
||||
/* Send write command, get response from the card, write data from ring
|
||||
* buffer to card, and send CMD 12 when done.
|
||||
* The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */
|
||||
#define RTSX_TM_AUTO_WRITE1 0x09
|
||||
|
||||
/* Like AUTO_WRITE1 except no CMD 12 is sent. */
|
||||
#define RTSX_TM_AUTO_WRITE2 0x0A
|
||||
|
||||
/* Send read command, read up to 512 bytes (SD_BYTE_CNT * SD_BLOCK_CNT)
|
||||
* from the card into the ring buffer or ping-pong buffer 2. */
|
||||
#define RTSX_TM_NORMAL_READ 0x0C
|
||||
|
||||
/* Same as WRITE1, except data is read from the card to the ring buffer. */
|
||||
#define RTSX_TM_AUTO_READ1 0x0D
|
||||
|
||||
/* Same as WRITE2, except data is read from the card to the ring buffer. */
|
||||
#define RTSX_TM_AUTO_READ2 0x0E
|
||||
|
||||
/* Send CMD 19 and receive response and tuning pattern from card and
|
||||
* report the result. */
|
||||
#define RTSX_TM_AUTO_TUNING 0x0F
|
||||
|
||||
/* transfer control */
|
||||
#define RTSX_SD_TRANSFER_START 0x80
|
||||
#define RTSX_SD_TRANSFER_END 0x40
|
||||
#define RTSX_SD_STAT_IDLE 0x20
|
||||
#define RTSX_SD_TRANSFER_ERR 0x10
|
||||
|
||||
#define RTSX_SD_CMD_STATE 0xFDB5
|
||||
#define RTSX_CMD_IDLE 0x80
|
||||
#define RTSX_SD_DATA_STATE 0xFDB6
|
||||
#define RTSX_DATA_IDLE 0x80
|
||||
|
||||
#define RTSX_CARD_STOP 0xFD54
|
||||
#define RTSX_SPI_STOP 0x01
|
||||
#define RTSX_XD_STOP 0x02
|
||||
#define RTSX_SD_STOP 0x04
|
||||
#define RTSX_MS_STOP 0x08
|
||||
#define RTSX_SPI_CLR_ERR 0x10
|
||||
#define RTSX_XD_CLR_ERR 0x20
|
||||
#define RTSX_SD_CLR_ERR 0x40
|
||||
#define RTSX_MS_CLR_ERR 0x80
|
||||
#define RTSX_ALL_STOP 0x0F
|
||||
#define RTSX_ALL_CLR_ERR 0xF0
|
||||
|
||||
#define RTSX_CARD_OE 0xFD55
|
||||
#define RTSX_XD_OUTPUT_EN 0x02
|
||||
#define RTSX_SD_OUTPUT_EN 0x04
|
||||
#define RTSX_MS_OUTPUT_EN 0x08
|
||||
#define RTSX_SPI_OUTPUT_EN 0x10
|
||||
#define RTSX_CARD_OUTPUT_EN (RTSX_XD_OUTPUT_EN|RTSX_SD_OUTPUT_EN|\
|
||||
RTSX_MS_OUTPUT_EN)
|
||||
|
||||
#define RTSX_CARD_DATA_SOURCE 0xFD5B
|
||||
#define RTSX_RING_BUFFER 0x00
|
||||
#define RTSX_PINGPONG_BUFFER 0x01
|
||||
#define RTSX_CARD_SELECT 0xFD5C
|
||||
#define RTSX_XD_MOD_SEL 0x01
|
||||
#define RTSX_SD_MOD_SEL 0x02
|
||||
#define RTSX_MS_MOD_SEL 0x03
|
||||
#define RTSX_SPI_MOD_SEL 0x04
|
||||
|
||||
#define RTSX_CARD_GPIO_DIR 0xFD57
|
||||
#define RTSX_CARD_GPIO 0xFD58
|
||||
#define RTSX_CARD_GPIO_LED_OFF 0x01
|
||||
|
||||
/* ping-pong buffer 2 */
|
||||
#define RTSX_PPBUF_BASE2 0xFA00
|
||||
#define RTSX_PPBUF_SIZE 256
|
||||
|
||||
#define RTSX_SUPPORT_VOLTAGE (MMC_OCR_3_3V_3_4V \
|
||||
| MMC_OCR_3_2V_3_3V \
|
||||
| MMC_OCR_3_1V_3_2V \
|
||||
| MMC_OCR_3_0V_3_1V)
|
||||
|
||||
#define RTSX_CFG_PCI 0x1C
|
||||
#define RTSX_CFG_ASIC 0x10
|
||||
|
||||
#define RTSX_IRQEN0 0xFE20
|
||||
#define RTSX_LINK_DOWN_INT_EN 0x10
|
||||
#define RTSX_LINK_READY_INT_EN 0x20
|
||||
#define RTSX_SUSPEND_INT_EN 0x40
|
||||
#define RTSX_DMA_DONE_INT_EN 0x80
|
||||
#define RTSX_IRQSTAT0 0xFE21
|
||||
#define RTSX_LINK_DOWN_INT 0x10
|
||||
#define RTSX_LINK_READY_INT 0x20
|
||||
#define RTSX_SUSPEND_INT 0x40
|
||||
#define RTSX_DMA_DONE_INT 0x80
|
||||
|
||||
#define RTSX_DMATC0 0xFE28
|
||||
#define RTSX_DMATC1 0xFE29
|
||||
#define RTSX_DMATC2 0xFE2A
|
||||
#define RTSX_DMATC3 0xFE2B
|
||||
|
||||
#define RTSX_DMACTL 0xFE2C
|
||||
#define RTSX_DMA_EN 0x01
|
||||
#define RTSX_DMA_DIR 0x02
|
||||
#define RTSX_DMA_DIR_TO_CARD 0x00
|
||||
#define RTSX_DMA_DIR_FROM_CARD 0x02
|
||||
#define RTSX_DMA_BUSY 0x04
|
||||
#define RTSX_DMA_RST 0x80
|
||||
#define RTSX_DMA_128 (0 << 4)
|
||||
#define RTSX_DMA_256 (1 << 4)
|
||||
#define RTSX_DMA_512 (2 << 4)
|
||||
#define RTSX_DMA_1024 (3 << 4)
|
||||
#define RTSX_DMA_PACK_SIZE_MASK 0x30
|
||||
|
||||
#define RTSX_RBCTL 0xFE34
|
||||
#define RTSX_RB_FLUSH 0x80
|
||||
|
||||
#define RTSX_CFGADDR0 0xFE35
|
||||
#define RTSX_CFGADDR1 0xFE36
|
||||
#define RTSX_CFGDATA0 0xFE37
|
||||
#define RTSX_CFGDATA1 0xFE38
|
||||
#define RTSX_CFGDATA2 0xFE39
|
||||
#define RTSX_CFGDATA3 0xFE3A
|
||||
#define RTSX_CFGRWCTL 0xFE3B
|
||||
#define RTSX_CFG_WRITE_DATA0 0x01
|
||||
#define RTSX_CFG_WRITE_DATA1 0x02
|
||||
#define RTSX_CFG_WRITE_DATA2 0x04
|
||||
#define RTSX_CFG_WRITE_DATA3 0x08
|
||||
#define RTSX_CFG_BUSY 0x80
|
||||
|
||||
#define RTSX_SDIOCFG_REG 0x724
|
||||
#define RTSX_SDIOCFG_NO_BYPASS_SDIO 0x02
|
||||
#define RTSX_SDIOCFG_HAVE_SDIO 0x04
|
||||
#define RTSX_SDIOCFG_SINGLE_LUN 0x08
|
||||
#define RTSX_SDIOCFG_SDIO_ONLY 0x80
|
||||
|
||||
#define RTSX_HOST_SLEEP_STATE 0xFE60
|
||||
#define RTSX_HOST_ENTER_S1 0x01
|
||||
#define RTSX_HOST_ENTER_S3 0x02
|
||||
|
||||
#define RTSX_SDIO_CFG 0xFE70
|
||||
#define RTSX_SDIO_BUS_AUTO_SWITCH 0x10
|
||||
|
||||
#define RTSX_NFTS_TX_CTRL 0xFE72
|
||||
#define RTSX_INT_READ_CLR 0x02
|
||||
|
||||
#define RTSX_PWR_GATE_CTRL 0xFE75
|
||||
#define RTSX_PWR_GATE_EN 0x01
|
||||
#define RTSX_LDO3318_ON 0x00
|
||||
#define RTSX_LDO3318_SUSPEND 0x04
|
||||
#define RTSX_LDO3318_OFF 0x06
|
||||
#define RTSX_LDO3318_VCC1 0x02
|
||||
#define RTSX_LDO3318_VCC2 0x04
|
||||
#define RTSX_PWD_SUSPEND_EN 0xFE76
|
||||
#define RTSX_LDO_PWR_SEL 0xFE78
|
||||
#define RTSX_LDO_PWR_SEL_3V3 0x01
|
||||
#define RTSX_LDO_PWR_SEL_DV33 0x03
|
||||
|
||||
#define RTSX_PHY_RWCTL 0xFE3C
|
||||
#define RTSX_PHY_READ 0x00
|
||||
#define RTSX_PHY_WRITE 0x01
|
||||
#define RTSX_PHY_BUSY 0x80
|
||||
#define RTSX_PHY_DATA0 0xFE3D
|
||||
#define RTSX_PHY_DATA1 0xFE3E
|
||||
#define RTSX_PHY_ADDR 0xFE3F
|
||||
|
||||
#define RTSX_PHY_VOLTAGE 0x08
|
||||
#define RTSX_PHY_VOLTAGE_MASK 0x3F
|
||||
|
||||
#define RTSX_PETXCFG 0xFE49
|
||||
#define RTSX_PETXCFG_CLKREQ_PIN 0x08
|
||||
|
||||
#define RTSX_CARD_AUTO_BLINK 0xFD56
|
||||
#define RTSX_LED_BLINK_EN 0x08
|
||||
#define RTSX_LED_BLINK_SPEED 0x05
|
||||
|
||||
#define RTSX_WAKE_SEL_CTL 0xFE54
|
||||
#define RTSX_PME_FORCE_CTL 0xFE56
|
||||
|
||||
#define RTSX_CHANGE_LINK_STATE 0xFE5B
|
||||
#define RTSX_CD_RST_CORE_EN 0x01
|
||||
#define RTSX_FORCE_RST_CORE_EN 0x02
|
||||
#define RTSX_NON_STICKY_RST_N_DBG 0x08
|
||||
#define RTSX_MAC_PHY_RST_N_DBG 0x10
|
||||
|
||||
#define RTSX_PERST_GLITCH_WIDTH 0xFE5C
|
||||
|
||||
#define RTSX_SD30_DRIVE_SEL 0xFE5E
|
||||
#define RTSX_SD30_DRIVE_SEL_3V3 0x01
|
||||
#define RTSX_SD30_DRIVE_SEL_1V8 0x03
|
||||
#define RTSX_SD30_DRIVE_SEL_MASK 0x07
|
||||
|
||||
#define RTSX_DUMMY_REG 0xFE90
|
||||
|
||||
#define RTSX_SG_INT 0x04
|
||||
#define RTSX_SG_END 0x02
|
||||
#define RTSX_SG_VALID 0x01
|
||||
|
||||
#define RTSX_SG_NO_OP 0x00
|
||||
#define RTSX_SG_TRANS_DATA (0x02 << 4)
|
||||
#define RTSX_SG_LINK_DESC (0x03 << 4)
|
||||
|
||||
#define RTSX_IC_VERSION_A 0x00
|
||||
#define RTSX_IC_VERSION_B 0x01
|
||||
#define RTSX_IC_VERSION_C 0x02
|
||||
#define RTSX_IC_VERSION_D 0x03
|
||||
|
||||
#endif /* _RTSXREG_H_ */
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/* $NetBSD: rtsxvar.h,v 1.1 2014/03/19 15:26:41 nonaka Exp $ */
|
||||
/* $OpenBSD: rtsxvar.h,v 1.2 2013/11/06 13:51:02 stsp Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
|
||||
* Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _RTSXVAR_H_
|
||||
#define _RTSXVAR_H_
|
||||
|
||||
#include <sys/bus.h>
|
||||
#include <sys/device.h>
|
||||
#include <sys/pmf.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/condvar.h>
|
||||
|
||||
/* Number of registers to save for suspend/resume in terms of their ranges. */
|
||||
#define RTSX_NREG ((0XFDAE - 0XFDA0) + (0xFD69 - 0xFD32) + (0xFE34 - 0xFE20))
|
||||
|
||||
struct rtsx_softc {
|
||||
device_t sc_dev;
|
||||
|
||||
device_t sc_sdmmc; /* generic SD/MMC device */
|
||||
|
||||
bus_space_tag_t sc_iot; /* host register set tag */
|
||||
bus_space_handle_t sc_ioh; /* host register set handle */
|
||||
bus_size_t sc_iosize;
|
||||
bus_dma_tag_t sc_dmat; /* DMA tag from attachment driver */
|
||||
bus_dmamap_t sc_dmap_cmd; /* DMA map for command transfer */
|
||||
|
||||
struct kmutex sc_host_mtx;
|
||||
struct kmutex sc_intr_mtx;
|
||||
struct kcondvar sc_intr_cv;
|
||||
|
||||
uint32_t sc_intr_status; /* soft interrupt status */
|
||||
|
||||
uint8_t sc_regs[RTSX_NREG]; /* host controller state */
|
||||
uint32_t sc_regs4[6]; /* host controller state */
|
||||
|
||||
uint32_t sc_flags;
|
||||
#define RTSX_F_CARD_PRESENT __BIT(0)
|
||||
#define RTSX_F_SDIO_SUPPORT __BIT(1)
|
||||
#define RTSX_F_5209 __BIT(2)
|
||||
#define RTSX_F_5229 __BIT(3)
|
||||
#define RTSX_F_5229_TYPE_C __BIT(4)
|
||||
};
|
||||
|
||||
/* Host controller functions called by the attachment driver. */
|
||||
int rtsx_attach(struct rtsx_softc *, bus_space_tag_t,
|
||||
bus_space_handle_t, bus_size_t, bus_dma_tag_t, int);
|
||||
int rtsx_detach(struct rtsx_softc *, int);
|
||||
bool rtsx_suspend(device_t, const pmf_qual_t *);
|
||||
bool rtsx_resume(device_t, const pmf_qual_t *);
|
||||
bool rtsx_shutdown(device_t, int);
|
||||
int rtsx_intr(void *);
|
||||
|
||||
#endif /* _RTSXVAR_H_ */
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: files.pci,v 1.370 2014/03/18 18:20:41 riastradh Exp $
|
||||
# $NetBSD: files.pci,v 1.371 2014/03/19 15:26:41 nonaka Exp $
|
||||
#
|
||||
# Config file and device description for machine-independent PCI code.
|
||||
# Included by ports that need it. Requires that the SCSI files be
|
||||
|
|
@ -977,7 +977,7 @@ attach msk at mskc
|
|||
file dev/pci/if_msk.c mskc | msk
|
||||
|
||||
# SD Host Controller
|
||||
attach sdhc at pci with sdhc_pci
|
||||
attach sdhc at pci with sdhc_pci
|
||||
file dev/pci/sdhc_pci.c sdhc_pci
|
||||
|
||||
# generic framebuffer console driver, PCI frontend
|
||||
|
|
@ -1148,5 +1148,9 @@ attach gffb at pci
|
|||
file dev/pci/gffb.c gffb
|
||||
defflag opt_gffb.h GFFB_DEBUG
|
||||
|
||||
# Realtek RTS5209/RTS5229 Card Reader driver
|
||||
attach rtsx at pci with rtsx_pci
|
||||
file dev/pci/rtsx_pci.c rtsx_pci
|
||||
|
||||
# PCI graphics devices with DRM/KMS
|
||||
include "external/bsd/drm2/pci/files.drmkms_pci"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,165 @@
|
|||
/* $NetBSD: rtsx_pci.c,v 1.1 2014/03/19 15:26:41 nonaka Exp $ */
|
||||
/* $OpenBSD: rtsx_pci.c,v 1.4 2013/11/06 13:51:02 stsp Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
|
||||
* Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: rtsx_pci.c,v 1.1 2014/03/19 15:26:41 nonaka Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/device.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/pmf.h>
|
||||
|
||||
#include <dev/pci/pcivar.h>
|
||||
#include <dev/pci/pcidevs.h>
|
||||
|
||||
#include <dev/ic/rtsxreg.h>
|
||||
#include <dev/ic/rtsxvar.h>
|
||||
|
||||
#include <dev/sdmmc/sdmmcvar.h>
|
||||
|
||||
#define RTSX_PCI_BAR 0x10
|
||||
|
||||
struct rtsx_pci_softc {
|
||||
struct rtsx_softc sc;
|
||||
pci_chipset_tag_t sc_pc;
|
||||
void *sc_ih;
|
||||
};
|
||||
|
||||
static int rtsx_pci_match(device_t , cfdata_t, void *);
|
||||
static void rtsx_pci_attach(device_t, device_t, void *);
|
||||
static int rtsx_pci_detach(device_t, int);
|
||||
|
||||
CFATTACH_DECL_NEW(rtsx_pci, sizeof(struct rtsx_pci_softc),
|
||||
rtsx_pci_match, rtsx_pci_attach, rtsx_pci_detach, NULL);
|
||||
|
||||
#ifdef RTSX_DEBUG
|
||||
extern int rtsxdebug;
|
||||
#define DPRINTF(n,s) do { if ((n) <= rtsxdebug) printf s; } while (0)
|
||||
#else
|
||||
#define DPRINTF(n,s) /**/
|
||||
#endif
|
||||
|
||||
static int
|
||||
rtsx_pci_match(device_t parent, cfdata_t cf, void *aux)
|
||||
{
|
||||
struct pci_attach_args *pa = aux;
|
||||
|
||||
/*
|
||||
* Explicitly match the UNDEFINED device class only. Some RTS5902
|
||||
* devices advertise a SYSTEM/SDHC class in addition to the UNDEFINED
|
||||
* device class. Let sdhc(4) handle the SYSTEM/SDHC ones.
|
||||
*/
|
||||
if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_REALTEK ||
|
||||
PCI_CLASS(pa->pa_class) != PCI_CLASS_UNDEFINED)
|
||||
return 0;
|
||||
|
||||
if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RTS5209 ||
|
||||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RTS5229)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
rtsx_pci_attach(device_t parent, device_t self, void *aux)
|
||||
{
|
||||
struct rtsx_pci_softc *sc = device_private(self);
|
||||
struct pci_attach_args *pa = (struct pci_attach_args *)aux;
|
||||
pci_chipset_tag_t pc = pa->pa_pc;
|
||||
pcitag_t tag = pa->pa_tag;
|
||||
pci_intr_handle_t ih;
|
||||
pcireg_t reg;
|
||||
char const *intrstr;
|
||||
bus_space_tag_t iot;
|
||||
bus_space_handle_t ioh;
|
||||
bus_size_t size;
|
||||
uint32_t flags;
|
||||
|
||||
sc->sc.sc_dev = self;
|
||||
sc->sc_pc = pc;
|
||||
|
||||
pci_aprint_devinfo(pa, NULL);
|
||||
|
||||
if ((pci_conf_read(pc, tag, RTSX_CFG_PCI) & RTSX_CFG_ASIC) != 0) {
|
||||
aprint_error_dev(self, "no asic\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (pci_mapreg_map(pa, RTSX_PCI_BAR, PCI_MAPREG_TYPE_MEM, 0,
|
||||
&iot, &ioh, NULL, &size)) {
|
||||
aprint_error_dev(self, "couldn't map registers\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (pci_intr_map(pa, &ih)) {
|
||||
aprint_error_dev(self, "couldn't map interrupt\n");
|
||||
return;
|
||||
}
|
||||
intrstr = pci_intr_string(pc, ih);
|
||||
sc->sc_ih = pci_intr_establish(pc, ih, IPL_SDMMC, rtsx_intr, &sc->sc);
|
||||
if (sc->sc_ih == NULL) {
|
||||
aprint_error_dev(self, "couldn't establish interrupt\n");
|
||||
return;
|
||||
}
|
||||
aprint_normal_dev(self, "interrupting at %s\n", intrstr);
|
||||
|
||||
/* Enable the device */
|
||||
reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
|
||||
reg |= PCI_COMMAND_MASTER_ENABLE;
|
||||
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
|
||||
|
||||
/* Power up the device */
|
||||
pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0);
|
||||
|
||||
switch (PCI_PRODUCT(pa->pa_id)) {
|
||||
case PCI_PRODUCT_REALTEK_RTS5209:
|
||||
flags = RTSX_F_5209;
|
||||
break;
|
||||
case PCI_PRODUCT_REALTEK_RTS5229:
|
||||
default:
|
||||
flags = RTSX_F_5229;
|
||||
break;
|
||||
}
|
||||
|
||||
if (rtsx_attach(&sc->sc, iot, ioh, size, pa->pa_dmat, flags) != 0) {
|
||||
aprint_error_dev(self, "couldn't initialize chip\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!pmf_device_register1(self, rtsx_suspend, rtsx_resume,
|
||||
rtsx_shutdown))
|
||||
aprint_error_dev(self, "couldn't establish powerhook\n");
|
||||
}
|
||||
|
||||
static int
|
||||
rtsx_pci_detach(device_t self, int flags)
|
||||
{
|
||||
struct rtsx_pci_softc *sc = device_private(self);
|
||||
int rv;
|
||||
|
||||
rv = rtsx_detach(&sc->sc, flags);
|
||||
if (rv)
|
||||
return rv;
|
||||
|
||||
pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: sdmmc.c,v 1.21 2013/10/12 16:49:01 christos Exp $ */
|
||||
/* $NetBSD: sdmmc.c,v 1.22 2014/03/19 15:26:42 nonaka Exp $ */
|
||||
/* $OpenBSD: sdmmc.c,v 1.18 2009/01/09 10:58:38 jsg Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -49,7 +49,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: sdmmc.c,v 1.21 2013/10/12 16:49:01 christos Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: sdmmc.c,v 1.22 2014/03/19 15:26:42 nonaka Exp $");
|
||||
|
||||
#ifdef _KERNEL_OPT
|
||||
#include "opt_sdmmc.h"
|
||||
|
|
@ -72,7 +72,7 @@ __KERNEL_RCSID(0, "$NetBSD: sdmmc.c,v 1.21 2013/10/12 16:49:01 christos Exp $");
|
|||
#include <dev/sdmmc/sdmmcvar.h>
|
||||
|
||||
#ifdef SDMMC_DEBUG
|
||||
int sdmmcdebug = 1;
|
||||
int sdmmcdebug = 0;
|
||||
static void sdmmc_dump_command(struct sdmmc_softc *, struct sdmmc_command *);
|
||||
#define DPRINTF(n,s) do { if ((n) <= sdmmcdebug) printf s; } while (0)
|
||||
#else
|
||||
|
|
@ -141,12 +141,6 @@ sdmmc_attach(device_t parent, device_t self, void *aux)
|
|||
}
|
||||
}
|
||||
|
||||
if (ISSET(sc->sc_caps, SMC_CAPS_POLL_CARD_DET)) {
|
||||
callout_init(&sc->sc_card_detect_ch, 0);
|
||||
callout_reset(&sc->sc_card_detect_ch, hz,
|
||||
sdmmc_polling_card, sc);
|
||||
}
|
||||
|
||||
SIMPLEQ_INIT(&sc->sf_head);
|
||||
TAILQ_INIT(&sc->sc_tskq);
|
||||
TAILQ_INIT(&sc->sc_intrq);
|
||||
|
|
@ -160,6 +154,12 @@ sdmmc_attach(device_t parent, device_t self, void *aux)
|
|||
mutex_init(&sc->sc_intr_task_mtx, MUTEX_DEFAULT, IPL_SDMMC);
|
||||
cv_init(&sc->sc_tskq_cv, "mmctaskq");
|
||||
|
||||
if (ISSET(sc->sc_caps, SMC_CAPS_POLL_CARD_DET)) {
|
||||
callout_init(&sc->sc_card_detect_ch, 0);
|
||||
callout_reset(&sc->sc_card_detect_ch, hz,
|
||||
sdmmc_polling_card, sc);
|
||||
}
|
||||
|
||||
if (!pmf_device_register(self, NULL, NULL)) {
|
||||
aprint_error_dev(self, "couldn't establish power handler\n");
|
||||
}
|
||||
|
|
@ -198,6 +198,17 @@ sdmmc_detach(device_t self, int flags)
|
|||
bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmap);
|
||||
}
|
||||
|
||||
if (ISSET(sc->sc_caps, SMC_CAPS_POLL_CARD_DET)) {
|
||||
callout_stop(&sc->sc_card_detect_ch);
|
||||
callout_destroy(&sc->sc_card_detect_ch);
|
||||
}
|
||||
|
||||
cv_destroy(&sc->sc_tskq_cv);
|
||||
mutex_destroy(&sc->sc_intr_task_mtx);
|
||||
mutex_destroy(&sc->sc_discover_task_mtx);
|
||||
mutex_destroy(&sc->sc_tskq_mtx);
|
||||
mutex_destroy(&sc->sc_mtx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -745,13 +756,8 @@ sdmmc_app_command(struct sdmmc_softc *sc, struct sdmmc_function *sf, struct sdmm
|
|||
|
||||
memset(&acmd, 0, sizeof(acmd));
|
||||
acmd.c_opcode = MMC_APP_CMD;
|
||||
if (sf != NULL) {
|
||||
acmd.c_arg = sf->rca << 16;
|
||||
acmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1;
|
||||
} else {
|
||||
acmd.c_arg = 0;
|
||||
acmd.c_flags = SCF_CMD_BCR | SCF_RSP_R1 | SCF_RSP_SPI_R1;
|
||||
}
|
||||
acmd.c_arg = (sf != NULL) ? (sf->rca << 16) : 0;
|
||||
acmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1;
|
||||
|
||||
error = sdmmc_mmc_command(sc, &acmd);
|
||||
if (error == 0) {
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: sdmmc_mem.c,v 1.30 2013/10/25 11:35:55 martin Exp $ */
|
||||
/* $NetBSD: sdmmc_mem.c,v 1.31 2014/03/19 15:26:42 nonaka Exp $ */
|
||||
/* $OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -45,7 +45,7 @@
|
|||
/* Routines for SD/MMC memory cards. */
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.30 2013/10/25 11:35:55 martin Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.31 2014/03/19 15:26:42 nonaka Exp $");
|
||||
|
||||
#ifdef _KERNEL_OPT
|
||||
#include "opt_sdmmc.h"
|
||||
|
|
@ -75,7 +75,7 @@ static int sdmmc_mem_send_cid(struct sdmmc_softc *, sdmmc_response *);
|
|||
static int sdmmc_mem_send_csd(struct sdmmc_softc *, struct sdmmc_function *,
|
||||
sdmmc_response *);
|
||||
static int sdmmc_mem_send_scr(struct sdmmc_softc *, struct sdmmc_function *,
|
||||
uint32_t scr[2]);
|
||||
uint32_t *scr);
|
||||
static int sdmmc_mem_decode_scr(struct sdmmc_softc *, struct sdmmc_function *);
|
||||
static int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t);
|
||||
static int sdmmc_set_bus_width(struct sdmmc_function *, int);
|
||||
|
|
@ -114,10 +114,12 @@ sdmmc_mem_enable(struct sdmmc_softc *sc)
|
|||
/* Reset memory (*must* do that before CMD55 or CMD1). */
|
||||
sdmmc_go_idle_state(sc);
|
||||
|
||||
/* Check SD Ver.2 */
|
||||
error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr);
|
||||
if (error == 0 && card_ocr == 0x1aa)
|
||||
SET(ocr, MMC_OCR_HCS);
|
||||
if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
|
||||
/* Check SD Ver.2 */
|
||||
error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr);
|
||||
if (error == 0 && card_ocr == 0x1aa)
|
||||
SET(ocr, MMC_OCR_HCS);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read the SD/MMC memory OCR value by issuing CMD55 followed
|
||||
|
|
@ -127,7 +129,7 @@ sdmmc_mem_enable(struct sdmmc_softc *sc)
|
|||
*/
|
||||
mmc_mode:
|
||||
error = sdmmc_mem_send_op_cond(sc,
|
||||
ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr);
|
||||
ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr);
|
||||
if (error) {
|
||||
if (ISSET(sc->sc_flags, SMF_SD_MODE) &&
|
||||
!ISSET(sc->sc_flags, SMF_IO_MODE)) {
|
||||
|
|
@ -165,7 +167,17 @@ mmc_mode:
|
|||
SDMMCDEVNAME(sc)));
|
||||
goto out;
|
||||
}
|
||||
host_ocr &= card_ocr;
|
||||
|
||||
/* Tell the card(s) to enter the idle state (again). */
|
||||
sdmmc_go_idle_state(sc);
|
||||
|
||||
host_ocr &= card_ocr; /* only allow the common voltages */
|
||||
if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
|
||||
/* Check SD Ver.2 */
|
||||
error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr);
|
||||
if (error == 0 && card_ocr == 0x1aa)
|
||||
SET(ocr, MMC_OCR_HCS);
|
||||
}
|
||||
host_ocr |= ocr;
|
||||
|
||||
/* Send the new OCR value until all cards are ready. */
|
||||
|
|
@ -454,11 +466,9 @@ sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf)
|
|||
goto out;
|
||||
}
|
||||
|
||||
if (!ISSET(sf->flags, SFF_SDHC)) {
|
||||
error = sdmmc_mem_set_blocklen(sc, sf);
|
||||
if (error)
|
||||
goto out;
|
||||
}
|
||||
error = sdmmc_mem_set_blocklen(sc, sf, SDMMC_SECTOR_SIZE);
|
||||
if (error)
|
||||
goto out;
|
||||
|
||||
if (ISSET(sc->sc_flags, SMF_SD_MODE))
|
||||
error = sdmmc_mem_sd_init(sc, sf);
|
||||
|
|
@ -556,7 +566,8 @@ sdmmc_mem_send_if_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp)
|
|||
* the card CSD register value.
|
||||
*/
|
||||
int
|
||||
sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf)
|
||||
sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf,
|
||||
int block_len)
|
||||
{
|
||||
struct sdmmc_command cmd;
|
||||
int error;
|
||||
|
|
@ -565,13 +576,13 @@ sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf)
|
|||
|
||||
memset(&cmd, 0, sizeof(cmd));
|
||||
cmd.c_opcode = MMC_SET_BLOCKLEN;
|
||||
cmd.c_arg = SDMMC_SECTOR_SIZE;
|
||||
cmd.c_arg = block_len;
|
||||
cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1;
|
||||
|
||||
error = sdmmc_mmc_command(sc, &cmd);
|
||||
|
||||
DPRINTF(("%s: sdmmc_mem_set_blocklen: read_bl_len=%d sector_size=%d\n",
|
||||
SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, SDMMC_SECTOR_SIZE));
|
||||
SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, block_len));
|
||||
|
||||
return error;
|
||||
}
|
||||
|
|
@ -614,9 +625,17 @@ sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf)
|
|||
/* DDR50 */
|
||||
{ MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 50000 },
|
||||
};
|
||||
int host_ocr, support_func, best_func, error, g, i;
|
||||
int host_ocr, support_func, best_func, bus_clock, error, g, i;
|
||||
sdmmc_bitfield512_t status; /* Switch Function Status */
|
||||
|
||||
/* change bus clock */
|
||||
bus_clock = min(sc->sc_busclk, sf->csd.tran_speed);
|
||||
error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock);
|
||||
if (error) {
|
||||
aprint_error_dev(sc->sc_dev, "can't change bus clock\n");
|
||||
return error;
|
||||
}
|
||||
|
||||
error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr);
|
||||
if (error) {
|
||||
aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n");
|
||||
|
|
@ -679,9 +698,13 @@ sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf)
|
|||
}
|
||||
}
|
||||
|
||||
/* change bus clock */
|
||||
/* update bus clock */
|
||||
if (sc->sc_busclk > sf->csd.tran_speed)
|
||||
sc->sc_busclk = sf->csd.tran_speed;
|
||||
if (sc->sc_busclk == bus_clock)
|
||||
return 0;
|
||||
|
||||
/* change bus clock */
|
||||
error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk);
|
||||
if (error) {
|
||||
aprint_error_dev(sc->sc_dev, "can't change bus clock\n");
|
||||
|
|
@ -694,14 +717,23 @@ sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf)
|
|||
static int
|
||||
sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf)
|
||||
{
|
||||
int width, value, hs_timing, error;
|
||||
int width, value, hs_timing, bus_clock, error;
|
||||
char ext_csd[512];
|
||||
|
||||
/* change bus clock */
|
||||
bus_clock = min(sc->sc_busclk, sf->csd.tran_speed);
|
||||
error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock);
|
||||
if (error) {
|
||||
aprint_error_dev(sc->sc_dev, "can't change bus clock\n");
|
||||
return error;
|
||||
}
|
||||
|
||||
if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) {
|
||||
error = sdmmc_mem_send_cxd_data(sc,
|
||||
MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd));
|
||||
if (error) {
|
||||
aprint_error_dev(sc->sc_dev, "can't read EXT_CSD\n");
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"can't read EXT_CSD (error=%d)\n", error);
|
||||
return error;
|
||||
}
|
||||
if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) &&
|
||||
|
|
@ -747,12 +779,14 @@ sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf)
|
|||
|
||||
if (sc->sc_busclk > sf->csd.tran_speed)
|
||||
sc->sc_busclk = sf->csd.tran_speed;
|
||||
error =
|
||||
sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk);
|
||||
if (error) {
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"can't change bus clock\n");
|
||||
return error;
|
||||
if (sc->sc_busclk != bus_clock) {
|
||||
error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch,
|
||||
sc->sc_busclk);
|
||||
if (error) {
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"can't change bus clock\n");
|
||||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
if (hs_timing) {
|
||||
|
|
@ -799,12 +833,14 @@ sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf)
|
|||
} else {
|
||||
if (sc->sc_busclk > sf->csd.tran_speed)
|
||||
sc->sc_busclk = sf->csd.tran_speed;
|
||||
error =
|
||||
sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk);
|
||||
if (error) {
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"can't change bus clock\n");
|
||||
return error;
|
||||
if (sc->sc_busclk != bus_clock) {
|
||||
error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch,
|
||||
sc->sc_busclk);
|
||||
if (error) {
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"can't change bus clock\n");
|
||||
return error;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -829,7 +865,8 @@ sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp)
|
|||
}
|
||||
|
||||
#ifdef SDMMC_DEBUG
|
||||
sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp));
|
||||
if (error == 0)
|
||||
sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp));
|
||||
#endif
|
||||
if (error == 0 && resp != NULL)
|
||||
memcpy(resp, &cmd.c_resp, sizeof(*resp));
|
||||
|
|
@ -856,7 +893,8 @@ sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf,
|
|||
}
|
||||
|
||||
#ifdef SDMMC_DEBUG
|
||||
sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp));
|
||||
if (error == 0)
|
||||
sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp));
|
||||
#endif
|
||||
if (error == 0 && resp != NULL)
|
||||
memcpy(resp, &cmd.c_resp, sizeof(*resp));
|
||||
|
|
@ -865,7 +903,7 @@ sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf,
|
|||
|
||||
static int
|
||||
sdmmc_mem_send_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf,
|
||||
uint32_t scr[2])
|
||||
uint32_t *scr)
|
||||
{
|
||||
struct sdmmc_command cmd;
|
||||
bus_dma_segment_t ds[1];
|
||||
|
|
@ -934,7 +972,7 @@ dmamem_free:
|
|||
|
||||
#ifdef SDMMC_DEBUG
|
||||
if (error == 0)
|
||||
sdmmc_dump_data("SCR", scr, 8);
|
||||
sdmmc_dump_data("SCR", scr, datalen);
|
||||
#endif
|
||||
return error;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: sdmmcvar.h,v 1.14 2012/07/12 15:59:32 jakllsch Exp $ */
|
||||
/* $NetBSD: sdmmcvar.h,v 1.15 2014/03/19 15:26:42 nonaka Exp $ */
|
||||
/* $OpenBSD: sdmmcvar.h,v 1.13 2009/01/09 10:55:22 jsg Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -125,6 +125,7 @@ struct sdmmc_command {
|
|||
#define SCF_RSP_R5B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY)
|
||||
#define SCF_RSP_R6 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
|
||||
#define SCF_RSP_R7 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
|
||||
#define SCF_RSP_MASK (0x1f << 1)
|
||||
/* SPI */
|
||||
#define SCF_RSP_SPI_R1 (SCF_RSP_SPI_S1)
|
||||
#define SCF_RSP_SPI_R1B (SCF_RSP_SPI_S1|SCF_RSP_SPI_BSY)
|
||||
|
|
@ -133,6 +134,7 @@ struct sdmmc_command {
|
|||
#define SCF_RSP_SPI_R4 (SCF_RSP_SPI_S1|SCF_RSP_SPI_B4)
|
||||
#define SCF_RSP_SPI_R5 (SCF_RSP_SPI_S1|SCF_RSP_SPI_S2)
|
||||
#define SCF_RSP_SPI_R7 (SCF_RSP_SPI_S1|SCF_RSP_SPI_B4)
|
||||
#define SCF_RSP_SPI_MASK (0xf << 10)
|
||||
int c_error; /* errno value on completion */
|
||||
|
||||
/* Host controller owned fields for data xfer in progress */
|
||||
|
|
@ -338,7 +340,8 @@ void sdmmc_mem_scan(struct sdmmc_softc *);
|
|||
int sdmmc_mem_init(struct sdmmc_softc *, struct sdmmc_function *);
|
||||
int sdmmc_mem_send_op_cond(struct sdmmc_softc *, uint32_t, uint32_t *);
|
||||
int sdmmc_mem_send_if_cond(struct sdmmc_softc *, uint32_t, uint32_t *);
|
||||
int sdmmc_mem_set_blocklen(struct sdmmc_softc *, struct sdmmc_function *);
|
||||
int sdmmc_mem_set_blocklen(struct sdmmc_softc *, struct sdmmc_function *,
|
||||
int);
|
||||
int sdmmc_mem_read_block(struct sdmmc_function *, uint32_t, u_char *,
|
||||
size_t);
|
||||
int sdmmc_mem_write_block(struct sdmmc_function *, uint32_t, u_char *,
|
||||
|
|
|
|||
Loading…
Reference in New Issue