Many fixes. Multicast hash filter works now. Autonegotiation with GigE
on Mac G4's now works. XXX Checksum offload still needs to be done.
This commit is contained in:
matt
parent
d2a97e2196
commit
c1fc5d35dc
186
sys/dev/ic/gem.c
186
sys/dev/ic/gem.c
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@ -1,4 +1,4 @@
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/* $NetBSD: gem.c,v 1.14 2002/05/08 02:12:55 matt Exp $ */
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/* $NetBSD: gem.c,v 1.15 2002/05/11 00:36:02 matt Exp $ */
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/*
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*
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@ -34,7 +34,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.14 2002/05/08 02:12:55 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.15 2002/05/11 00:36:02 matt Exp $");
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#include "bpfilter.h"
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@ -132,7 +132,9 @@ gem_attach(sc, enaddr)
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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struct mii_data *mii = &sc->sc_mii;
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struct mii_softc *child;
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struct ifmedia_entry *ifm;
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int i, error;
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u_int32_t v;
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/* Make sure the chip is stopped. */
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ifp->if_softc = sc;
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@ -189,8 +191,9 @@ gem_attach(sc, enaddr)
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txs = &sc->sc_txsoft[i];
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txs->txs_mbuf = NULL;
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if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES,
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GEM_NTXSEGS, MCLBYTES, 0, 0,
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if ((error = bus_dmamap_create(sc->sc_dmatag,
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ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS,
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ETHER_MAX_LEN_JUMBO, 0, 0,
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&txs->txs_dmamap)) != 0) {
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printf("%s: unable to create tx DMA map %d, "
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"error = %d\n", sc->sc_dev.dv_xname, i, error);
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@ -219,9 +222,18 @@ gem_attach(sc, enaddr)
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*/
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/* Announce ourselves. */
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printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname,
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printf("%s: Ethernet address %s", sc->sc_dev.dv_xname,
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ether_sprintf(enaddr));
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/* Get RX FIFO size */
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sc->sc_rxfifosize = 64 *
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bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE);
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printf(", %uKB RX fifo", sc->sc_rxfifosize / 1024);
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/* Get TX FIFO size */
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v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE);
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printf(", %uKB TX fifo\n", v / 16);
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/* Initialize ifnet structure. */
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strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
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ifp->if_softc = sc;
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@ -276,6 +288,7 @@ gem_attach(sc, enaddr)
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}
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sc->sc_phys[child->mii_inst] = child->mii_phy;
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}
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/*
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@ -305,6 +318,24 @@ gem_attach(sc, enaddr)
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ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO);
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}
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/*
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* If we support GigE media, we support jumbo frames too.
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* Unless we are Apple.
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*/
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TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) {
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if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T ||
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IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX ||
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IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX ||
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IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) {
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if (sc->sc_variant != GEM_APPLE_GMAC)
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sc->sc_ethercom.ec_capabilities
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|= ETHERCAP_JUMBO_MTU;
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sc->sc_flags |= GEM_GIGABIT;
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break;
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}
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}
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/* claim 802.1q capability */
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sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
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@ -705,6 +736,7 @@ gem_init(struct ifnet *ifp)
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t h = sc->sc_h;
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int s;
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u_int max_frame_size;
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u_int32_t v;
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s = splnet();
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@ -734,10 +766,12 @@ gem_init(struct ifnet *ifp)
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/* step 4. TX MAC registers & counters */
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gem_init_regs(sc);
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max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU);
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max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN;
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if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)
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max_frame_size += ETHER_VLAN_ENCAP_LEN;
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bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
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((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
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ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN + sizeof(struct ether_header):
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ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16));
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max_frame_size|/* burst size */(0x2000<<16));
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/* step 5. RX MAC registers & counters */
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gem_setladrf(sc);
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@ -782,14 +816,16 @@ gem_init(struct ifnet *ifp)
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(2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN|
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(0<<GEM_RX_CONFIG_CXM_START_SHFT));
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/*
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* The following value is for an OFF Threshold of about 15.5 Kbytes
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* and an ON Threshold of 4K bytes.
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* The following value is for an OFF Threshold of about 3/4 full
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* and an ON Threshold of 1/4 full.
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*/
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bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 0xf8 | (0x40 << 12));
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bus_space_write_4(t, h, GEM_RX_BLANKING, (2<<12)|6);
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bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
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(3 * sc->sc_rxfifosize / 256) |
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( (sc->sc_rxfifosize / 256) << 12));
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bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6);
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/* step 11. Configure Media */
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gem_mii_statchg(&sc->sc_dev);
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mii_mediachg(&sc->sc_mii);
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/* XXXX Serial link needs a whole different setup. */
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@ -827,6 +863,7 @@ gem_init_regs(struct gem_softc *sc)
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t h = sc->sc_h;
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const u_char *laddr = LLADDR(ifp->if_sadl);
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u_int32_t v;
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/* These regs are not cleared on reset */
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if (!sc->sc_inited) {
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@ -839,14 +876,15 @@ gem_init_regs(struct gem_softc *sc)
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bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
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/* Max frame and max burst size */
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bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
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(ifp->if_mtu+18) | (0x2000<<16)/* Burst size */);
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ETHER_MAX_LEN | (0x2000<<16));
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bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7);
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bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4);
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bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
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/* Dunno.... */
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bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
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bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
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((laddr[5]<<8)|laddr[4])&0x3ff);
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((laddr[5]<<8)|laddr[4])&0x3ff);
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/* Secondary MAC addr set to 0:0:0:0:0:0 */
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bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
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@ -896,10 +934,24 @@ gem_init_regs(struct gem_softc *sc)
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bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
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bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
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#if 0
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if (sc->sc_variant != APPLE_GMAC)
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return;
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#endif
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/*
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* Enable MII outputs. Enable GMII if there is a gigabit PHY.
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*/
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sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
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v = GEM_MAC_XIF_TX_MII_ENA;
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if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
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v |= GEM_MAC_XIF_FDPLX_LED;
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if (sc->sc_flags & GEM_GIGABIT)
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v |= GEM_MAC_XIF_GMII_MODE;
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}
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bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
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}
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void
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gem_start(ifp)
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struct ifnet *ifp;
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@ -948,6 +1000,13 @@ gem_start(ifp)
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*/
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if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0,
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BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) {
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if (m0->m_pkthdr.len > MCLBYTES) {
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printf("%s: unable to allocate jumbo Tx "
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"cluster\n", sc->sc_dev.dv_xname);
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IFQ_DEQUEUE(&ifp->if_snd, m0);
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m_freem(m0);
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continue;
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}
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MGETHDR(m, M_DONTWAIT, MT_DATA);
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if (m == NULL) {
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printf("%s: unable to allocate Tx mbuf\n",
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@ -1636,6 +1695,7 @@ gem_mii_statchg(dev)
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v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG);
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v = GEM_MAC_XIF_LINK_LED;
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v |= GEM_MAC_XIF_TX_MII_ENA;
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/* If an external transceiver is connected, enable its MII drivers */
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sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
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if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
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@ -1643,9 +1703,10 @@ gem_mii_statchg(dev)
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if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
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/* turn on full duplex LED */
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v |= GEM_MAC_XIF_FDPLX_LED;
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else
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/* half duplex -- disable echo */
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v |= GEM_MAC_XIF_ECHO_DISABL;
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else
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/* half duplex -- disable echo */
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v |= GEM_MAC_XIF_ECHO_DISABL;
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if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000))
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v |= GEM_MAC_XIF_GMII_MODE;
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else
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@ -1746,44 +1807,46 @@ void
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gem_setladrf(sc)
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struct gem_softc *sc;
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{
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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struct ethercom *ec = &sc->sc_ethercom;
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struct ifnet *ifp = &ec->ec_if;
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struct ether_multi *enm;
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struct ether_multistep step;
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struct ethercom *ec = &sc->sc_ethercom;
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t h = sc->sc_h;
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u_char *cp;
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u_int32_t crc;
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u_int32_t hash[16];
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u_int32_t v;
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int len;
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/* Clear hash table */
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memset(hash, 0, sizeof(hash));
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int i;
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/* Get current RX configuration */
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v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
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/*
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* Turn off promiscuous mode, promiscuous group mode (all multicast),
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* and hash filter. Depending on the case, the right bit will be
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* enabled.
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*/
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v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
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GEM_MAC_RX_PROMISC_GRP);
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if ((ifp->if_flags & IFF_PROMISC) != 0) {
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/* Turn on promiscuous mode; turn off the hash filter */
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/* Turn on promiscuous mode */
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v |= GEM_MAC_RX_PROMISCUOUS;
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v &= ~GEM_MAC_RX_HASH_FILTER;
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ifp->if_flags |= IFF_ALLMULTI;
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goto chipit;
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}
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/* Turn off promiscuous mode; turn on the hash filter */
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v &= ~GEM_MAC_RX_PROMISCUOUS;
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v |= GEM_MAC_RX_HASH_FILTER;
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/*
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* Set up multicast address filter by passing all multicast addresses
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* through a crc generator, and then using the high order 6 bits as an
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* index into the 256 bit logical address filter. The high order bit
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* selects the word, while the rest of the bits select the bit within
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* the word.
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* through a crc generator, and then using the high order 8 bits as an
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* index into the 256 bit logical address filter. The high order 4
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* bits select the word, while the other 4 bits select the bit within
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* the word (where bit 0 is the MSB).
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*/
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/* Clear hash table */
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memset(hash, 0, sizeof(hash));
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ETHER_FIRST_MULTI(step, ec, enm);
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while (enm != NULL) {
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if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
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@ -1794,59 +1857,36 @@ gem_setladrf(sc)
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* the range. (At this time, the only use of address
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* ranges is for IP multicast routing, for which the
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* range is big enough to require all bits set.)
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* XXX use the addr filter for this
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*/
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hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
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ifp->if_flags |= IFF_ALLMULTI;
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v |= GEM_MAC_RX_PROMISC_GRP;
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goto chipit;
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}
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cp = enm->enm_addrlo;
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crc = 0xffffffff;
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for (len = sizeof(enm->enm_addrlo); --len >= 0;) {
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int octet = *cp++;
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int i;
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/* Get the LE CRC32 of the address */
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crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo));
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#define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */
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for (i = 0; i < 8; i++) {
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if ((crc & 1) ^ (octet & 1)) {
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crc >>= 1;
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crc ^= MC_POLY_LE;
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} else {
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crc >>= 1;
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}
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octet >>= 1;
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}
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}
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/* Just want the 8 most significant bits. */
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crc >>= 24;
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/* Set the corresponding bit in the filter. */
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hash[crc >> 4] |= 1 << (crc & 0xf);
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hash[crc >> 4] |= 1 << (15 - (crc & 15));
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ETHER_NEXT_MULTI(step, enm);
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}
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v |= GEM_MAC_RX_HASH_FILTER;
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ifp->if_flags &= ~IFF_ALLMULTI;
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chipit:
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/* Now load the hash table into the chip */
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bus_space_write_4(t, h, GEM_MAC_HASH0, hash[0]);
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bus_space_write_4(t, h, GEM_MAC_HASH1, hash[1]);
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bus_space_write_4(t, h, GEM_MAC_HASH2, hash[2]);
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bus_space_write_4(t, h, GEM_MAC_HASH3, hash[3]);
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bus_space_write_4(t, h, GEM_MAC_HASH4, hash[4]);
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bus_space_write_4(t, h, GEM_MAC_HASH5, hash[5]);
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bus_space_write_4(t, h, GEM_MAC_HASH6, hash[6]);
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bus_space_write_4(t, h, GEM_MAC_HASH7, hash[7]);
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bus_space_write_4(t, h, GEM_MAC_HASH8, hash[8]);
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bus_space_write_4(t, h, GEM_MAC_HASH9, hash[9]);
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bus_space_write_4(t, h, GEM_MAC_HASH10, hash[10]);
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bus_space_write_4(t, h, GEM_MAC_HASH11, hash[11]);
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bus_space_write_4(t, h, GEM_MAC_HASH12, hash[12]);
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bus_space_write_4(t, h, GEM_MAC_HASH13, hash[13]);
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bus_space_write_4(t, h, GEM_MAC_HASH14, hash[14]);
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bus_space_write_4(t, h, GEM_MAC_HASH15, hash[15]);
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/* Now load the hash table into the chip (if we are using it) */
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for (i = 0; i < 16; i++) {
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bus_space_write_4(t, h,
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GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
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hash[i]);
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}
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chipit:
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bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: gemreg.h,v 1.3 2002/05/08 02:12:55 matt Exp $ */
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/* $NetBSD: gemreg.h,v 1.4 2002/05/11 00:36:02 matt Exp $ */
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/*
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*
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@ -204,13 +204,14 @@
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/* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */
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#define GEM_RX_PTH_XOFF_THRESH 0x000001ff
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#define GEM_RX_PTH_XON_THRESH 0x07fc0000
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#define GEM_RX_PTH_XON_THRESH 0x001ff000
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/* GEM_RX_BLANKING register bits */
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#define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */
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||||
#define GEM_RX_BLANKING_TIME 0x03fc0000 /* Delay intr for x ticks */
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||||
/* One tick is 1048 PCI clocs, or 16us at 66MHz */
|
||||
#define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */
|
||||
#define GEM_RX_BLANKING_TIME_SHIFT 12
|
||||
/* One tick is 2048 PCI clocks, or 16us at 66MHz */
|
||||
|
||||
|
||||
/* GEM_MAC registers */
|
||||
|
|
@ -475,6 +476,8 @@
|
|||
#define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */
|
||||
#define GEM_MII_DATAPATH_MII 0x00000004 /* Use MII, not PCS */
|
||||
#define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */
|
||||
#define GEM_MII_DATAPATH_BITS "\177\020" \
|
||||
"b\0SERIAL\0b\1SERDES\0b\2MII\0b\3MIIOUT\0\0"
|
||||
|
||||
|
||||
/* GEM_MII_SLINK_CONTROL reg */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: gemvar.h,v 1.6 2002/05/08 02:12:55 matt Exp $ */
|
||||
/* $NetBSD: gemvar.h,v 1.7 2002/05/11 00:36:03 matt Exp $ */
|
||||
|
||||
/*
|
||||
*
|
||||
|
|
@ -130,6 +130,13 @@ struct gem_softc {
|
|||
int sc_mif_config; /* Selected MII reg setting */
|
||||
|
||||
int sc_pci; /* XXXXX -- PCI buses are LE. */
|
||||
u_int sc_variant; /* which GEM are we dealing with? */
|
||||
#define GEM_UNKNOWN 0 /* don't know */
|
||||
#define GEM_SUN_GEM 1 /* Sun GEM variant */
|
||||
#define GEM_APPLE_GMAC 2 /* Apple GMAC variant */
|
||||
|
||||
u_int sc_flags; /* */
|
||||
#define GEM_GIGABIT 0x0001 /* has a gigabit PHY */
|
||||
|
||||
void *sc_sdhook; /* shutdown hook */
|
||||
void *sc_powerhook; /* power management hook */
|
||||
|
|
@ -163,6 +170,7 @@ struct gem_softc {
|
|||
struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */
|
||||
|
||||
int sc_rxptr; /* next ready RX descriptor/descsoft */
|
||||
int sc_rxfifosize; /* Rx FIFO size (bytes) */
|
||||
|
||||
/* ========== */
|
||||
int sc_inited;
|
||||
|
|
|
|||
Loading…
Reference in New Issue