Centralise SYNC/BDSYNC in asm.h and introduce a new LLCSCSYNC and use it
before any ll/sc sequences.
Define LLSCSYNC as syncw; syncw for cnMIPS - issue two as early cnMIPS
has errat{um,a} that means the first can fail.
This commit is contained in:
skrll
parent
e3a3fcce9b
commit
bf8d907e75
@ -1,4 +1,4 @@
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/* $NetBSD: atomic_add.S,v 1.6 2020/08/01 09:26:49 skrll Exp $ */
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/* $NetBSD: atomic_add.S,v 1.7 2020/08/06 10:00:21 skrll Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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@ -29,7 +29,7 @@
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#include <machine/asm.h>
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#include "atomic_op_asm.h"
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RCSID("$NetBSD: atomic_add.S,v 1.6 2020/08/01 09:26:49 skrll Exp $")
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RCSID("$NetBSD: atomic_add.S,v 1.7 2020/08/06 10:00:21 skrll Exp $")
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.text
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.set noreorder
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@ -49,6 +49,7 @@ LEAF(_atomic_add_32)
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#if defined(_MIPS_ARCH_OCTEONP) || defined(_MIPS_ARCH_OCTEON2)
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saa a1, (a0)
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#else
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LLSCSYNC
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1: INT_LL t0, 0(a0)
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nop
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INT_ADDU t0, a1
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@ -62,6 +63,7 @@ END(_atomic_add_32)
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ATOMIC_OP_ALIAS(atomic_add_32, _atomic_add_32)
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LEAF(_atomic_add_32_nv)
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LLSCSYNC
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1: INT_LL v0, 0(a0)
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nop
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INT_ADDU v0, a1
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@ -79,6 +81,7 @@ LEAF(_atomic_add_64)
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#if defined(_MIPS_ARCH_OCTEONP) || defined(_MIPS_ARCH_OCTEON2)
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saad a1, (a0)
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#else
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LLSCSYNC
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1: REG_LL t0, 0(a0)
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nop
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REG_ADDU t0, a1
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@ -92,6 +95,7 @@ END(_atomic_add_64)
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ATOMIC_OP_ALIAS(atomic_add_64, _atomic_add_64)
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LEAF(_atomic_add_64_nv)
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LLSCSYNC
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1: REG_LL v0, 0(a0)
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nop
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REG_ADDU v0, a1
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@ -1,4 +1,4 @@
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/* $NetBSD: atomic_and.S,v 1.5 2020/08/01 09:26:49 skrll Exp $ */
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/* $NetBSD: atomic_and.S,v 1.6 2020/08/06 10:00:21 skrll Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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@ -29,7 +29,7 @@
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#include <machine/asm.h>
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#include "atomic_op_asm.h"
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RCSID("$NetBSD: atomic_and.S,v 1.5 2020/08/01 09:26:49 skrll Exp $")
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RCSID("$NetBSD: atomic_and.S,v 1.6 2020/08/06 10:00:21 skrll Exp $")
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.text
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.set noreorder
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@ -46,6 +46,7 @@ RCSID("$NetBSD: atomic_and.S,v 1.5 2020/08/01 09:26:49 skrll Exp $")
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LEAF(_atomic_and_32)
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LLSCSYNC
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1: INT_LL t0, 0(a0)
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nop
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and t0, a1
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@ -58,6 +59,7 @@ END(_atomic_and_32)
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ATOMIC_OP_ALIAS(atomic_and_32, _atomic_and_32)
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LEAF(_atomic_and_32_nv)
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LLSCSYNC
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1: INT_LL v0, 0(a0)
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nop
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and v0, a1
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@ -72,6 +74,7 @@ ATOMIC_OP_ALIAS(atomic_and_32_nv, _atomic_and_32_nv)
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#if !defined(__mips_o32)
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LEAF(_atomic_and_64)
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LLSCSYNC
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1: REG_LL t0, 0(a0)
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nop
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and t0, a1
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@ -84,6 +87,7 @@ END(_atomic_and_64)
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ATOMIC_OP_ALIAS(atomic_and_64, _atomic_and_64)
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LEAF(_atomic_and_64_nv)
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LLSCSYNC
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1: REG_LL v0, 0(a0)
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nop
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and v0, a1
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@ -1,4 +1,4 @@
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/* $NetBSD: atomic_cas.S,v 1.7 2020/08/01 09:26:49 skrll Exp $ */
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/* $NetBSD: atomic_cas.S,v 1.8 2020/08/06 10:00:21 skrll Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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@ -29,7 +29,7 @@
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#include <machine/asm.h>
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#include "atomic_op_asm.h"
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RCSID("$NetBSD: atomic_cas.S,v 1.7 2020/08/01 09:26:49 skrll Exp $")
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RCSID("$NetBSD: atomic_cas.S,v 1.8 2020/08/06 10:00:21 skrll Exp $")
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.text
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.set noat
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@ -37,6 +37,7 @@ RCSID("$NetBSD: atomic_cas.S,v 1.7 2020/08/01 09:26:49 skrll Exp $")
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.set nomacro
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LEAF(_atomic_cas_32)
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LLSCSYNC
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1: INT_LL v0, 0(a0)
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nop
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bne v0, a1, 2f
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@ -58,6 +59,7 @@ ATOMIC_OP_ALIAS(atomic_cas_32_ni, _atomic_cas_32)
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#if !defined(__mips_o32)
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LEAF(_atomic_cas_64)
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LLSCSYNC
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1: REG_LL v0, 0(a0)
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nop
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bne v0, a1, 2f
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@ -1,4 +1,4 @@
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/* $NetBSD: atomic_dec.S,v 1.6 2020/08/01 09:26:49 skrll Exp $ */
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/* $NetBSD: atomic_dec.S,v 1.7 2020/08/06 10:00:21 skrll Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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@ -29,7 +29,7 @@
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#include <machine/asm.h>
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#include "atomic_op_asm.h"
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RCSID("$NetBSD: atomic_dec.S,v 1.6 2020/08/01 09:26:49 skrll Exp $")
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RCSID("$NetBSD: atomic_dec.S,v 1.7 2020/08/06 10:00:21 skrll Exp $")
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.text
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.set noreorder
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@ -49,6 +49,7 @@ LEAF(_atomic_dec_32)
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li t0, -1
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saa t0, (a0)
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#else
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LLSCSYNC
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1: INT_LL t0, 0(a0)
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nop
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INT_ADDU t0, -1
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@ -62,6 +63,7 @@ END(_atomic_dec_32)
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ATOMIC_OP_ALIAS(atomic_dec_32, _atomic_dec_32)
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LEAF(_atomic_dec_32_nv)
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LLSCSYNC
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1: INT_LL v0, 0(a0)
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nop
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INT_ADDU v0, -1
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@ -80,6 +82,7 @@ LEAF(_atomic_dec_64)
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li t0, -1
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saad t0, (a0)
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#else
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LLSCSYNC
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1: REG_LL t0, 0(a0)
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nop
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REG_ADDU t0, -1
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@ -93,6 +96,7 @@ END(_atomic_dec_64)
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ATOMIC_OP_ALIAS(atomic_dec_64, _atomic_dec_64)
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LEAF(_atomic_dec_64_nv)
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LLSCSYNC
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1: REG_LL v0, 0(a0)
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nop
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REG_ADDU v0, -1
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@ -1,4 +1,4 @@
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/* $NetBSD: atomic_inc.S,v 1.6 2020/08/01 09:26:49 skrll Exp $ */
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/* $NetBSD: atomic_inc.S,v 1.7 2020/08/06 10:00:21 skrll Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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@ -29,7 +29,7 @@
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#include <machine/asm.h>
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#include "atomic_op_asm.h"
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RCSID("$NetBSD: atomic_inc.S,v 1.6 2020/08/01 09:26:49 skrll Exp $")
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RCSID("$NetBSD: atomic_inc.S,v 1.7 2020/08/06 10:00:21 skrll Exp $")
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.text
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.set noreorder
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@ -50,6 +50,7 @@ LEAF(_atomic_inc_32)
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li t0, 1
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saa t0, (a0)
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#else
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LLSCSYNC
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1: INT_LL t0, 0(a0)
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nop
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INT_ADDU t0, 1
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@ -63,6 +64,7 @@ END(_atomic_inc_32)
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ATOMIC_OP_ALIAS(atomic_inc_32, _atomic_inc_32)
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LEAF(_atomic_inc_32_nv)
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LLSCSYNC
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1: INT_LL v0, 0(a0)
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nop
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INT_ADDU v0, 1
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@ -81,6 +83,7 @@ LEAF(_atomic_inc_64)
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li t0, 1
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saad t0, (a0)
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#else
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LLSCSYNC
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1: REG_LL t0, 0(a0)
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nop
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REG_ADDU t0, 1
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@ -94,6 +97,7 @@ END(_atomic_inc_64)
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ATOMIC_OP_ALIAS(atomic_inc_64, _atomic_inc_64)
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LEAF(_atomic_inc_64_nv)
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LLSCSYNC
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1: REG_LL v0, 0(a0)
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nop
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REG_ADDU v0, 1
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@ -1,4 +1,4 @@
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/* $NetBSD: atomic_or.S,v 1.5 2020/08/01 09:26:49 skrll Exp $ */
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/* $NetBSD: atomic_or.S,v 1.6 2020/08/06 10:00:21 skrll Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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@ -43,6 +43,7 @@
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#endif /* _KERNEL_OPT */
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LEAF(_atomic_or_32)
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LLSCSYNC
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1: INT_LL t0, 0(a0)
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nop
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or t0, a1
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@ -55,6 +56,7 @@ END(_atomic_or_32)
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ATOMIC_OP_ALIAS(atomic_or_32, _atomic_or_32)
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LEAF(_atomic_or_32_nv)
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LLSCSYNC
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1: INT_LL v0, 0(a0)
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nop
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or v0, a1
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@ -69,6 +71,7 @@ ATOMIC_OP_ALIAS(atomic_or_32_nv, _atomic_or_32_nv)
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#if !defined(__mips_o32)
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LEAF(_atomic_or_64)
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LLSCSYNC
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1: REG_LL t0, 0(a0)
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nop
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or t0, a1
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@ -81,6 +84,7 @@ END(_atomic_or_64)
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ATOMIC_OP_ALIAS(atomic_or_64, _atomic_or_64)
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LEAF(_atomic_or_64_nv)
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LLSCSYNC
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1: REG_LL v0, 0(a0)
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nop
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or v0, a1
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@ -1,4 +1,4 @@
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/* $NetBSD: atomic_swap.S,v 1.6 2020/08/01 09:26:49 skrll Exp $ */
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/* $NetBSD: atomic_swap.S,v 1.7 2020/08/06 10:00:21 skrll Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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@ -29,7 +29,7 @@
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#include <machine/asm.h>
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#include "atomic_op_asm.h"
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RCSID("$NetBSD: atomic_swap.S,v 1.6 2020/08/01 09:26:49 skrll Exp $")
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RCSID("$NetBSD: atomic_swap.S,v 1.7 2020/08/06 10:00:21 skrll Exp $")
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.text
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.set noreorder
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@ -44,8 +44,8 @@ RCSID("$NetBSD: atomic_swap.S,v 1.6 2020/08/01 09:26:49 skrll Exp $")
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.set nomacro
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#endif /* _KERNEL_OPT */
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LEAF(_atomic_swap_32)
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LLSCSYNC
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1: INT_LL v0, 0(a0)
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nop
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move t0, a1
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@ -60,6 +60,7 @@ ATOMIC_OP_ALIAS(atomic_swap_32, _atomic_swap_32)
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#if !defined(__mips_o32)
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LEAF(_atomic_swap_64)
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LLSCSYNC
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1: REG_LL v0, 0(a0)
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nop
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move t0, a1
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@ -1,4 +1,4 @@
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/* $NetBSD: asm.h,v 1.57 2020/07/26 08:08:41 simonb Exp $ */
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/* $NetBSD: asm.h,v 1.58 2020/08/06 10:00:20 skrll Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -54,6 +54,10 @@
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#ifndef _MIPS_ASM_H
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#define _MIPS_ASM_H
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#include "opt_cputype.h"
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#include "opt_lockdebug.h"
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#include "opt_multiprocessor.h"
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#include <sys/cdefs.h> /* for API selection */
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#include <mips/regdef.h>
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@ -513,6 +517,24 @@ _C_LABEL(x):
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#define NOP_L /* nothing */
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#endif
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#if defined(MULTIPROCESSOR)
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#if defined(MIPS64_OCTEON)
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/* early cnMIPS have erratum which means 2 */
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#define LLSCSYNC sync 4; sync 4
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#define SYNC sync 4 /* sync 4 == syncw - sync all writes */
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#define BDSYNC sync 4 /* sync 4 == syncw - sync all writes */
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#else
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#define LLSCSYNC /* nothing (something?) */
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#define SYNC sync
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#define BDSYNC sync
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#endif
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#else
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#define LLSCSYNC /* nothing */
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#define SYNC /* nothing */
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#define BDSYNC nop
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#endif /* defined(MULTIPROCESSOR) */
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/* CPU dependent hook for cp0 load delays */
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#if defined(MIPS1) || defined(MIPS2) || defined(MIPS3)
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#define MFC0_HAZARD sll $0,$0,1 /* super scalar nop */
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@ -1,4 +1,4 @@
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/* $NetBSD: lock_stubs_llsc.S,v 1.10 2020/08/01 07:09:41 simonb Exp $ */
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/* $NetBSD: lock_stubs_llsc.S,v 1.11 2020/08/06 10:00:21 skrll Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -37,7 +37,7 @@
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#include <machine/asm.h>
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RCSID("$NetBSD: lock_stubs_llsc.S,v 1.10 2020/08/01 07:09:41 simonb Exp $")
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RCSID("$NetBSD: lock_stubs_llsc.S,v 1.11 2020/08/06 10:00:21 skrll Exp $")
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#include "assym.h"
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@ -45,20 +45,6 @@ RCSID("$NetBSD: lock_stubs_llsc.S,v 1.10 2020/08/01 07:09:41 simonb Exp $")
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#define FULL
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#endif
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#if defined(MULTIPROCESSOR)
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#if defined(__OCTEON__)
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#define SYNC sync 4 /* sync 4 == syncw - sync all writes */
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#define BDSYNC sync 4 /* sync 4 == syncw - sync all writes */
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#else
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#define SYNC sync
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#define BDSYNC sync
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#endif
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#else
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#define SYNC /* nothing */
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#define BDSYNC nop
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#endif /* MIPS_HAS_LLSC != 0 && defined(MULTIPROCESSOR) */
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/*
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* Set ISA level for the assembler.
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* XXX Clean up with a macro? Same code fragment is in mipsX_subr.S too.
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@ -84,6 +70,7 @@ RCSID("$NetBSD: lock_stubs_llsc.S,v 1.10 2020/08/01 07:09:41 simonb Exp $")
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* unsigned long old, unsigned long new);
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*/
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STATIC_LEAF(llsc_atomic_cas_ulong)
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LLSCSYNC
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1:
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LONG_LL t0, (a0)
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bne t0, a1, 2f
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@ -104,6 +91,7 @@ END(llsc_atomic_cas_ulong)
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* unsigned int old, unsigned int new);
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*/
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STATIC_LEAF(llsc_atomic_cas_uint)
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LLSCSYNC
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1:
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INT_LL t0, (a0)
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bne t0, a1, 2f
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@ -133,6 +121,7 @@ STATIC_LEAF(llsc_ucas_32)
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nop
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move v0, zero
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LLSCSYNC
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1: ll t0, 0(a0)
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bne t0, a1, 2f
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move t1, a2
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@ -161,6 +150,7 @@ STATIC_LEAF(llsc_ucas_64)
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nop
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move v0, zero
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LLSCSYNC
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1: lld t0, 0(a0)
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bne t0, a1, 2f
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move t1, a2
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@ -187,6 +177,7 @@ END(llsc_ucaserr)
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* void mutex_enter(kmutex_t *mtx);
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*/
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STATIC_LEAF(llsc_mutex_enter)
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LLSCSYNC
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PTR_LL t0, MTX_OWNER(a0)
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1:
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bnez t0, 2f
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@ -205,6 +196,7 @@ END(llsc_mutex_enter)
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* void mutex_exit(kmutex_t *mtx);
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*/
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STATIC_LEAF(llsc_mutex_exit)
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LLSCSYNC
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PTR_LL t0, MTX_OWNER(a0)
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SYNC
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1:
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@ -268,6 +260,7 @@ STATIC_NESTED(llsc_mutex_spin_enter, CALLFRAME_SIZ, ra)
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nop
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#endif /* PARANOIA */
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#if defined(FULL)
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LLSCSYNC
|
||||
INT_LL t3, MTX_LOCK(t0)
|
||||
3:
|
||||
bnez t3, 4f
|
||||
|
||||
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Reference in New Issue
Block a user