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add support for i.MX6UltraLite, and 

ConnectCore for iMX6UL Starter Board.
This commit is contained in:
ryo 2017-06-09 18:14:59 +00:00
parent 170cdb15b3
commit bf4c80a7b2
25 changed files with 1276 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
etc/etc.evbarm/Makefile.inc
View File

@ -1,4 +1,4 @@
# $NetBSD: Makefile.inc,v 1.81 2017/01/07 16:29:04 kiyohara Exp $
# $NetBSD: Makefile.inc,v 1.82 2017/06/09 18:14:59 ryo Exp $
#
# etc.evbarm/Makefile.inc -- evbarm-specific etc Makefile targets
#
@ -105,6 +105,8 @@ EVBARM_BOARDS.armv7hf+= CUBOX-I
EVBARM_BOARDS.armv7+= HUMMINGBIRD_A31
EVBARM_BOARDS.armv7hf+= HUMMINGBIRD_A31
#EVBARM_BOARDS.armv7+= IGEPV2
EVBARM_BOARDS.armv7+= IMX6UL-STARTER
EVBARM_BOARDS.armv7hf+= IMX6UL-STARTER
EVBARM_BOARDS.armv7+= TEGRA
EVBARM_BOARDS.armv7hf+= TEGRA
EVBARM_BOARDS.armv7+= ARMADILLO-IOT-G3

45
sys/arch/arm/imx/if_enet.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_enet.c,v 1.10 2016/12/15 09:28:02 ozaki-r Exp $ */
/* $NetBSD: if_enet.c,v 1.11 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_enet.c,v 1.10 2016/12/15 09:28:02 ozaki-r Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_enet.c,v 1.11 2017/06/09 18:14:59 ryo Exp $");
#include "vlan.h"
@ -92,8 +92,10 @@ int enet_debug = 0;
#define ENET_MAX_PKT_NSEGS 64
#define ENET_TX_NEXTIDX(idx) (((idx) >= (ENET_TX_RING_CNT - 1)) ? 0 : ((idx) + 1))
#define ENET_RX_NEXTIDX(idx) (((idx) >= (ENET_RX_RING_CNT - 1)) ? 0 : ((idx) + 1))
#define ENET_TX_NEXTIDX(idx) \
(((idx) >= (ENET_TX_RING_CNT - 1)) ? 0 : ((idx) + 1))
#define ENET_RX_NEXTIDX(idx) \
(((idx) >= (ENET_RX_RING_CNT - 1)) ? 0 : ((idx) + 1))
#define TXDESC_WRITEOUT(idx) \
bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap, \
@ -234,13 +236,15 @@ enet_attach_common(device_t self, bus_space_tag_t iot,
/* i.MX7 use 3 interrupts */
if ((sc->sc_ih2 = intr_establish(irq + 1, IPL_NET,
IST_LEVEL, enet_intr, sc)) == NULL) {
aprint_error_dev(self, "unable to establish 2nd interrupt\n");
aprint_error_dev(self,
"unable to establish 2nd interrupt\n");
intr_disestablish(sc->sc_ih);
goto failure;
}
if ((sc->sc_ih3 = intr_establish(irq + 2, IPL_NET,
IST_LEVEL, enet_intr, sc)) == NULL) {
aprint_error_dev(self, "unable to establish 3rd interrupt\n");
aprint_error_dev(self,
"unable to establish 3rd interrupt\n");
intr_disestablish(sc->sc_ih2);
intr_disestablish(sc->sc_ih);
goto failure;
@ -1030,8 +1034,8 @@ enet_ioctl(struct ifnet *ifp, u_long command, void *data)
ENET_REG_WRITE(sc, ENET_FTRL, v);
v = ENET_REG_READ(sc, ENET_RCR);
v &= ~ENET_RCR_MAX_FL(0x3fff);
v |= ENET_RCR_MAX_FL(ifp->if_mtu +
ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
v |= ENET_RCR_MAX_FL(ifp->if_mtu + ETHER_HDR_LEN +
ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
ENET_REG_WRITE(sc, ENET_RCR, v);
}
break;
@ -1187,6 +1191,7 @@ enet_miibus_statchg(struct ifnet *ifp)
case IFM_AUTO:
case IFM_1000_T:
ecr |= ENET_ECR_SPEED; /* 1000Mbps mode */
rcr &= ~ENET_RCR_RMII_10T;
break;
case IFM_100_TX:
ecr &= ~ENET_ECR_SPEED; /* 100Mbps mode */
@ -1203,6 +1208,9 @@ enet_miibus_statchg(struct ifnet *ifp)
break;
}
if (sc->sc_rgmii == 0)
ecr &= ~ENET_ECR_SPEED;
if (sc->sc_flowflags & IFM_FLOW)
rcr |= ENET_RCR_FCE;
else
@ -1227,7 +1235,7 @@ enet_init_txring(struct enet_softc *sc)
/* build TX ring */
for (i = 0; i < ENET_TX_RING_CNT; i++) {
sc->sc_txdesc_ring[i].tx_flags1_len =
sc->sc_txdesc_ring[i].tx_flags1_len =
((i == (ENET_TX_RING_CNT - 1)) ? TXFLAGS1_W : 0);
sc->sc_txdesc_ring[i].tx_databuf = 0;
sc->sc_txdesc_ring[i].tx_flags2 = TXFLAGS2_INT;
@ -1298,7 +1306,7 @@ enet_alloc_rxbuf(struct enet_softc *sc, int idx)
}
bus_dmamap_sync(sc->sc_dmat, sc->sc_rxsoft[idx].rxs_dmamap, 0,
sc->sc_rxsoft[idx].rxs_dmamap->dm_mapsize,
sc->sc_rxsoft[idx].rxs_dmamap->dm_mapsize,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
sc->sc_rxsoft[idx].rxs_mbuf = m;
@ -1578,7 +1586,8 @@ enet_encap_mbufalign(struct mbuf **mp)
ap = mt->m_dat;
}
ap = ALIGN_PTR(ap, ALIGNBYTE);
memcpy(ap, mt->m_data, mt->m_len);
memcpy(ap, mt->m_data,
mt->m_len);
mt->m_data = ap;
}
@ -1765,7 +1774,7 @@ enet_init_regs(struct enet_softc *sc, int init)
struct ifmedia_entry *ife;
paddr_t paddr;
uint32_t val;
int fulldup, ecr_speed, rcr_speed, flowctrl;
int miimode, fulldup, ecr_speed, rcr_speed, flowctrl;
if (init) {
fulldup = 1;
@ -1799,6 +1808,9 @@ enet_init_regs(struct enet_softc *sc, int init)
flowctrl = sc->sc_flowflags & IFM_FLOW;
}
if (sc->sc_rgmii == 0)
ecr_speed = 0;
/* reset */
ENET_REG_WRITE(sc, ENET_ECR, ecr_speed | ENET_ECR_RESET);
@ -1846,9 +1858,14 @@ enet_init_regs(struct enet_softc *sc, int init)
/* maximum frame size */
val = ENET_DEFAULT_PKT_LEN;
ENET_REG_WRITE(sc, ENET_FTRL, val); /* Frame Truncation Length */
if (sc->sc_rgmii == 0)
miimode = ENET_RCR_RMII_MODE | ENET_RCR_MII_MODE;
else
miimode = ENET_RCR_RGMII_EN;
ENET_REG_WRITE(sc, ENET_RCR,
ENET_RCR_PADEN | /* RX frame padding remove */
ENET_RCR_RGMII_EN | /* use RGMII */
miimode |
(flowctrl ? ENET_RCR_FCE : 0) | /* flow control enable */
rcr_speed |
(fulldup ? 0 : ENET_RCR_DRT) |
@ -1880,7 +1897,7 @@ enet_init_regs(struct enet_softc *sc, int init)
#if _BYTE_ORDER == _LITTLE_ENDIAN
ENET_ECR_DBSWP |
#endif
ENET_ECR_SPEED | /* default 1000Mbps mode */
ecr_speed |
ENET_ECR_EN1588 | /* use enhanced TX/RX descriptor */
ENET_ECR_ETHEREN); /* Ethernet Enable */

54
sys/arch/arm/imx/if_enet_imx6.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_enet_imx6.c,v 1.2 2016/11/24 03:59:36 hkenken Exp $ */
/* $NetBSD: if_enet_imx6.c,v 1.3 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_enet_imx6.c,v 1.2 2016/11/24 03:59:36 hkenken Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_enet_imx6.c,v 1.3 2017/06/09 18:14:59 ryo Exp $");
#include "locators.h"
#include "imxccm.h"
@ -41,6 +41,7 @@ __KERNEL_RCSID(0, "$NetBSD: if_enet_imx6.c,v 1.2 2016/11/24 03:59:36 hkenken Exp
#include <arm/imx/imx6_reg.h>
#include <arm/imx/imx6_ccmreg.h>
#include <arm/imx/imx6_ccmvar.h>
#include <arm/imx/imx6_iomuxreg.h>
#include <arm/imx/imx6_ocotpreg.h>
#include <arm/imx/imx6_ocotpvar.h>
#include <arm/imx/if_enetreg.h>
@ -56,6 +57,10 @@ enet_match(device_t parent __unused, struct cfdata *match __unused, void *aux)
switch (aa->aa_addr) {
case (IMX6_AIPS2_BASE + AIPS2_ENET_BASE):
return 1;
case (IMX6_AIPS1_BASE + AIPS1_ENET2_BASE):
if (IMX6_CHIPID_MAJOR(imx6_chip_id()) == CHIPID_MAJOR_IMX6UL)
return 1;
break;
}
return 0;
@ -77,7 +82,19 @@ enet_attach(device_t parent, device_t self, void *aux)
aa->aa_size = AIPS_ENET_SIZE;
sc->sc_imxtype = 6; /* i.MX6 */
sc->sc_unit = 0;
if (IMX6_CHIPID_MAJOR(imx6_chip_id()) == CHIPID_MAJOR_IMX6UL)
sc->sc_rgmii = 0;
else
sc->sc_rgmii = 1;
switch (aa->aa_addr) {
case (IMX6_AIPS2_BASE + AIPS2_ENET_BASE):
sc->sc_unit = 0;
break;
case (IMX6_AIPS1_BASE + AIPS1_ENET2_BASE):
sc->sc_unit = 1;
break;
}
#if NIMXOCOTP > 0
/* get mac-address from OCOTP */
@ -88,18 +105,45 @@ enet_attach(device_t parent, device_t self, void *aux)
sc->sc_enaddr[2] = eaddr >> 24;
sc->sc_enaddr[3] = eaddr >> 16;
sc->sc_enaddr[4] = eaddr >> 8;
sc->sc_enaddr[5] = eaddr;
sc->sc_enaddr[5] = eaddr + sc->sc_unit;
#endif
#if NIMXCCM > 0
/* PLL power up */
if (imx6_pll_power(CCM_ANALOG_PLL_ENET, 1,
CCM_ANALOG_PLL_ENET_ENABLE) != 0) {
CCM_ANALOG_PLL_ENET_ENABLE) != 0) {
aprint_error_dev(sc->sc_dev,
"couldn't enable CCM_ANALOG_PLL_ENET\n");
return;
}
if (IMX6_CHIPID_MAJOR(imx6_chip_id()) == CHIPID_MAJOR_IMX6UL) {
uint32_t v;
/* iMX6UL */
if ((imx6_pll_power(CCM_ANALOG_PLL_ENET, 1,
CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN) != 0) ||
(imx6_pll_power(CCM_ANALOG_PLL_ENET, 1,
CCM_ANALOG_PLL_ENET_ENET2_125M_EN) != 0)) {
aprint_error_dev(sc->sc_dev,
"couldn't enable CCM_ANALOG_PLL_ENET\n");
return;
}
v = iomux_read(IMX6UL_IOMUX_GPR1);
switch (sc->sc_unit) {
case 0:
v |= IMX6UL_IOMUX_GPR1_ENET1_TX_CLK_DIR;
v &= ~IMX6UL_IOMUX_GPR1_ENET1_CLK_SEL;
break;
case 1:
v |= IMX6UL_IOMUX_GPR1_ENET2_TX_CLK_DIR;
v &= ~IMX6UL_IOMUX_GPR1_ENET2_CLK_SEL;
break;
}
iomux_write(IMX6UL_IOMUX_GPR1, v);
}
sc->sc_pllclock = imx6_get_clock(IMX6CLK_PLL6);
#else
sc->sc_pllclock = 50000000;

5
sys/arch/arm/imx/if_enet_imx7.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_enet_imx7.c,v 1.1 2016/05/17 06:44:45 ryo Exp $ */
/* $NetBSD: if_enet_imx7.c,v 1.2 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_enet_imx7.c,v 1.1 2016/05/17 06:44:45 ryo Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_enet_imx7.c,v 1.2 2017/06/09 18:14:59 ryo Exp $");
#include "locators.h"
#include "imxccm.h"
@ -79,6 +79,7 @@ enet_attach(device_t parent, device_t self, void *aux)
aa->aa_size = AIPS_ENET_SIZE;
sc->sc_imxtype = 7; /* i.MX7 */
sc->sc_rgmii = 1;
#if NIMXCCM > 0
/* PLL power up */

6
sys/arch/arm/imx/if_enetreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_enetreg.h,v 1.2 2016/05/17 06:44:45 ryo Exp $ */
/* $NetBSD: if_enetreg.h,v 1.3 2017/06/09 18:14:59 ryo Exp $ */
/*-
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@ -118,10 +118,14 @@
# define ENET_RCR_PAUFWD __BIT(13)
# define ENET_RCR_PADEN __BIT(12)
# define ENET_RCR_RMII_10T __BIT(9)
# define ENET_RCR_RMII_MODE __BIT(8)
# define ENET_RCR_RGMII_EN __BIT(6)
# define ENET_RCR_FCE __BIT(5)
# define ENET_RCR_BC_REJ __BIT(4)
# define ENET_RCR_PROM __BIT(3)
# define ENET_RCR_MII_MODE __BIT(2)
# define ENET_RCR_DRT __BIT(1)
# define ENET_RCR_LOOP __BIT(0)
#define ENET_TCR 0x000000c4
# define ENET_TCR_FDEN __BIT(2)

3
sys/arch/arm/imx/if_enetvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_enetvar.h,v 1.1 2016/05/17 06:44:45 ryo Exp $ */
/* $NetBSD: if_enetvar.h,v 1.2 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@ -58,6 +58,7 @@ struct enet_softc {
int sc_unit;
int sc_imxtype;
int sc_rgmii;
unsigned int sc_pllclock;
/* interrupts */

5
sys/arch/arm/imx/imx6_ahcisata.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_ahcisata.c,v 1.4 2016/11/24 03:59:36 hkenken Exp $ */
/* $NetBSD: imx6_ahcisata.c,v 1.5 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_ahcisata.c,v 1.4 2016/11/24 03:59:36 hkenken Exp $");
__KERNEL_RCSID(0, "$NetBSD: imx6_ahcisata.c,v 1.5 2017/06/09 18:14:59 ryo Exp $");
#include "locators.h"
#include "opt_imx.h"
@ -81,6 +81,7 @@ imx6_ahcisata_match(device_t parent, cfdata_t match, void *aux)
case CHIPID_MAJOR_IMX6SL:
case CHIPID_MAJOR_IMX6DL:
case CHIPID_MAJOR_IMX6SOLO:
case CHIPID_MAJOR_IMX6UL:
return 0;
default:
break;

13
sys/arch/arm/imx/imx6_board.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_board.c,v 1.7 2016/11/24 08:41:20 hkenken Exp $ */
/* $NetBSD: imx6_board.c,v 1.8 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
@ -27,10 +27,11 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: imx6_board.c,v 1.7 2016/11/24 08:41:20 hkenken Exp $");
__KERNEL_RCSID(1, "$NetBSD: imx6_board.c,v 1.8 2017/06/09 18:14:59 ryo Exp $");
#include "opt_imx.h"
#include "arml2cc.h"
#include "opt_cputypes.h"
#include <sys/param.h>
#include <sys/bus.h>
@ -223,6 +224,14 @@ imx6_device_register(device_t self, void *aux)
imx6_armrootclk() / IMX6_PERIPHCLK_N);
return;
}
#ifdef CPU_CORTEXA7
/* also for A7 */
if (device_is_a(self, "armgtmr")) {
prop_dictionary_set_uint32(dict, "frequency",
armreg_cnt_frq_read());
return;
}
#endif
}
#ifdef MULTIPROCESSOR

10
sys/arch/arm/imx/imx6_ccm.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_ccm.c,v 1.5 2016/11/24 03:59:36 hkenken Exp $ */
/* $NetBSD: imx6_ccm.c,v 1.6 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2010-2012, 2014 Genetec Corporation. All rights reserved.
@ -31,10 +31,11 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.5 2016/11/24 03:59:36 hkenken Exp $");
__KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.6 2017/06/09 18:14:59 ryo Exp $");
#include "opt_imx.h"
#include "opt_imx6clk.h"
#include "opt_cputypes.h"
#include "locators.h"
@ -48,7 +49,9 @@ __KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.5 2016/11/24 03:59:36 hkenken Exp $")
#include <sys/param.h>
#include <machine/cpu.h>
#ifdef CPU_CORTEXA9
#include <arm/cortex/a9tmr_var.h>
#endif
#include <arm/imx/imx6_ccmvar.h>
#include <arm/imx/imx6_ccmreg.h>
@ -439,7 +442,9 @@ imx6_set_clock(enum imx6_clock clk, uint32_t freq)
v = imx6_get_clock(IMX6CLK_ARM_ROOT);
cpufreq_set_all(v);
#ifdef CPU_CORTEXA9
a9tmr_update_freq(v / IMX6_PERIPHCLK_N);
#endif
return 0;
}
}
@ -501,6 +506,7 @@ imx6_get_clock(enum imx6_clock clk)
break;
case IMX6CLK_PLL6:
/* XXX: iMX6UL has 2 div. which? */
v = imx6_ccm_read(CCM_ANALOG_PLL_ENET);
switch (v & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) {
case 0:

9
sys/arch/arm/imx/imx6_ccmreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_ccmreg.h,v 1.4 2016/11/24 03:59:36 hkenken Exp $ */
/* $NetBSD: imx6_ccmreg.h,v 1.5 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@ -247,15 +247,20 @@
#define CCM_ANALOG_PLL_ENET_CLR 0x000040e8
#define CCM_ANALOG_PLL_ENET_TOG 0x000040ec
#define CCM_ANALOG_PLL_ENET_LOCK __BIT(31)
#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN __BIT(21) /* iMX6UL */
#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN __BIT(20) /* iMX6UL */
#define CCM_ANALOG_PLL_ENET_ENABLE_100M __BIT(20) /* SATA */
#define CCM_ANALOG_PLL_ENET_ENABLE_125M __BIT(19) /* PCIe */
#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN __BIT(18)
#define CCM_ANALOG_PLL_ENET_BYPASS __BIT(16)
#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(s) __SHIFTIN(s, __BITS(15, 14))
#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN __BIT(13) /* iMX6UL */
#define CCM_ANALOG_PLL_ENET_ENABLE __BIT(13) /* Ether */
#define CCM_ANALOG_PLL_ENET_POWERDOWN __BIT(12)
#define CCM_ANALOG_PLL_ENET1_DIV_SELECT(d) __SHIFTIN(d, __BITS(2, 1))
#define CCM_ANALOG_PLL_ENET1_DIV_SELECT_MASK __BITS(3, 2)
#define CCM_ANALOG_PLL_ENET_DIV_SELECT(d) __SHIFTIN(d, __BITS(1, 0))
#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK __SHIFTIN(3, __BITS(1, 0))
#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK __BITS(1, 0)
#define CCM_ANALOG_PFD_480 0x000040f0
#define CCM_ANALOG_PFD_480_SET 0x000040f4
#define CCM_ANALOG_PFD_480_CLR 0x000040f8

10
sys/arch/arm/imx/imx6_gpio.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_gpio.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/* $NetBSD: imx6_gpio.c,v 1.2 2017/06/09 18:14:59 ryo Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_gpio.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
__KERNEL_RCSID(0, "$NetBSD: imx6_gpio.c,v 1.2 2017/06/09 18:14:59 ryo Exp $");
#include "opt_imx.h"
@ -73,9 +73,13 @@ imxgpio_match(device_t parent, cfdata_t cfdata, void *aux)
case IMX6_AIPS1_BASE + AIPS1_GPIO3_BASE:
case IMX6_AIPS1_BASE + AIPS1_GPIO4_BASE:
case IMX6_AIPS1_BASE + AIPS1_GPIO5_BASE:
return 1;
case IMX6_AIPS1_BASE + AIPS1_GPIO6_BASE:
case IMX6_AIPS1_BASE + AIPS1_GPIO7_BASE:
return 1;
/* iMX6UL does not have GPIO7 */
if (IMX6_CHIPID_MAJOR(imx6_chip_id()) != CHIPID_MAJOR_IMX6UL)
return 1;
break;
}
return 0;

47
sys/arch/arm/imx/imx6_intr.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_intr.h,v 1.3 2015/06/01 09:49:36 ryo Exp $ */
/* $NetBSD: imx6_intr.h,v 1.4 2017/06/09 18:14:59 ryo Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@ -45,20 +45,29 @@
#define IRQ_DAP 33
#define IRQ_SDMA 34
#define IRQ_VPU_JPEG 35
#define IRQ_TSC 35 /* iMX6UL */
#define IRQ_SNVS_PMIC 36
#define IRQ_IPU1_ERROR 37
#define IRQ_LCDIF_SYNC 37 /* iMX6UL */
#define IRQ_IPU1_SYNC 38
#define IRQ_BEE 38 /* iMX6UL */
#define IRQ_IPU2_ERROR 39
#define IRQ_CSI 39 /* iMX6UL */
#define IRQ_IPU2_SYNC 40
#define IRQ_PXP 40 /* iMX6UL */
#define IRQ_GPU3D 41
#define IRQ_GPU2D_IDLE 42
#define IRQ_SCTR_A 41 /* iMX6UL */
#define IRQ_SCTR_B 42 /* iMX6UL */
#define IRQ_GPU2D 43
#define IRQ_WDOG3 43 /* iMX6UL */
#define IRQ_VPU 44
#define IRQ_APBH 45
#define IRQ_EIM 46
#define IRQ_BCH 47
#define IRQ_GPMI 48
#define IRQ_DTCP 49
#define IRQ_UART6 49 /* iMX6UL */
#define IRQ_VDOA 50
#define IRQ_SNVS 51
#define IRQ_SNVS_SEC 52
@ -67,6 +76,8 @@
#define IRQ_USDHC2 55
#define IRQ_USDHC3 56
#define IRQ_USDHC4 57
#define IRQ_SAI3_A 56 /* iMX6UL */
#define IRQ_SAI3_B 57 /* iMX6UL */
#define IRQ_UART1 58
#define IRQ_UART2 59
#define IRQ_UART3 60
@ -77,26 +88,35 @@
#define IRQ_ECSPI3 65
#define IRQ_ECSPI4 66
#define IRQ_ECSPI5 67
#define IRQ_I2C4 67 /* iMX6UL */
#define IRQ_I2C1 68
#define IRQ_I2C2 69
#define IRQ_I2C3 70
#define IRQ_SATA 71
#define IRQ_UART7 71 /* iMX6UL */
#define IRQ_USB1 72
#define IRQ_UART8 72 /* iMX6UL */
#define IRQ_USB2 73
#define IRQ__RSVD73 73 /* iMX6UL */
#define IRQ_USB3 74
#define IRQ_USBOTG2 74 /* iMX6UL */
#define IRQ_USBOTG 75
#define IRQ_USBOTG1 75 /* iMX6UL */
#define IRQ_USBPHY0 76
#define IRQ_USBPHY1 77
#define IRQ_SSI1 78
#define IRQ_CAAM_JQ2 78 /* iMX6UL */
#define IRQ_SSI2 79
#define IRQ_CAAM_ERR 79 /* iMX6UL */
#define IRQ_SSI3 80
#define IRQ_CAAM_RTIC 80 /* iMX6UL */
#define IRQ_TEMP 81
#define IRQ_ASRC 82
#define IRQ_ESAI 83
#define IRQ_SPDIF 84
#define IRQ_MLB 85
#define IRQ_PMU 86
#define IRQ_GPT 87
#define IRQ_GPT1 87
#define IRQ_EPIT1 88
#define IRQ_EPIT2 89
#define IRQ_GPIO7 90
@ -139,28 +159,41 @@
#define IRQ_CPU_CTI 127
#define IRQ_CPU_WDOG 128
#define IRQ__RSVD129 129
#define IRQ_SAI1 129 /* iMX6UL */
#define IRQ__RSVD130 130
#define IRQ_SAI2 130 /* iMX6UL */
#define IRQ__RSVD131 131
#define IRQ_MIPI_CSI1 132
#define IRQ_ADC1 132 /* iMX6UL */
#define IRQ_MIPI_CSI2 133
#define IRQ_ADC2 133 /* iMX6UL */
#define IRQ_MIPI_DSI 134
#define IRQ__RSVD134 134 /* iMX6UL */
#define IRQ_MIPI_HSI 135
#define IRQ__RSVD135 135 /* iMX6UL */
#define IRQ_SJC 136
#define IRQ_CAAM0 137
#define IRQ_CAAM1 138
#define IRQ__RSVD139 139
#define IRQ_QSPI 139 /* iMX6UL */
#define IRQ_ASC1 140
#define IRQ_ASC2 141
#define IRQ_GPT2 141 /* iMX6UL */
#define IRQ_FLEXCAN1 142
#define IRQ_FLEXCAN2 143
#define IRQ__RSVD144 144
#define IRQ__RSVD145 145
#define IRQ__RSVD146 146
#define IRQ_SIM1 144 /* iMX6UL */
#define IRQ_SIM2 145 /* iMX6UL */
#define IRQ_PWM5 146 /* iMX6UL */
#define IRQ_HDMI_MASTER 147
#define IRQ_PWM6 147 /* iMX6UL */
#define IRQ_HDMI_CEC 148
#define IRQ_PWM7 148 /* iMX6UL */
#define IRQ_MLB150L 149
#define IRQ_ENET 150
#define IRQ_ENET_1588 151
#define IRQ_PWM8 149 /* iMX6UL */
#define IRQ_ENET1 150
#define IRQ_ENET1_1588 151
#define IRQ_ENET2 152 /* iMX6UL */
#define IRQ_ENET2_1588 153 /* iMX6UL */
#define IRQ_PCIE1 152
#define IRQ_PCIE2 153
#define IRQ_PCIE3 154

451
sys/arch/arm/imx/imx6_iomuxreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_iomuxreg.h,v 1.3 2015/12/31 11:53:18 ryo Exp $ */
/* $NetBSD: imx6_iomuxreg.h,v 1.4 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@ -38,7 +38,6 @@
#define IOMUX_GPR1_APP_REQ_ENTR_L1 __BIT(26)
#define IOMUX_GPR1_MIPI_COLOR_SW __BIT(25)
#define IOMUX_GPR1_MIPI_DPI_OFF __BIT(24)
#define IOMUX_GPR1_Reserved __BIT(23
#define IOMUX_GPR1_EXC_MON __BIT(22)
#define IOMUX_GPR1_ENET_CLK_SEL __BIT(21)
#define IOMUX_GPR1_MIPI_IPU2_MUX __BIT(20)
@ -1777,6 +1776,452 @@
#define IMX6SL_IOMUXC_EIM_DTACK_B_SELECT_INPUT 0x00000880
#define IMX6SL_IOMUXC_EIM_WAIT_B_SELECT_INPUT 0x00000884
/* for iMX6UltraLight */
#define IMX6UL_IOMUX_GPR0 0x00004000
#define IMX6UL_IOMUX_GPR1 0x00004004
#define IMX6UL_IOMUX_GPR1_ARMA7_CLK_AHB_EN __BIT(26)
#define IMX6UL_IOMUX_GPR1_ARMA7_CLK_ATB_EN __BIT(25)
#define IMX6UL_IOMUX_GPR1_ARMA7_CLK_APB_DBG_EN __BIT(24)
#define IMX6UL_IOMUX_GPR1_TZASC1_BOOT_LOCK __BIT(23)
#define IMX6UL_IOMUX_GPR1_EXC_MON __BIT(22)
#define IMX6UL_IOMUX_GPR1_SAI3_MCLK_DIR __BIT(21)
#define IMX6UL_IOMUX_GPR1_SAI2_MCLK_DIR __BIT(20)
#define IMX6UL_IOMUX_GPR1_SAI1_MCLK_DIR __BIT(19)
#define IMX6UL_IOMUX_GPR1_ENET2_TX_CLK_DIR __BIT(18)
#define IMX6UL_IOMUX_GPR1_ENET1_TX_CLK_DIR __BIT(17)
#define IMX6UL_IOMUX_GPR1_ADD_DS __BIT(16)
#define IMX6UL_IOMUX_GPR1_USB_EXP_MODE __BIT(15)
#define IMX6UL_IOMUX_GPR1_ENET2_CLK_SEL __BIT(14)
#define IMX6UL_IOMUX_GPR1_ENET1_CLK_SEL __BIT(13)
#define IMX6UL_IOMUX_GPR1_GINT __BIT(12)
#define IMX6UL_IOMUX_GPR2 0x00004008
#define IMX6UL_IOMUX_GPR3 0x0000400c
#define IMX6UL_IOMUX_GPR4 0x00004010
#define IMX6UL_IOMUX_GPR5 0x00004014
#define IMX6UL_IOMUX_GPR9 0x00004024
#define IMX6UL_IOMUX_GPR10 0x00004028
#define IMX6UL_IOMUX_GPR14 0x00004038
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_BOOT_MODE0 0x00000014
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_BOOT_MODE1 0x00000018
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0 0x0000001c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1 0x00000020
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER2 0x00000024
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER3 0x00000028
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER4 0x0000002c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5 0x00000030
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6 0x00000034
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER7 0x00000038
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER8 0x0000003c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER9 0x00000040
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_MOD 0x00000044
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_TMS 0x00000048
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_TDO 0x0000004c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_TDI 0x00000050
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_TCK 0x00000054
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_TRST_B 0x00000058
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 0x0000005c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 0x00000060
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 0x00000064
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 0x00000068
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 0x0000006c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 0x00000070
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 0x00000074
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 0x00000078
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 0x0000007c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 0x00000080
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA 0x00000084
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA 0x00000088
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B 0x0000008c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B 0x00000090
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA 0x00000094
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA 0x00000098
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART2_CTS_B 0x0000009c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART2_RTS_B 0x000000a0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA 0x000000a4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA 0x000000a8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B 0x000000ac
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B 0x000000b0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA 0x000000b4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA 0x000000b8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART5_TX_DATA 0x000000bc
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART5_RX_DATA 0x000000c0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA0 0x000000c4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA1 0x000000c8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_EN 0x000000cc
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA0 0x000000d0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA1 0x000000d4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_EN 0x000000d8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK 0x000000dc
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_ER 0x000000e0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA0 0x000000e4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA1 0x000000e8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_EN 0x000000ec
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA0 0x000000f0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA1 0x000000f4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_EN 0x000000f8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK 0x000000fc
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_ER 0x00000100
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_CLK 0x00000104
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE 0x00000108
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC 0x0000010c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC 0x00000110
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_RESET 0x00000114
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00 0x00000118
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01 0x0000011c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02 0x00000120
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03 0x00000124
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04 0x00000128
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05 0x0000012c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06 0x00000130
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07 0x00000134
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08 0x00000138
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09 0x0000013c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10 0x00000140
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11 0x00000144
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12 0x00000148
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13 0x0000014c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14 0x00000150
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15 0x00000154
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16 0x00000158
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17 0x0000015c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18 0x00000160
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19 0x00000164
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20 0x00000168
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21 0x0000016c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22 0x00000170
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23 0x00000174
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B 0x00000178
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B 0x0000017c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x00000180
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x00000184
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x00000188
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x0000018c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x00000190
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x00000194
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x00000198
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x0000019c
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x000001a0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x000001a4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B 0x000001a8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B 0x000001ac
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B 0x000001b0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x000001b4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DQS 0x000001b8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x000001bc
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x000001c0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x000001c4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x000001c8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x000001cc
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x000001d0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK 0x000001d4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK 0x000001d8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC 0x000001dc
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC 0x000001e0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00 0x000001e4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01 0x000001e8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02 0x000001ec
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03 0x000001f0
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04 0x000001f4
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05 0x000001f8
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06 0x000001fc
#define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07 0x00000200
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x00000204
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x00000208
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x0000020c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x00000210
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x00000214
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x00000218
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x0000021c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x00000220
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x00000224
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x00000228
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x0000022c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x00000230
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x00000234
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x00000238
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x0000023c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x00000240
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x00000244
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x00000248
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B 0x0000024c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B 0x00000250
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x00000254
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x00000258
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x0000025c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x00000260
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x00000264
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x00000268
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x0000026c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x00000270
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x00000274
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x00000278
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x0000027c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x00000280
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x00000284
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x00000288
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_TEST_MODE 0x0000028c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_POR_B 0x00000290
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ONOFF 0x00000294
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_PMIC_ON_REQ 0x00000298
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CCM_PMIC_STBY_REQ 0x0000029c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 0x000002a0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 0x000002a4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0 0x000002a8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1 0x000002ac
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER2 0x000002b0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER3 0x000002b4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER4 0x000002b8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5 0x000002bc
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6 0x000002c0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER7 0x000002c4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER8 0x000002c8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER9 0x000002cc
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x000002d0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x000002d4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x000002d8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x000002dc
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x000002e0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B 0x000002e4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 0x000002e8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 0x000002ec
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 0x000002f0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 0x000002f4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 0x000002f8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 0x000002fc
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 0x00000300
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 0x00000304
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 0x00000308
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 0x0000030c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA 0x00000310
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA 0x00000314
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B 0x00000318
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B 0x0000031c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA 0x00000320
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA 0x00000324
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART2_CTS_B 0x00000328
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART2_RTS_B 0x0000032c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA 0x00000330
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA 0x00000334
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B 0x00000338
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B 0x0000033c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART4_TX_DATA 0x00000340
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART4_RX_DATA 0x00000344
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART5_TX_DATA 0x00000348
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART5_RX_DATA 0x0000034c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA0 0x00000350
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA1 0x00000354
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_EN 0x00000358
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA0 0x0000035c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA1 0x00000360
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_EN 0x00000364
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK 0x00000368
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_ER 0x0000036c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA0 0x00000370
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA1 0x00000374
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_EN 0x00000378
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA0 0x0000037c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA1 0x00000380
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_EN 0x00000384
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK 0x00000388
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_ER 0x0000038c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_CLK 0x00000390
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE 0x00000394
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC 0x00000398
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC 0x0000039c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_RESET 0x000003a0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00 0x000003a4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01 0x000003a8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02 0x000003ac
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03 0x000003b0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04 0x000003b4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05 0x000003b8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06 0x000003bc
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07 0x000003c0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08 0x000003c4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09 0x000003c8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10 0x000003cc
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11 0x000003d0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12 0x000003d4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13 0x000003d8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14 0x000003dc
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15 0x000003e0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16 0x000003e4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17 0x000003e8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18 0x000003ec
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19 0x000003f0
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20 0x000003f4
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21 0x000003f8
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22 0x000003fc
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23 0x00000400
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B 0x00000404
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B 0x00000408
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x0000040c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x00000410
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x00000414
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x00000418
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x0000041c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x00000420
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x00000424
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x00000428
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x0000042c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B 0x00000430
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B 0x00000434
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B 0x00000438
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B 0x0000043c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x00000440
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DQS 0x00000444
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x00000448
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x0000044c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x00000450
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x00000454
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x00000458
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x0000045c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK 0x00000460
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK 0x00000464
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC 0x00000468
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC 0x0000046c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00 0x00000470
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01 0x00000474
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02 0x00000478
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03 0x0000047c
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04 0x00000480
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05 0x00000484
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06 0x00000488
#define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07 0x0000048c
#define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x00000490
#define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x00000494
#define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_B0DS 0x00000498
#define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x0000049c
#define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x000004a0
#define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_B1DS 0x000004a4
#define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x000004a8
#define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x000004ac
#define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x000004b0
#define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x000004b4
#define IMX6UL_IOMUXC_USB_OTG1_ID_SELECT_INPUT 0x000004b8
#define IMX6UL_IOMUXC_USB_OTG2_ID_SELECT_INPUT 0x000004bc
#define IMX6UL_IOMUXC_CCM_PMIC_READY_SELECT_INPUT 0x000004c0
#define IMX6UL_IOMUXC_CSI_DATA02_SELECT_INPUT 0x000004c4
#define IMX6UL_IOMUXC_CSI_DATA03_SELECT_INPUT 0x000004c8
#define IMX6UL_IOMUXC_CSI_DATA05_SELECT_INPUT 0x000004cc
#define IMX6UL_IOMUXC_CSI_DATA00_SELECT_INPUT 0x000004d0
#define IMX6UL_IOMUXC_CSI_DATA01_SELECT_INPUT 0x000004d4
#define IMX6UL_IOMUXC_CSI_DATA04_SELECT_INPUT 0x000004d8
#define IMX6UL_IOMUXC_CSI_DATA06_SELECT_INPUT 0x000004dc
#define IMX6UL_IOMUXC_CSI_DATA07_SELECT_INPUT 0x000004e0
#define IMX6UL_IOMUXC_CSI_DATA08_SELECT_INPUT 0x000004e4
#define IMX6UL_IOMUXC_CSI_DATA09_SELECT_INPUT 0x000004e8
#define IMX6UL_IOMUXC_CSI_DATA10_SELECT_INPUT 0x000004ec
#define IMX6UL_IOMUXC_CSI_DATA11_SELECT_INPUT 0x000004f0
#define IMX6UL_IOMUXC_CSI_DATA12_SELECT_INPUT 0x000004f4
#define IMX6UL_IOMUXC_CSI_DATA13_SELECT_INPUT 0x000004f8
#define IMX6UL_IOMUXC_CSI_DATA14_SELECT_INPUT 0x000004fc
#define IMX6UL_IOMUXC_CSI_DATA15_SELECT_INPUT 0x00000500
#define IMX6UL_IOMUXC_CSI_DATA16_SELECT_INPUT 0x00000504
#define IMX6UL_IOMUXC_CSI_DATA17_SELECT_INPUT 0x00000508
#define IMX6UL_IOMUXC_CSI_DATA18_SELECT_INPUT 0x0000050c
#define IMX6UL_IOMUXC_CSI_DATA19_SELECT_INPUT 0x00000510
#define IMX6UL_IOMUXC_CSI_DATA20_SELECT_INPUT 0x00000514
#define IMX6UL_IOMUXC_CSI_DATA21_SELECT_INPUT 0x00000518
#define IMX6UL_IOMUXC_CSI_DATA22_SELECT_INPUT 0x0000051c
#define IMX6UL_IOMUXC_CSI_DATA23_SELECT_INPUT 0x00000520
#define IMX6UL_IOMUXC_CSI_HSYNC_SELECT_INPUT 0x00000524
#define IMX6UL_IOMUXC_CSI_PIXCLK_SELECT_INPUT 0x00000528
#define IMX6UL_IOMUXC_CSI_VSYNC_SELECT_INPUT 0x0000052c
#define IMX6UL_IOMUXC_CSI_FIELD_SELECT_INPUT 0x00000530
#define IMX6UL_IOMUXC_ECSPI1_SCLK_SELECT_INPUT 0x00000534
#define IMX6UL_IOMUXC_ECSPI1_MISO_SELECT_INPUT 0x00000538
#define IMX6UL_IOMUXC_ECSPI1_MOSI_SELECT_INPUT 0x0000053c
#define IMX6UL_IOMUXC_ECSPI1_SS0_B_SELECT_INPUT 0x00000540
#define IMX6UL_IOMUXC_ECSPI2_SCLK_SELECT_INPUT 0x00000544
#define IMX6UL_IOMUXC_ECSPI2_MISO_SELECT_INPUT 0x00000548
#define IMX6UL_IOMUXC_ECSPI2_MOSI_SELECT_INPUT 0x0000054c
#define IMX6UL_IOMUXC_ECSPI2_SS0_B_SELECT_INPUT 0x00000550
#define IMX6UL_IOMUXC_ECSPI3_SCLK_SELECT_INPUT 0x00000554
#define IMX6UL_IOMUXC_ECSPI3_MISO_SELECT_INPUT 0x00000558
#define IMX6UL_IOMUXC_ECSPI3_MOSI_SELECT_INPUT 0x0000055c
#define IMX6UL_IOMUXC_ECSPI3_SS0_B_SELECT_INPUT 0x00000560
#define IMX6UL_IOMUXC_ECSPI4_SCLK_SELECT_INPUT 0x00000564
#define IMX6UL_IOMUXC_ECSPI4_MISO_SELECT_INPUT 0x00000568
#define IMX6UL_IOMUXC_ECSPI4_MOSI_SELECT_INPUT 0x0000056c
#define IMX6UL_IOMUXC_ECSPI4_SS0_B_SELECT_INPUT 0x00000570
#define IMX6UL_IOMUXC_ENET1_REF_CLK1_SELECT_INPUT 0x00000574
#define IMX6UL_IOMUXC_ENET1_MAC0_MDIO_SELECT_INPUT 0x00000578
#define IMX6UL_IOMUXC_ENET2_REF_CLK2_SELECT_INPUT 0x0000057c
#define IMX6UL_IOMUXC_ENET2_MAC0_MDIO_SELECT_INPUT 0x00000580
#define IMX6UL_IOMUXC_FLEXCAN1_RX_SELECT_INPUT 0x00000584
#define IMX6UL_IOMUXC_FLEXCAN2_RX_SELECT_INPUT 0x00000588
#define IMX6UL_IOMUXC_GPT1_CAPTURE1_SELECT_INPUT 0x0000058c
#define IMX6UL_IOMUXC_GPT1_CAPTURE2_SELECT_INPUT 0x00000590
#define IMX6UL_IOMUXC_GPT1_CLK_SELECT_INPUT 0x00000594
#define IMX6UL_IOMUXC_GPT2_CAPTURE1_SELECT_INPUT 0x00000598
#define IMX6UL_IOMUXC_GPT2_CAPTURE2_SELECT_INPUT 0x0000059c
#define IMX6UL_IOMUXC_GPT2_CLK_SELECT_INPUT 0x000005a0
#define IMX6UL_IOMUXC_I2C1_SCL_SELECT_INPUT 0x000005a4
#define IMX6UL_IOMUXC_I2C1_SDA_SELECT_INPUT 0x000005a8
#define IMX6UL_IOMUXC_I2C2_SCL_SELECT_INPUT 0x000005ac
#define IMX6UL_IOMUXC_I2C2_SDA_SELECT_INPUT 0x000005b0
#define IMX6UL_IOMUXC_I2C3_SCL_SELECT_INPUT 0x000005b4
#define IMX6UL_IOMUXC_I2C3_SDA_SELECT_INPUT 0x000005b8
#define IMX6UL_IOMUXC_I2C4_SCL_SELECT_INPUT 0x000005bc
#define IMX6UL_IOMUXC_I2C4_SDA_SELECT_INPUT 0x000005c0
#define IMX6UL_IOMUXC_KPP_COL0_SELECT_INPUT 0x000005c4
#define IMX6UL_IOMUXC_KPP_COL1_SELECT_INPUT 0x000005c8
#define IMX6UL_IOMUXC_KPP_COL2_SELECT_INPUT 0x000005cc
#define IMX6UL_IOMUXC_KPP_ROW0_SELECT_INPUT 0x000005d0
#define IMX6UL_IOMUXC_KPP_ROW1_SELECT_INPUT 0x000005d4
#define IMX6UL_IOMUXC_KPP_ROW2_SELECT_INPUT 0x000005d8
#define IMX6UL_IOMUXC_LCD_BUSY_SELECT_INPUT 0x000005dc
#define IMX6UL_IOMUXC_SAI1_MCLK_SELECT_INPUT 0x000005e0
#define IMX6UL_IOMUXC_SAI1_RX_DATA_SELECT_INPUT 0x000005e4
#define IMX6UL_IOMUXC_SAI1_TX_BCLK_SELECT_INPUT 0x000005e8
#define IMX6UL_IOMUXC_SAI1_TX_SYNC_SELECT_INPUT 0x000005ec
#define IMX6UL_IOMUXC_SAI2_MCLK_SELECT_INPUT 0x000005f0
#define IMX6UL_IOMUXC_SAI2_RX_DATA_SELECT_INPUT 0x000005f4
#define IMX6UL_IOMUXC_SAI2_TX_BCLK_SELECT_INPUT 0x000005f8
#define IMX6UL_IOMUXC_SAI2_TX_SYNC_SELECT_INPUT 0x000005fc
#define IMX6UL_IOMUXC_SAI3_MCLK_SELECT_INPUT 0x00000600
#define IMX6UL_IOMUXC_SAI3_RX_DATA_SELECT_INPUT 0x00000604
#define IMX6UL_IOMUXC_SAI3_TX_BCLK_SELECT_INPUT 0x00000608
#define IMX6UL_IOMUXC_SAI3_TX_SYNC_SELECT_INPUT 0x0000060c
#define IMX6UL_IOMUXC_SDMA_EVENTS0_SELECT_INPUT 0x00000610
#define IMX6UL_IOMUXC_SDMA_EVENTS1_SELECT_INPUT 0x00000614
#define IMX6UL_IOMUXC_SPDIF_IN_SELECT_INPUT 0x00000618
#define IMX6UL_IOMUXC_SPDIF_EXT_CLK_SELECT_INPUT 0x0000061c
#define IMX6UL_IOMUXC_UART1_RTS_B_SELECT_INPUT 0x00000620
#define IMX6UL_IOMUXC_UART1_RX_DATA_SELECT_INPUT 0x00000624
#define IMX6UL_IOMUXC_UART2_RTS_B_SELECT_INPUT 0x00000628
#define IMX6UL_IOMUXC_UART2_RX_DATA_SELECT_INPUT 0x0000062c
#define IMX6UL_IOMUXC_UART3_RTS_B_SELECT_INPUT 0x00000630
#define IMX6UL_IOMUXC_UART3_RX_DATA_SELECT_INPUT 0x00000634
#define IMX6UL_IOMUXC_UART4_RTS_B_SELECT_INPUT 0x00000638
#define IMX6UL_IOMUXC_UART4_RX_DATA_SELECT_INPUT 0x0000063c
#define IMX6UL_IOMUXC_UART5_RTS_B_SELECT_INPUT 0x00000640
#define IMX6UL_IOMUXC_UART5_RX_DATA_SELECT_INPUT 0x00000644
#define IMX6UL_IOMUXC_UART6_RTS_B_SELECT_INPUT 0x00000648
#define IMX6UL_IOMUXC_UART6_RX_DATA_SELECT_INPUT 0x0000064c
#define IMX6UL_IOMUXC_UART7_RTS_B_SELECT_INPUT 0x00000650
#define IMX6UL_IOMUXC_UART7_RX_DATA_SELECT_INPUT 0x00000654
#define IMX6UL_IOMUXC_UART8_RTS_B_SELECT_INPUT 0x00000658
#define IMX6UL_IOMUXC_UART8_RX_DATA_SELECT_INPUT 0x0000065c
#define IMX6UL_IOMUXC_USB_OTG2_OC_SELECT_INPUT 0x00000660
#define IMX6UL_IOMUXC_USB_OTG_OC_SELECT_INPUT 0x00000664
#define IMX6UL_IOMUXC_USDHC1_CD_B_SELECT_INPUT 0x00000668
#define IMX6UL_IOMUXC_USDHC1_WP_SELECT_INPUT 0x0000066c
#define IMX6UL_IOMUXC_USDHC2_CLK_SELECT_INPUT 0x00000670
#define IMX6UL_IOMUXC_USDHC2_CD_B_SELECT_INPUT 0x00000674
#define IMX6UL_IOMUXC_USDHC2_CMD_SELECT_INPUT 0x00000678
#define IMX6UL_IOMUXC_USDHC2_DATA0_SELECT_INPUT 0x0000067c
#define IMX6UL_IOMUXC_USDHC2_DATA1_SELECT_INPUT 0x00000680
#define IMX6UL_IOMUXC_USDHC2_DATA2_SELECT_INPUT 0x00000684
#define IMX6UL_IOMUXC_USDHC2_DATA3_SELECT_INPUT 0x00000688
#define IMX6UL_IOMUXC_USDHC2_DATA4_SELECT_INPUT 0x0000068c
#define IMX6UL_IOMUXC_USDHC2_DATA5_SELECT_INPUT 0x00000690
#define IMX6UL_IOMUXC_USDHC2_DATA6_SELECT_INPUT 0x00000694
#define IMX6UL_IOMUXC_USDHC2_DATA7_SELECT_INPUT 0x00000698
#define IMX6UL_IOMUXC_USDHC2_WP_SELECT_INPUT 0x0000069c
/* IOMUXC_SW_MUX_CTL_PAD_xxx */
#define IOMUX_CONFIG_SION __BIT(4)
#define IOMUX_CONFIG_ALT0 0
@ -1806,7 +2251,7 @@
#define PAD_CTL_ODE __BIT(11)
#define PAD_CTL_ODT __BITS(10, 8)
#define PAD_CTL_SPEED_MASK __BITS(7, 6)
#define PAD_CTL_SPEED_RESERVED0 __SHIFTIN(0, PAD_CTL_SPEED_MASK)
#define PAD_CTL_SPEED_LOW50MHZ __SHIFTIN(0, PAD_CTL_SPEED_MASK)
#define PAD_CTL_SPEED_50MHZ __SHIFTIN(1, PAD_CTL_SPEED_MASK)
#define PAD_CTL_SPEED_100MHZ __SHIFTIN(2, PAD_CTL_SPEED_MASK)
#define PAD_CTL_SPEED_200MHZ __SHIFTIN(3, PAD_CTL_SPEED_MASK)

7
sys/arch/arm/imx/imx6_pcie.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_pcie.c,v 1.2 2016/11/25 05:03:36 hkenken Exp $ */
/* $NetBSD: imx6_pcie.c,v 1.3 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2016 Genetec Corporation. All rights reserved.
@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.2 2016/11/25 05:03:36 hkenken Exp $");
__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.3 2017/06/09 18:14:59 ryo Exp $");
#include "opt_pci.h"
@ -519,9 +519,10 @@ imx6pcie_match(device_t parent, cfdata_t cf, void *aux)
{
struct axi_attach_args * const aa = aux;
/* i.MX6 SoloLite has no PCIe controller */
/* i.MX6 SoloLite/UltraLight has no PCIe controller */
switch (IMX6_CHIPID_MAJOR(imx6_chip_id())) {
case CHIPID_MAJOR_IMX6SL:
case CHIPID_MAJOR_IMX6UL:
return 0;
default:
break;

16
sys/arch/arm/imx/imx6_reg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_reg.h,v 1.5 2016/05/17 06:44:45 ryo Exp $ */
/* $NetBSD: imx6_reg.h,v 1.6 2017/06/09 18:14:59 ryo Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@ -48,11 +48,9 @@
#define IMX6_CS0_BASE 0x08000000
#define IMX6_CS0_SIZE 0x08000000
#define IMX6_IPU2_BASE 0x02c00000
#define IMX6_IPU2_SIZE 0x00400000
#define IMX6_IPU1_BASE 0x02800000
#define IMX6_IPU1_SIZE 0x00400000
#define IMX6_IPU2_BASE 0x02a00000
#define IMX6_IPU1_BASE 0x02600000
#define IMX6_IPU_SIZE 0x00400000
#define IMX6_HSI_BASE 0x02208000
#define IMX6_HSI_SIZE 0x00004000
@ -133,7 +131,7 @@
#define AIPS1_DCIC2_BASE 0x000e8000
#define AIPS1_DCIC1_BASE 0x000e4000
#define AIPS1_IOMUXC_BASE 0x000e0000
#define AIPS1_IOMUXC_SIZE 0x00001000
#define AIPS1_IOMUXC_SIZE 0x00005000
#define AIPS1_GPC_BASE 0x000dc000
#define AIPS1_SRC_BASE 0x000d8000
#define AIPS1_EPIT2_BASE 0x000d4000
@ -149,6 +147,7 @@
#define AIPS1_WDOG1_BASE 0x000bc000
#define AIPS1_WDOG_SIZE 0x00000010
#define AIPS1_KPP_BASE 0x000b8000
#define AIPS1_ENET2_BASE 0x000b4000 /* iMX6UL */
#define AIPS1_GPIO7_BASE 0x000b4000
#define AIPS1_GPIO6_BASE 0x000b0000
#define AIPS1_GPIO5_BASE 0x000ac000
@ -173,6 +172,7 @@
#define AIPS1_SSI1_BASE 0x00028000
#define AIPS1_ESAI_BASE 0x00024000
#define AIPS1_UART1_BASE 0x00020000
#define AIPS1_UART7_BASE 0x00018000 /* iMX6UL */
#define AIPS1_ECSPI5_BASE 0x00018000
#define AIPS1_ECSPI4_BASE 0x00014000
#define AIPS1_ECSPI3_BASE 0x00010000
@ -180,10 +180,12 @@
#define AIPS1_ECSPI1_BASE 0x00008000
#define AIPS1_SPDIF_BASE 0x00004000
#define AIPS2_UART6_BASE 0x000fc000 /* iMX6UL */
#define AIPS2_UART5_BASE 0x000f4000
#define AIPS2_UART4_BASE 0x000f0000
#define AIPS2_UART3_BASE 0x000ec000
#define AIPS2_UART2_BASE 0x000e8000
#define AIPS2_WDOG3_BASE 0x000e4000 /* iMX6UL */
#define AIPS2_VDOA_BASE 0x000e3000
#define AIPS2_MIPIDSI_BASE 0x000e0000
#define AIPS2_MIPICSI_BASE 0x000dc000

7
sys/arch/arm/imx/imx6_uart.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_uart.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/* $NetBSD: imx6_uart.c,v 1.2 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2013 Genetec Corporation. All rights reserved.
@ -47,6 +47,11 @@ imxuart_match(device_t parent, struct cfdata *cf, void *aux)
case (IMX6_AIPS2_BASE + AIPS2_UART4_BASE):
case (IMX6_AIPS2_BASE + AIPS2_UART5_BASE):
return 1;
case (IMX6_AIPS2_BASE + AIPS2_UART6_BASE):
case (IMX6_AIPS1_BASE + AIPS1_UART7_BASE):
if (IMX6_CHIPID_MAJOR(imx6_chip_id()) == CHIPID_MAJOR_IMX6UL)
return 1;
break;
}
return 0;

11
sys/arch/arm/imx/imx6_usdhc.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_usdhc.c,v 1.3 2016/11/24 08:41:20 hkenken Exp $ */
/* $NetBSD: imx6_usdhc.c,v 1.4 2017/06/09 18:14:59 ryo Exp $ */
/*-
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
@ -30,7 +30,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_usdhc.c,v 1.3 2016/11/24 08:41:20 hkenken Exp $");
__KERNEL_RCSID(0, "$NetBSD: imx6_usdhc.c,v 1.4 2017/06/09 18:14:59 ryo Exp $");
#include "imxgpio.h"
@ -78,8 +78,11 @@ sdhc_match(device_t parent, cfdata_t cf, void *aux)
switch (aa->aa_addr) {
case IMX6_AIPS2_BASE + AIPS2_USDHC1_BASE:
case IMX6_AIPS2_BASE + AIPS2_USDHC2_BASE:
return 1;
case IMX6_AIPS2_BASE + AIPS2_USDHC3_BASE:
case IMX6_AIPS2_BASE + AIPS2_USDHC4_BASE:
if (IMX6_CHIPID_MAJOR(imx6_chip_id()) == CHIPID_MAJOR_IMX6UL)
break;
return 1;
}
@ -89,11 +92,11 @@ sdhc_match(device_t parent, cfdata_t cf, void *aux)
static int
imx6_sdhc_card_detect(struct sdhc_softc *ssc)
{
struct sdhc_axi_softc *sc;
int detect;
#if NIMXGPIO > 0
struct sdhc_axi_softc *sc;
sc = device_private(ssc->sc_dev);
#if NIMXGPIO > 0
if (sc->sc_gpio_cd >= 0) {
detect = gpio_data_read(sc->sc_gpio_cd);
if (sc->sc_gpio_cd_active == GPIO_PIN_LOW)

10
sys/arch/arm/imx/imx6_wdog.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_wdog.c,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/* $NetBSD: imx6_wdog.c,v 1.2 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2010 Genetec Corporation. All rights reserved.
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_wdog.c,v 1.1 2014/09/25 05:05:28 ryo Exp $");
__KERNEL_RCSID(0, "$NetBSD: imx6_wdog.c,v 1.2 2017/06/09 18:14:59 ryo Exp $");
#include "opt_imx.h"
@ -48,9 +48,13 @@ wdog_match(device_t parent, struct cfdata *cf, void *aux)
case IMX6_AIPS1_BASE + AIPS1_WDOG1_BASE:
case IMX6_AIPS1_BASE + AIPS1_WDOG2_BASE:
return 1;
case IMX6_AIPS2_BASE + AIPS2_WDOG3_BASE:
if (IMX6_CHIPID_MAJOR(imx6_chip_id()) == CHIPID_MAJOR_IMX6UL)
return 1;
break;
}
return (0);
return 0;
}
void

7
sys/arch/arm/imx/imx6var.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6var.h,v 1.5 2016/11/24 08:41:20 hkenken Exp $ */
/* $NetBSD: imx6var.h,v 1.6 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@ -50,8 +50,8 @@ extern bus_space_handle_t imx6_armcore_bsh;
struct iomux_conf {
uint32_t pin; /* ((MUXADDR<<16)|PADADDR) */
#define IOMUX_CONF_EOT ((uint32_t)(-1))
uint32_t mux:8,
pad:24;
uint32_t mux;
uint32_t pad;
};
uint32_t iomux_read(uint32_t);
@ -76,6 +76,7 @@ uint32_t imx6_chip_id(void);
#define CHIPID_MAJOR_IMX6DL 0x00610000
#define CHIPID_MAJOR_IMX6SOLO 0x00620000
#define CHIPID_MAJOR_IMX6Q 0x00630000
#define CHIPID_MAJOR_IMX6UL 0x00640000
#define IMX6_CHIPID_MAJOR(v) ((v) & CHIPID_MAJOR_MASK)
#define IMX6_CHIPID_MINOR(v) ((v) & CHIPID_MINOR_MASK)

434
sys/arch/evbarm/conf/IMX6UL-STARTER Normal file
View File

@ -0,0 +1,434 @@
# $NetBSD: IMX6UL-STARTER,v 1.1 2017/06/09 18:14:59 ryo Exp $
#
# IMX6UL-STARTER - Freescale i.MX6UL Evaluation Board
#
# ConnectCore i.MX6UL Starter Kit
# - https://www.digikey.com/en/product-highlight/d/digi-intl/i-mx6ul-starter-kit
#
include "arch/evbarm/conf/std.imx6ul"
#options INCLUDE_CONFIG_FILE # embed config file in kernel binary
# estimated number of users
maxusers 32
# Board Type
options EVBARM_BOARDTYPE=ccimx6ulstarter
# CPU options
options CPU_CORTEX
options CPU_CORTEXA7
options IMX6
options PMAPCOUNTERS
# Standard system options
options INSECURE # disable kernel security levels - X needs this
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
options KTRACE # system call tracing via ktrace(1)
# Note: SysV IPC parameters can be changed dynamically; see sysctl(8).
options SYSVMSG # System V-like message queues
options SYSVSEM # System V-like semaphores
options SYSVSHM # System V-like memory sharing
#options USERCONF # userconf(4) support
#options PIPE_SOCKETPAIR # smaller, but slower pipe(2)
options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel
# Alternate buffer queue strategies for better responsiveness under high
# disk I/O load.
#options BUFQ_READPRIO
options BUFQ_PRIOCSCAN
# Diagnostic/debugging support options
options VERBOSE_INIT_ARM # verbose bootstraping messages
#options PERFCTRS # performance counters
options DIAGNOSTIC # internally consistency checks
#options DEBUG
#options PMAP_DEBUG # Enable pmap_debug_level code
options LOCKDEBUG # expensive locking checks/support
options IRQSTATS # manage IRQ statistics
#options NO_POWERSAVE # uncomment this to run under ICE
#makeoptions COPTS="-O2"
options DDB # in-kernel debugger
#options DDB_KEYCODE=0x1d # ^]
#options DDB_COMMANDONENTER="bt" # execute command when ddb is entered
options DDB_ONPANIC=1 # see also sysctl(7): `ddb.onpanic'
options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
options DDB_VERBOSE_HELP
#options IPKDB # remote kernel debugging
#options KGDB
#options KGDB_DEVNAME="\"imxuart\""
#options KGDB_DEVADDR=0x021f4000
#options KGDB_DEVRATE=115200
makeoptions DEBUG="-g" # compile full symbol table
makeoptions COPY_SYMTAB=1
#options SYSCALL_STATS # per syscall counts
#options SYSCALL_TIMES # per syscall times
#options SYSCALL_TIMES_HASCOUNTER # use 'broken' rdtsc (soekris)
# Compatibility options
#options COMPAT_43 # 4.3BSD compatibility.
#options COMPAT_09 # NetBSD 0.9,
#options COMPAT_10 # NetBSD 1.0,
#options COMPAT_11 # NetBSD 1.1,
#options COMPAT_12 # NetBSD 1.2,
#options COMPAT_13 # NetBSD 1.3,
#options COMPAT_14 # NetBSD 1.4,
#options COMPAT_15 # NetBSD 1.5,
#options COMPAT_16 # NetBSD 1.6,
#options COMPAT_20 # NetBSD 2.0,
#options COMPAT_30 # NetBSD 3.0,
#options COMPAT_40 # NetBSD 4.0,
#options COMPAT_50 # NetBSD 5.0,
options COMPAT_60 # NetBSD 6.0, and
options COMPAT_70 # NetBSD 7.0 binary compatibility.
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
options COMPAT_OSSAUDIO # OSS (Voxware) audio driver compatibility
options COMPAT_NETBSD32 # allow running arm (e.g. non-earm) binaries
options COMPAT_BSDPTY # /dev/[pt]ty?? ptys.
# Wedge support
options DKWEDGE_AUTODISCOVER # Automatically add dk(4) instances
options DKWEDGE_METHOD_GPT # Supports GPT partitions as wedges
#options DKWEDGE_METHOD_BSDLABEL # Support disklabel entries as wedges
#options DKWEDGE_METHOD_MBR # Support MBR partitions as wedges
# File systems
file-system FFS # UFS
file-system MFS # memory file system
file-system NFS # Network File System client
file-system TMPFS # Efficient memory file-system
file-system EXT2FS # second extended file system (linux)
file-system LFS # log-structured file system
file-system NTFS # Windows/NT file system (experimental)
file-system CD9660 # ISO 9660 + Rock Ridge file system
file-system MSDOSFS # MS-DOS file system
file-system FDESC # /dev/fd
file-system KERNFS # /kern
file-system NULLFS # loopback file system
file-system OVERLAY # overlay file system
file-system PROCFS # /proc
file-system PUFFS # Userspace file systems (e.g. ntfs-3g & sshfs)
file-system SMBFS # experimental - CIFS; also needs nsmb (below)
file-system UMAPFS # NULLFS + uid and gid remapping
file-system UNION # union file system
file-system CODA # Coda File System; also needs vcoda (below)
file-system PTYFS # /dev/ptm support
#file-system UDF # experimental - OSTA UDF CD/DVD file-system
#file-system HFS # experimental - Apple HFS+ (read-only)
#file-system NILFS # experimental - NTT's NiLFS(2)
# File system options
options QUOTA # legacy UFS quotas
options QUOTA2 # new, in-filesystem UFS quotas
options FFS_EI # FFS Endian Independent support
options WAPBL # File system journaling support
# Note that UFS_DIRHASH is suspected of causing kernel memory corruption.
# It is not recommended for general use.
#options UFS_DIRHASH # UFS Large Directory Hashing - Experimental
options NFSSERVER # Network File System server
#options EXT2FS_SYSTEM_FLAGS # makes ext2fs file flags (append and
# immutable) behave as system flags.
#options FFS_NO_SNAPSHOT # No FFS snapshot support
options UFS_EXTATTR # Extended attribute support for UFS1
# Networking options
#options GATEWAY # packet forwarding
options INET # IP + ICMP + TCP + UDP
options INET6 # IPv6
options IPSEC # IP security
#options IPSEC_DEBUG # debug for IP security
#options MPLS # MultiProtocol Label Switching (needs mpls)
#options MROUTING # IP multicast routing
#options PIM # Protocol Independent Multicast
options NETATALK # AppleTalk networking protocols
#options CAN # Controller Area Network protocol
options PPP_BSDCOMP # BSD-Compress compression support for PPP
options PPP_DEFLATE # Deflate compression support for PPP
options PPP_FILTER # Active filter support for PPP (requires bpf)
options IPFILTER_LOG # ipmon(8) log support
options IPFILTER_LOOKUP # ippool(8) support
options IPFILTER_COMPAT # Compat for IP-Filter
#options IPFILTER_DEFAULT_BLOCK # block all packets by default
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
#options TCP_SIGNATURE # Enable RFC-2385 TCP md5 signatures
#options ALTQ # Manipulate network interfaces' output queues
#options ALTQ_BLUE # Stochastic Fair Blue
#options ALTQ_CBQ # Class-Based Queueing
#options ALTQ_CDNR # Diffserv Traffic Conditioner
#options ALTQ_FIFOQ # First-In First-Out Queue
#options ALTQ_FLOWVALVE # RED/flow-valve (red-penalty-box)
#options ALTQ_HFSC # Hierarchical Fair Service Curve
#options ALTQ_LOCALQ # Local queueing discipline
#options ALTQ_PRIQ # Priority Queueing
#options ALTQ_RED # Random Early Detection
#options ALTQ_RIO # RED with IN/OUT
#options ALTQ_WFQ # Weighted Fair Queueing
# Device options
# Console options. also need IMXUARTCONSOLE
options CONSDEVNAME="\"imxuart\"",CONADDR=0x021f4000,CONSPEED=115200
options CONS_OVERRIDE
# These options enable verbose messages for several subsystems.
# Warning, these may compile large string tables into the kernel!
options MIIVERBOSE # verbose PHY autoconfig messages
#options PCIVERBOSE # verbose PCI device autoconfig messages
#options PCI_CONFIG_DUMP # verbosely dump PCI config space
#options PCMCIAVERBOSE # verbose PCMCIA configuration messages
#options SCSIVERBOSE # Verbose SCSI errors
#options USBVERBOSE # verbose USB device autoconfig messages
# Kernel root file system and dump configuration.
config netbsd root on ? type ?
options NFS_BOOT_BOOTP
options NFS_BOOT_DHCP
#options NFS_BOOT_BOOTPARAM
#options NFS_BOOT_BOOTSTATIC
#options NFS_BOOTSTATIC_MYIP="\"192.168.0.2\""
#options NFS_BOOTSTATIC_GWIP="\"192.168.0.1\""
#options NFS_BOOTSTATIC_MASK="\"255.255.255.0\""
#options NFS_BOOTSTATIC_SERVADDR="\"192.168.0.3\""
#options NFS_BOOTSTATIC_SERVER="\"192.168.0.3:/nfs/imx6ul\""
#
# Device configuration
#
mainbus0 at root
cpu* at mainbus?
# A7 core devices
armperiph0 at mainbus? # A7 On-Chip Peripherals
armgic0 at armperiph? # ARM Generic Interrupt Controller
armgtmr0 at armperiph? # ARM Generic Timer
axi0 at mainbus?
# Enhanced Periodic Interrupt Timer
#imxclock0 at axi? addr 0x020d0000 irq 88
#imxclock1 at axi? addr 0x020d4000 irq 89
# GPIO
imxgpio0 at axi? addr 0x0209c000 irqbase 256 irq 98
imxgpio1 at axi? addr 0x020a0000 irqbase 288 irq 100
imxgpio2 at axi? addr 0x020a4000 irqbase 320 irq 102
imxgpio3 at axi? addr 0x020a8000 irqbase 352 irq 104
imxgpio4 at axi? addr 0x020ac000 irqbase 384 irq 106
gpio* at imxgpio?
options IMX_GPIO_INTR_SPLIT
# Clock Control
imxccm0 at axi? addr 0x020c4000
# On-Chip OTP Controller
imxocotp0 at axi? addr 0x021bc000
# Secure Non-Volatile Storage
imxsnvs0 at axi? addr 0x020cc000
# IOMUX
imxiomux0 at axi? addr 0x020e0000
# WatchDog
imxwdog0 at axi? addr 0x020bc000 irq 112 flags 0
#imxwdog1 at axi? addr 0x020c0000 irq 113 flags 0
#imxwdog2 at axi? addr 0x021e4000 irq 43 flags 0
# Serial
#imxuart0 at axi? addr 0x02020000 irq 58 # UART1
#imxuart1 at axi? addr 0x021e8000 irq 59 # UART2
#imxuart2 at axi? addr 0x021ec000 irq 60 # UART3
#imxuart3 at axi? addr 0x021f0000 irq 61 # UART4
imxuart4 at axi? addr 0x021f4000 irq 62 # UART5
#imxuart5 at axi? addr 0x021fc000 irq 49 # UART6
#imxuart6 at axi? addr 0x02018000 irq 71 # UART7
options IMXUARTCONSOLE
# Network Interfaces
enet0 at axi? addr 0x02188000 irq 150 # iMX6 SoC Ethernet
#enet1 at axi? addr 0x020b4000 irq 152 # iMX6 SoC Ethernet
# MII/PHY support
acphy* at mii? phy ? # DAltima AC101 and AMD Am79c874 PHYs
amhphy* at mii? phy ? # AMD 79c901 Ethernet PHYs
atphy* at mii? phy ? # Attansic/Atheros PHYs
bmtphy* at mii? phy ? # Broadcom BCM5201 and BCM5202 PHYs
brgphy* at mii? phy ? # Broadcom BCM5400-family PHYs
ciphy* at mii? phy ? # Cicada CS8201 Gig-E PHYs
dmphy* at mii? phy ? # Davicom DM9101 PHYs
etphy* at mii? phy ? # Agere/LSI ET1011 TruePHY Gig-E PHYs
exphy* at mii? phy ? # 3Com internal PHYs
gentbi* at mii? phy ? # Generic Ten-Bit 1000BASE-[CLS]X PHYs
glxtphy* at mii? phy ? # Level One LXT-1000 PHYs
gphyter* at mii? phy ? # NS83861 Gig-E PHY
icsphy* at mii? phy ? # Integrated Circuit Systems ICS189x
igphy* at mii? phy ? # Intel IGP01E1000
ihphy* at mii? phy ? # Intel 82577 PHYs
ikphy* at mii? phy ? # Intel 82563 PHYs
inphy* at mii? phy ? # Intel 82555 PHYs
iophy* at mii? phy ? # Intel 82553 PHYs
lxtphy* at mii? phy ? # Level One LXT-970 PHYs
makphy* at mii? phy ? # Marvell Semiconductor 88E1000 PHYs
micphy* at mii? phy ? # Micrel KSZ9021RNI PHYs
nsphy* at mii? phy ? # NS83840 PHYs
nsphyter* at mii? phy ? # NS83843 PHYs
pnaphy* at mii? phy ? # generic HomePNA PHYs
qsphy* at mii? phy ? # Quality Semiconductor QS6612 PHYs
rgephy* at mii? phy ? # Realtek 8169S/8110 internal PHYs
rlphy* at mii? phy ? # Realtek 8139/8201L PHYs
sqphy* at mii? phy ? # Seeq 80220/80221/80223 PHYs
tlphy* at mii? phy ? # ThunderLAN PHYs
tqphy* at mii? phy ? # TDK Semiconductor PHYs
ukphy* at mii? phy ? # generic unknown PHYs
urlphy* at mii? phy ? # Realtek RTL8150L internal PHYs
# USB Controller and Devices
imxusbc0 at axi? addr 0x02184000
ehci0 at imxusbc0 unit 0 irq 75 # USBOTG1
ehci1 at imxusbc0 unit 1 irq 74 # USBOTG2
usb* at ehci?
# USB device drivers
include "dev/usb/usbdevices.config"
midi* at midibus?
# SD/MMC controller
#sdhc0 at axi? addr 0x02190000 irq 54 # uSDHC1
#sdhc1 at axi? addr 0x02194000 irq 55 # uSDHC2
#sdmmc* at sdhc?
#options SDHC_DEBUG
#options SDMMC_DEBUG
#
#ld* at sdmmc? # MMC/SD card
# Pseudo-Devices
pseudo-device crypto # /dev/crypto device
pseudo-device swcrypto # software crypto implementation
# disk/mass storage pseudo-devices
pseudo-device bio # RAID control device driver
pseudo-device ccd # concatenated/striped disk devices
pseudo-device cgd # cryptographic disk devices
pseudo-device raid # RAIDframe disk driver
#options RAID_AUTOCONFIG # auto-configuration of RAID components
#Options to enable various other RAIDframe RAID types.
#options RF_INCLUDE_EVENODD=1
#options RF_INCLUDE_RAID5_RS=1
#options RF_INCLUDE_PARITYLOGGING=1
#options RF_INCLUDE_CHAINDECLUSTER=1
#options RF_INCLUDE_INTERDECLUSTER=1
#options RF_INCLUDE_PARITY_DECLUSTERING=1
#options RF_INCLUDE_PARITY_DECLUSTERING_DS=1
pseudo-device fss # file system snapshot device
pseudo-device putter # for puffs and pud
pseudo-device vnd # disk-like interface to files
options VND_COMPRESSION # compressed vnd(4)
# network pseudo-devices
pseudo-device bpfilter # Berkeley packet filter
#pseudo-device carp # Common Address Redundancy Protocol
#pseudo-device ipfilter # IP filter (firewall) and NAT
pseudo-device loop # network loopback
#pseudo-device mpls # MPLS pseudo-interface
pseudo-device ppp # Point-to-Point Protocol
pseudo-device pppoe # PPP over Ethernet (RFC 2516)
pseudo-device sl # Serial Line IP
pseudo-device strip # Starmode Radio IP (Metricom)
pseudo-device irframetty # IrDA frame line discipline
pseudo-device tun # network tunneling over tty
pseudo-device tap # virtual Ethernet
pseudo-device gre # generic L3 over IP tunnel
pseudo-device gif # IPv[46] over IPv[46] tunnel (RFC1933)
#pseudo-device faith # IPv[46] tcp relay translation i/f
pseudo-device stf # 6to4 IPv6 over IPv4 encapsulation
pseudo-device vlan # IEEE 802.1q encapsulation
pseudo-device bridge # simple inter-network bridging
#options BRIDGE_IPF # bridge uses IP/IPv6 pfil hooks too
pseudo-device agr # IEEE 802.3ad link aggregation
pseudo-device l2tp # L2TPv3 interface
#pseudo-device pf # PF packet filter
#pseudo-device pflog # PF log if
#pseudo-device pfsync # PF sync if
#pseudo-device npf # NPF packet filter
#pseudo-device canloop # CAN loopback interface
#
# accept filters
pseudo-device accf_data # "dataready" accept filter
pseudo-device accf_http # "httpready" accept filter
# miscellaneous pseudo-devices
pseudo-device pty # pseudo-terminals
pseudo-device sequencer # MIDI sequencer
# rnd works; RND_COM does not on port i386 yet.
#options RND_COM # use "com" randomness as well (BROKEN)
pseudo-device clockctl # user control of clock subsystem
pseudo-device ksyms # /dev/ksyms
pseudo-device lockstat # lock profiling
pseudo-device bcsp # BlueCore Serial Protocol
pseudo-device btuart # Bluetooth HCI UART (H4)
# a pseudo device needed for Coda # also needs CODA (above)
pseudo-device vcoda # coda minicache <-> venus comm.
# a pseudo device needed for SMBFS
pseudo-device nsmb # experimental - SMB requester
# wscons pseudo-devices
pseudo-device wsmux # mouse & keyboard multiplexor
pseudo-device wsfont
# pseudo audio device driver
#pseudo-device pad
# userland interface to drivers, including autoconf and properties retrieval
pseudo-device drvctl
options FILEASSOC # fileassoc(9) - required for Veriexec
# and PAX_SEGVGUARD
# Veriexec
#
# a pseudo device needed for veriexec
pseudo-device veriexec
#
# Uncomment the fingerprint methods below that are desired. Note that
# removing fingerprint methods will have almost no impact on the kernel
# code size.
#
options VERIFIED_EXEC_FP_RMD160
options VERIFIED_EXEC_FP_SHA256
options VERIFIED_EXEC_FP_SHA384
options VERIFIED_EXEC_FP_SHA512
options VERIFIED_EXEC_FP_SHA1
options VERIFIED_EXEC_FP_MD5
options PAX_SEGVGUARD=0 # PaX Segmentation fault guard
options PAX_MPROTECT=1 # PaX mprotect(2) restrictions
options PAX_MPROTECT_DEBUG=1 # PaX mprotect debug
options PAX_ASLR=1 # PaX Address Space Layout Randomization
options PAX_ASLR_DEBUG=1 # PaX ASLR debug

10
sys/arch/evbarm/conf/IMX6UL-STARTER_INSTALL Normal file
View File

@ -0,0 +1,10 @@
# $NetBSD: IMX6UL-STARTER_INSTALL,v 1.1 2017/06/09 18:14:59 ryo Exp $
#
# IMX6UL-STARTER_INSTALL -- IMX6UL-STARTER kernel with installation-sized
# ramdisk
#
include "arch/evbarm/conf/IMX6UL-STARTER"
include "arch/evbarm/conf/INSTALL"
no makeoptions DEBUG
options BOOTHOWTO=RB_SINGLE

33
sys/arch/evbarm/conf/mk.imx6ul Normal file
View File

@ -0,0 +1,33 @@
# $NetBSD: mk.imx6ul,v 1.1 2017/06/09 18:14:59 ryo Exp $
SYSTEM_FIRST_OBJ= nitrogen6_start.o
SYSTEM_FIRST_SFILE= ${THISARM}/nitrogen6/nitrogen6_start.S
GENASSYM_EXTRAS+= ${THISARM}/nitrogen6/genassym.cf
_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
KERNEL_BASE_PHYS?=$(LOADADDRESS)
KERNEL_BASE_VIRT?=$(LOADADDRESS)
MKUBOOTIMAGEARGS= -A arm -T kernel
MKUBOOTIMAGEARGS+= -a $(KERNEL_BASE_PHYS) -e $(KERNEL_BASE_PHYS)
MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
MKUBOOTIMAGEARGS_GZ= ${MKUBOOTIMAGEARGS} -C gz
SYSTEM_LD_TAIL_EXTRA+=; \
echo ${OBJCOPY} -S -O binary $@ $@.bin; \
${OBJCOPY} -S -O binary $@ $@.bin; \
echo ${TOOL_GZIP} -9c $@.bin > $@.bin.gz; \
${TOOL_GZIP} -9c $@.bin > $@.bin.gz; \
echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} $@.bin.gz $@.gz.ub; \
${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} $@.bin.gz $@.gz.ub; \
echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} $@.bin $@.ub; \
${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} $@.bin $@.ub; \
echo
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin@}
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.ub@}
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin.gz@}
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.gz.ub@}

35
sys/arch/evbarm/conf/std.imx6ul Normal file
View File

@ -0,0 +1,35 @@
# $NetBSD: std.imx6ul,v 1.1 2017/06/09 18:14:59 ryo Exp $
#
# standard NetBSD/evbarm options for i.MX6UL
machine evbarm arm
include "arch/evbarm/conf/std.evbarm"
# Pull in nitrogen6 config definitions.
include "arch/evbarm/conf/files.nitrogen6"
options NITROGEN6
options ARM_HAS_VBAR
options __HAVE_CPU_COUNTER
options __HAVE_FAST_SOFTINTS # should be in types.h
options TPIDRPRW_IS_CURCPU
#options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
#options PMAP_NEED_ALLOC_POOLPAGE
makeoptions CPUFLAGS="-mcpu=cortex-a7 -mfpu=neon"
# To support easy transit to ../arch/arm/arm32
options FPU_VFP
options CORTEX_PMC
options CORTEX_PMC_CCNT_HZ=792000000
options KERNEL_BASE_EXT=0x80000000
makeoptions KERNEL_BASE_PHYS="0x80800000"
makeoptions KERNEL_BASE_VIRT="0x80800000"
makeoptions BOARDMKFRAG="${THISARM}/conf/mk.imx6ul"
makeoptions CPPFLAGS+="-I$S/../../../include"
options ARM_INTR_IMPL="<arch/arm/imx/imx6_intr.h>"
options ARM_GENERIC_TODR

107
sys/arch/evbarm/nitrogen6/nitrogen6_iomux.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: nitrogen6_iomux.c,v 1.3 2016/11/24 12:06:44 hkenken Exp $ */
/* $NetBSD: nitrogen6_iomux.c,v 1.4 2017/06/09 18:14:59 ryo Exp $ */
/*
* Copyright (c) 2015 Ryo Shimizu <ryo@nerv.org>
@ -26,7 +26,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: nitrogen6_iomux.c,v 1.3 2016/11/24 12:06:44 hkenken Exp $");
__KERNEL_RCSID(0, "$NetBSD: nitrogen6_iomux.c,v 1.4 2017/06/09 18:14:59 ryo Exp $");
#include "opt_evbarm_boardtype.h"
#include <sys/bus.h>
@ -57,6 +57,7 @@ static void nitrogen6_gpio_config(const struct gpio_conf *);
#define cubox_i 3
#define hummingboard 4
#define hummingboard_edge 5
#define ccimx6ulstarter 6
#define PAD_UART \
(PAD_CTL_HYS | PAD_CTL_PUS_100K_PU | PAD_CTL_PULL | \
@ -112,6 +113,17 @@ static void nitrogen6_gpio_config(const struct gpio_conf *);
PAD_CTL_SPEED_100MHZ | PAD_CTL_DSE_40OHM | PAD_CTL_SRE_SLOW)
#define PAD_OUTPUT_40OHM (PAD_CTL_SPEED_100MHZ | PAD_CTL_DSE_40OHM)
#define PAD_ENET6UL \
(PAD_CTL_PUS_100K_PU | PAD_CTL_PULL | \
PAD_CTL_SPEED_200MHZ | PAD_CTL_DSE_45OHM | PAD_CTL_SRE_FAST)
#define PAD_ENET6UL_REFCLK \
(PAD_CTL_PUS_100K_PD | \
PAD_CTL_SPEED_LOW50MHZ | PAD_CTL_DSE_40OHM | PAD_CTL_SRE_FAST)
#define PAD_LCD_HSYNC \
(PAD_CTL_PUS_100K_PD | PAD_CTL_KEEPER | \
PAD_CTL_SPEED_100MHZ | PAD_CTL_DSE_40OHM | PAD_CTL_SRE_SLOW)
#define PAD_PCIE_GPIO \
(PAD_CTL_HYS | PAD_CTL_PUS_22K_PU | PAD_CTL_PULL | \
PAD_CTL_SPEED_50MHZ | PAD_CTL_DSE_40OHM | PAD_CTL_SRE_FAST)
@ -457,6 +469,71 @@ static const struct iomux_conf iomux_data_6dq[] = {
{.pin = IOMUX_CONF_EOT}
};
/* iMX6 UltraLight */
static const struct iomux_conf iomux_data_6ul[] = {
/* Digi-Key i.MX6UL Starter Kit */
#if (EVBARM_BOARDTYPE == ccimx6ulstarter)
{
.pin = MUX_PIN(IMX6UL, GPIO1_IO07),
.mux = IOMUX_CONFIG_ALT0, /* ENET1_MDC */
.pad = PAD_ENET6UL
},
{
.pin = MUX_PIN(IMX6UL, GPIO1_IO06),
.mux = IOMUX_CONFIG_ALT0, /* ENET1_MDIO */
.pad = PAD_ENET6UL
},
{
.pin = MUX_PIN(IMX6UL, ENET1_RX_EN),
.mux = IOMUX_CONFIG_ALT0, /* ENET1_RX_EN */
.pad = PAD_ENET6UL
},
{
.pin = MUX_PIN(IMX6UL, ENET1_RX_ER),
.mux = IOMUX_CONFIG_ALT0, /* ENET1_RX_ER */
.pad = PAD_ENET6UL
},
{
.pin = MUX_PIN(IMX6UL, ENET1_RX_DATA0),
.mux = IOMUX_CONFIG_ALT0, /* ENET1_RDATA00 */
.pad = PAD_ENET6UL
},
{
.pin = MUX_PIN(IMX6UL, ENET1_RX_DATA1),
.mux = IOMUX_CONFIG_ALT0, /* ENET1_RDATA01 */
.pad = PAD_ENET6UL
},
{
.pin = MUX_PIN(IMX6UL, ENET1_TX_EN),
.mux = IOMUX_CONFIG_ALT0, /* ENET1_TX_EN */
.pad = PAD_ENET6UL
},
{
.pin = MUX_PIN(IMX6UL, ENET1_TX_DATA0),
.mux = IOMUX_CONFIG_ALT0, /* ENET1_TDATA00 */
.pad = PAD_ENET6UL
},
{
.pin = MUX_PIN(IMX6UL, ENET1_TX_DATA1),
.mux = IOMUX_CONFIG_ALT0, /* ENET1_TDATA01 */
.pad = PAD_ENET6UL
},
{
.pin = MUX_PIN(IMX6UL, ENET1_TX_CLK),
.mux = IOMUX_CONFIG_ALT4 | /* ENET1_REF_CLK */
IOMUX_CONFIG_SION, /* Force input ENET1_TX_CLK */
.pad = PAD_ENET6UL_REFCLK
},
{
.pin = MUX_PIN(IMX6UL, LCD_HSYNC),
.mux = IOMUX_CONFIG_ALT5, /* GPIO3_IO02 */
.pad = PAD_LCD_HSYNC
},
#endif
/* end of table */
{.pin = IOMUX_CONF_EOT}
};
static const struct gpio_conf gpio_data[] = {
/* GPIOn, PIN, dir, value */
#if (EVBARM_BOARDTYPE == nitrogen6x)
@ -489,6 +566,9 @@ static const struct gpio_conf gpio_data[] = {
{ 1, 4, GPIO_DIR_IN, 0 }, /* USDHC2 */
{ 2, 11, GPIO_DIR_OUT, 0 }, /* PCIe */
#endif
#if (EVBARM_BOARDTYPE == ccimx6ulstarter)
{ 3, 2, GPIO_DIR_OUT, 1 }, /* ENET1 phy */
#endif
/* end of table */
{ 0, 0, 0, 0 },
@ -497,6 +577,8 @@ static const struct gpio_conf gpio_data[] = {
#define AIPS1_ADDR(addr) \
((volatile uint32_t *)(KERNEL_IO_IOREG_VBASE + (addr)))
#define IOMUX_READ(reg) \
(*AIPS1_ADDR(AIPS1_IOMUXC_BASE + (reg)))
#define IOMUX_WRITE(reg, val) \
(*AIPS1_ADDR(AIPS1_IOMUXC_BASE + (reg)) = (val))
#define GPIO_ADDR(group, reg) \
@ -510,12 +592,20 @@ nitrogen6_mux_config(const struct iomux_conf *conflist)
for (i = 0; conflist[i].pin != IOMUX_CONF_EOT; i++) {
reg = IOMUX_PIN_TO_PAD_ADDRESS(conflist[i].pin);
if (reg != IOMUX_PAD_NONE)
if (reg != IOMUX_PAD_NONE) {
#ifdef IOMUX_DEBUG
printf("IOMUX PAD[%08x] = %08x -> %08x\n", reg, IOMUX_READ(reg), conflist[i].pad);
#endif
IOMUX_WRITE(reg, conflist[i].pad);
}
reg = IOMUX_PIN_TO_MUX_ADDRESS(conflist[i].pin);
if (reg != IOMUX_MUX_NONE)
if (reg != IOMUX_MUX_NONE) {
#ifdef IOMUX_DEBUG
printf("IOMUX MUX[%08x] = %08x -> %08x\n", reg, IOMUX_READ(reg), conflist[i].mux);
#endif
IOMUX_WRITE(reg, conflist[i].mux);
}
}
}
@ -556,8 +646,10 @@ nitrogen6_setup_iomux(void)
case CHIPID_MAJOR_IMX6Q:
nitrogen6_mux_config(iomux_data_6dq);
break;
case CHIPID_MAJOR_IMX6UL:
nitrogen6_mux_config(iomux_data_6ul);
break;
default:
panic("unknown IMX6_CHIPID %08x\n", imx6_chip_id());
break;
}
nitrogen6_gpio_config(gpio_data);
@ -568,6 +660,8 @@ nitrogen6_device_register(device_t self, void *aux)
{
prop_dictionary_t dict = device_properties(self);
(void)&dict;
imx6_device_register(self, aux);
if (device_is_a(self, "sdhc") &&
@ -592,6 +686,9 @@ nitrogen6_device_register(device_t self, void *aux)
}
if (device_is_a(self, "imxpcie") &&
device_is_a(device_parent(self), "axi")) {
#if (EVBARM_BOARDTYPE == nitrogen6max)
prop_dictionary_set_cstring(dict, "imx6pcie-reset-gpio", "!6,31");
#endif
#if (EVBARM_BOARDTYPE == hummingboard)
prop_dictionary_set_cstring(dict, "imx6pcie-reset-gpio", "!3,4");
#endif

13
sys/arch/evbarm/nitrogen6/nitrogen6_start.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: nitrogen6_start.S,v 1.1 2014/09/25 05:05:28 ryo Exp $ */
/* $NetBSD: nitrogen6_start.S,v 1.2 2017/06/09 18:14:59 ryo Exp $ */
/*-
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@ -37,7 +37,7 @@
#include <arm/cortex/scu_reg.h>
#include "assym.h"
RCSID("$NetBSD: nitrogen6_start.S,v 1.1 2014/09/25 05:05:28 ryo Exp $")
RCSID("$NetBSD: nitrogen6_start.S,v 1.2 2017/06/09 18:14:59 ryo Exp $")
#ifndef CONADDR
#define CONADDR 0x021e8000
@ -155,7 +155,7 @@ _C_LABEL(nitrogen6_start):
mov r3, #0 /* flags for arm_cpu_hatched */
cmp r0, #0
ble 9f
ble .hatch_done
#ifdef VERBOSE_INIT_ARM
/* wait to prevent the mixing of console output */
@ -221,10 +221,10 @@ _C_LABEL(nitrogen6_start):
.not_hatched:
PRINT("\r\nnot hatched. arm_cpu_hatched=")
PRINT_R0
b 9f
b .hatch_done
.hatched:
PRINT("\r\nMULTIPROCESSOR hatched!\r\n")
9:
.hatch_done:
#endif
PRINT("jump to start()\r\n")
@ -256,6 +256,9 @@ mmu_init_table:
(BOOT_MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
#endif
MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET,
(BOOT_MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
/* Map the 2MB of primary peripherals (AIPS1 + AIPS2) */
MMU_INIT(KERNEL_IO_IOREG_VBASE, IMX6_IOREG_PBASE,