Add __BITS to asm.h (remove from imxuartreg.h)
Add L1_S_AP_KR to genassym.h Use L1_S_AP_* in omap_start.S and don't include pmap.h
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@ -1,4 +1,4 @@
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# $NetBSD: genassym.cf,v 1.52 2012/08/31 23:59:51 matt Exp $
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# $NetBSD: genassym.cf,v 1.53 2012/09/01 14:46:25 matt Exp $
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# Copyright (c) 1982, 1990 The Regents of the University of California.
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# All rights reserved.
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@ -92,6 +92,7 @@ define L1_S_SHIFT L1_S_SHIFT
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define L1_S_SIZE L1_S_SIZE
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define L1_S_B L1_S_B
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define L1_S_C L1_S_C
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define L1_S_AP_KR L1_S_AP(AP_KR)
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define L1_S_AP_KRW L1_S_AP(AP_KRW)
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define L1_S_APv7_KRW L1_S_AP(AP7_KRW)
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define L1_TABLE_SIZE L1_TABLE_SIZE
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@ -1,4 +1,4 @@
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/* $NetBSD: imxuartreg.h,v 1.4 2010/11/13 06:12:17 bsh Exp $ */
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/* $NetBSD: imxuartreg.h,v 1.5 2012/09/01 14:46:25 matt Exp $ */
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/*
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* register definitions for Freescale i.MX31 and i.MX31L UARTs
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*
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@ -18,13 +18,6 @@
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#ifndef _IMXUARTREG_H
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#define _IMXUARTREG_H
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#ifdef __ASSEMBLER__
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#define __BIT(n) (1<<(n))
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#define __BITS(hi,lo) ((~((~0)<<((hi)+1)))&((~0)<<(lo)))
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#else
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#include <sys/cdefs.h>
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#endif
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/*
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* Registers are 32 bits wide; the 16 MSBs are unused --
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* they read as zeros and are ignored on write.
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@ -1,4 +1,4 @@
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/* $NetBSD: asm.h,v 1.15 2012/08/29 22:25:05 matt Exp $ */
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/* $NetBSD: asm.h,v 1.16 2012/09/01 14:46:25 matt Exp $ */
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/*
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* Copyright (c) 1990 The Regents of the University of California.
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@ -40,6 +40,7 @@
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#include <arm/cdefs.h>
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#define __BIT(n) (1 << (n))
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#define __BITS(hi,lo) ((~((~0)<<((hi)+1)))&((~0)<<(lo)))
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#define _C_LABEL(x) x
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#define _ASM_LABEL(x) x
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@ -1,4 +1,4 @@
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/* $NetBSD: omap_start.S,v 1.4 2011/06/30 20:09:20 wiz Exp $ */
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/* $NetBSD: omap_start.S,v 1.5 2012/09/01 14:46:25 matt Exp $ */
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/*
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* Machine dependent startup code for OMAP boards.
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@ -88,8 +88,6 @@
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#include <machine/asm.h>
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#include <arm/armreg.h>
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#undef DOMAIN_CLIENT /* assym.h defines as 1, but pte.h defines as 0x01 */
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#include <arm/arm32/pmap.h>
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#include <arm/omap/omap_reg.h>
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/*
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@ -228,14 +226,14 @@ mmu_init_table:
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/* Map SDRAM where we're executing from VA==PA, read-only */
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MMU_INIT(KERNEL_BASE_phys, KERNEL_BASE_phys,
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1,
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L1_S_PROTO | L1_S_AP(AP_KR))
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L1_S_PROTO | L1_S_AP_KR)
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/* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable */
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MMU_INIT(KERNEL_BASE, KERNEL_BASE_phys,
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(MEMSIZE_BYTES + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_AP(AP_KRW) | L1_S_B | L1_S_C)
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L1_S_PROTO | L1_S_AP_KRW | L1_S_B | L1_S_C)
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/* Map TIPB VA==PA so peripherals will work. */
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MMU_INIT(OMAP_TIPB_PBASE, OMAP_TIPB_PBASE,
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(OMAP_TIPB_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_AP(AP_KRW))
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L1_S_PROTO | L1_S_AP_KRW)
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/* end of table */
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MMU_INIT(0, 0, 0, 0)
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