Oops, replace this with a (very) slightly modified version of prep's
intr.h instead of a remnant of my original hacking where it was based on sandpoint's.
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scw
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bd9412df1c
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@ -1,7 +1,7 @@
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/* $NetBSD: intr.h,v 1.1 2002/02/27 21:02:16 scw Exp $ */
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/* $NetBSD: intr.h,v 1.2 2002/02/28 00:27:38 scw Exp $ */
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/*-
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* Copyright (c) 1998, 2002 The NetBSD Foundation, Inc.
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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@ -35,37 +35,6 @@
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Sandpoint-specific code developed
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* by Allen Briggs for Wasabi Systems, Inc.
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*
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* OpenPIC code derived from code with the following notice.
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*/
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/*-
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* Copyright (c) 2000 Tsubai Masanari. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MVMEPPC_INTR_H_
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#define _MVMEPPC_INTR_H_
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@ -106,45 +75,51 @@ struct intrhand {
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int ih_irq;
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};
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void setsoftclock(void);
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void clearsoftclock(void);
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int splsoftclock(void);
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void setsoftnet(void);
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void clearsoftnet(void);
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int splsoftnet(void);
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void softnet(void);
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void setsoftclock(void);
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void clearsoftclock(void);
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int splsoftclock(void);
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void setsoftnet(void);
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void clearsoftnet(void);
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int splsoftnet(void);
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void ext_intr(void);
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void do_pending_int(void);
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void do_pending_int(void);
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void *intr_establish(int, int, int, int (*)(void *), void *);
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void intr_disestablish(void *);
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void ext_intr(void);
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void ext_intr_ivr(void);
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void enable_intr(void);
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void disable_intr(void);
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void *intr_establish(int, int, int, int (*)(void *), void *);
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void intr_disestablish(void *);
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void softnet(void);
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void softserial(void);
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int isa_intr(void);
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void isa_intr_mask(int);
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void isa_intr_clr(int);
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void isa_setirqstat(int, int, int);
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extern volatile int cpl, ipending, astpending, tickspending;
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extern int imask[];
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extern long intrcnt[];
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extern int intrtype[];
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extern struct intrhand *intrhand[];
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static __inline int splraise(int);
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static __inline int spllower(int);
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static __inline void splx(int);
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static __inline void spllower(int);
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static __inline void set_sint(int);
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extern volatile int cpl, ipending, astpending, tickspending;
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extern int imen;
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extern int imask[];
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extern long intrcnt[];
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extern unsigned intrcnt2[];
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extern struct intrhand *intrhand[];
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extern int intrtype[];
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extern vaddr_t mvmeppc_intr_reg;
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/*
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* Reorder protection in the following inline functions is
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* protected with the "eieio" instruction.
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* Reorder protection in the following inline functions is
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* achieved with the "eieio" instruction which the assembler
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* seems to detect and then doesn't move instructions past....
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*/
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static __inline int
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splraise(newcpl)
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int newcpl;
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splraise(int newcpl)
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{
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int oldcpl;
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@ -156,9 +131,9 @@ splraise(newcpl)
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}
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static __inline void
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splx(newcpl)
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int newcpl;
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spllower(int newcpl)
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{
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__asm__ volatile("sync; eieio\n"); /* reorder protect */
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cpl = newcpl;
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if(ipending & ~newcpl)
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@ -166,26 +141,10 @@ splx(newcpl)
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__asm__ volatile("sync; eieio\n"); /* reorder protect */
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}
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static __inline int
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spllower(newcpl)
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int newcpl;
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{
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int oldcpl;
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__asm__ volatile("sync; eieio\n"); /* reorder protect */
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oldcpl = cpl;
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cpl = newcpl;
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if(ipending & ~newcpl)
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do_pending_int();
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__asm__ volatile("sync; eieio\n"); /* reorder protect */
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return(oldcpl);
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}
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/* Following code should be implemented with lwarx/stwcx to avoid
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* the disable/enable. i need to read the manual once more.... */
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static __inline void
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set_sint(pending)
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int pending;
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set_sint(int pending)
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{
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int msrsave;
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@ -213,29 +172,30 @@ set_sint(pending)
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#define CNT_SINT_SERIAL 31
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#define CNT_CLOCK 0
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#define spl0() spllower(0)
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#define splbio() splraise(imask[IPL_BIO])
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#define splnet() splraise(imask[IPL_NET])
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#define spltty() splraise(imask[IPL_TTY])
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#define spllpt() spltty()
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#define splclock() splraise(imask[IPL_CLOCK])
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#define splvm() splraise(imask[IPL_IMP])
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#define splaudio() splraise(imask[IPL_AUDIO])
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#define splserial() splraise(imask[IPL_SERIAL])
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#define splstatclock() splclock()
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#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
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#define splsoftclock() splraise(imask[IPL_SOFTCLOCK])
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#define splsoftnet() splraise(imask[IPL_SOFTNET])
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#define splsoftserial() splraise(imask[IPL_SOFTSERIAL])
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#define splhigh() splraise(imask[IPL_HIGH])
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#define splsched() splhigh()
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#define spllock() splhigh()
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#if 1
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#define setsoftisa() set_sint(SINT_ISA);
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#define spllpt() spltty()
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#define setsoftclock() set_sint(SINT_CLOCK);
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#define setsoftnet() set_sint(SINT_NET);
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#define setsoftserial() set_sint(SINT_SERIAL);
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#endif
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#define splhigh() splraise(imask[IPL_HIGH])
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#define splsched() splhigh()
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#define spllock() splhigh()
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#define splx(x) spllower(x)
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#define spl0() spllower(0)
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#endif /* !_LOCORE */
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