add support for (ancient) Mach64 CX and GX, while there make sure the visible
vram area starts at the same offset as the area we're going to draw into - zero that is. from David Riley
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macallan
parent
9e66d3e091
commit
bcb7f01345
@ -1,4 +1,4 @@
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/* $NetBSD: machfb.c,v 1.63 2011/01/22 15:14:28 cegger Exp $ */
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/* $NetBSD: machfb.c,v 1.64 2011/05/04 23:36:21 macallan Exp $ */
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/*
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* Copyright (c) 2002 Bang Jun-Young
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@ -34,7 +34,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0,
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"$NetBSD: machfb.c,v 1.63 2011/01/22 15:14:28 cegger Exp $");
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"$NetBSD: machfb.c,v 1.64 2011/05/04 23:36:21 macallan Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -169,6 +169,8 @@ static struct {
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uint16_t chip_id;
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uint32_t ramdac_freq;
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} const mach64_info[] = {
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{ PCI_PRODUCT_ATI_MACH64_GX, 135000 },
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{ PCI_PRODUCT_ATI_MACH64_CX, 135000 },
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{ PCI_PRODUCT_ATI_MACH64_CT, 135000 },
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{ PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 },
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{ PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 },
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@ -184,12 +186,11 @@ static struct {
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{ PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 },
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{ PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 },
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#if 0
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{ PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 },
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{ PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 },
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{ PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 },
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{ PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 },
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{ PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 },
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#endif
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{ PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 },
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{ PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 },
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{ PCI_PRODUCT_ATI_RAGE_LT, 230000 },
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{ PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 },
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@ -201,6 +202,11 @@ static struct {
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static int mach64_chip_id, mach64_chip_rev;
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static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
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static const char *mach64_gx_memtype_names[] = {
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"DRAM", "VRAM", "VRAM", "DRAM",
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"DRAM", "VRAM", "VRAM", "(unknown type)"
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};
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static const char *mach64_memtype_names[] = {
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"(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM",
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"(unknown type)"
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@ -507,7 +513,9 @@ mach64_attach(device_t parent, device_t self, void *aux)
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prop_data_t edid_data;
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const struct videomode *mode = NULL;
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char devinfo[256];
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int bar, id;
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int bar, id, expected_id;
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int is_gx;
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const char **memtype_names;
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struct wsemuldisplaydev_attach_args aa;
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long defattr;
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int setmode, width, height;
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@ -566,6 +574,13 @@ mach64_attach(device_t parent, device_t self, void *aux)
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}
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sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh);
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/* If the BAR was never mapped, fix it up in MMIO. */
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if(sc->sc_regsize == 0) {
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sc->sc_regsize = MACH64_REG_SIZE;
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sc->sc_regbase = sc->sc_aperbase + MACH64_REG_OFF;
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sc->sc_regphys = sc->sc_aperphys + MACH64_REG_OFF;
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}
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sc->sc_regt = sc->sc_memt;
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bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF,
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sc->sc_regsize, &sc->sc_regh);
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@ -608,19 +623,36 @@ mach64_attach(device_t parent, device_t self, void *aux)
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printf("mode: %s\n", mode->name);
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}
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}
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if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT ||
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((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT ||
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mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) &&
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(mach64_chip_rev & 0x07) == 0))
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sc->has_dsp = 0;
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else
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sc->has_dsp = 1;
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is_gx = 0;
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switch(mach64_chip_id) {
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case PCI_PRODUCT_ATI_MACH64_GX:
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case PCI_PRODUCT_ATI_MACH64_CX:
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is_gx = 1;
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case PCI_PRODUCT_ATI_MACH64_CT:
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sc->has_dsp = 0;
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break;
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case PCI_PRODUCT_ATI_MACH64_VT:
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case PCI_PRODUCT_ATI_RAGE_II:
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if((mach64_chip_rev & 0x07) == 0) {
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sc->has_dsp = 0;
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break;
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}
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/* Otherwise fall through. */
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default:
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sc->has_dsp = 1;
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}
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memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names;
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sc->memsize = mach64_get_memsize(sc);
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if (sc->memsize == 8192)
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/* The last page is used as register aperture. */
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sc->memsize -= 4;
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sc->memtype = regr(sc, CONFIG_STAT0) & 0x07;
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if(is_gx)
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sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07;
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else
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sc->memtype = regr(sc, CONFIG_STAT0) & 0x07;
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/* XXX is there any way to calculate reference frequency from
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known values? */
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@ -649,14 +681,26 @@ mach64_attach(device_t parent, device_t self, void *aux)
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aprint_normal_dev(sc->sc_dev,
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"%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n",
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(u_long)sc->memsize,
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mach64_memtype_names[sc->memtype],
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memtype_names[sc->memtype],
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sc->mem_freq / 1000, sc->mem_freq % 1000,
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sc->ramdac_freq / 1000);
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id = regr(sc, CONFIG_CHIP_ID) & 0xffff;
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if (id != mach64_chip_id) {
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switch(mach64_chip_id) {
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case PCI_PRODUCT_ATI_MACH64_GX:
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expected_id = 0x00d7;
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break;
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case PCI_PRODUCT_ATI_MACH64_CX:
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expected_id = 0x0057;
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break;
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default:
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/* Most chip IDs match their PCI product ID. */
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expected_id = mach64_chip_id;
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}
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if (id != expected_id) {
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aprint_error_dev(sc->sc_dev,
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"chip ID mismatch, 0x%x != 0x%x\n", id, mach64_chip_id);
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"chip ID mismatch, 0x%x != 0x%x\n", id, expected_id);
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return;
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}
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@ -706,11 +750,6 @@ mach64_attach(device_t parent, device_t self, void *aux)
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if (setmode)
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mach64_modeswitch(sc, sc->sc_my_mode);
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#if 0
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mach64_adjust_frame(0, 0);
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if (sc->bits_per_pixel == 8)
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mach64_init_lut(sc);
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#endif
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aprint_normal_dev(sc->sc_dev,
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"initial resolution %dx%d at %d bpp\n",
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@ -732,6 +771,7 @@ mach64_attach(device_t parent, device_t self, void *aux)
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machfb_blank(sc, 0); /* unblank the screen */
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if (sc->sc_console) {
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vcons_init_screen(&sc->vd, &mach64_console_screen, 1,
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&defattr);
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mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC;
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@ -741,6 +781,7 @@ mach64_attach(device_t parent, device_t self, void *aux)
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mach64_defaultscreen.capabilities = ri->ri_caps;
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mach64_defaultscreen.nrows = ri->ri_rows;
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mach64_defaultscreen.ncols = ri->ri_cols;
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wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr);
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vcons_replay_msgbuf(&mach64_console_screen);
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} else {
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@ -1045,6 +1086,9 @@ mach64_init_engine(struct mach64_softc *sc)
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regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22);
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/* make sure the visible area starts where we're going to draw */
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regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22);
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regw(sc, DST_Y_X, 0);
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regw(sc, DST_HEIGHT, 0);
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regw(sc, DST_BRES_ERR, 0);
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@ -1090,13 +1134,13 @@ mach64_init_engine(struct mach64_softc *sc)
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wait_for_fifo(sc, 2);
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switch (sc->bits_per_pixel) {
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case 8:
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regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP);
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regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP);
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regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP);
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/* We want 8 bit per channel */
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regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN);
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break;
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case 32:
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regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP);
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regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP);
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regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP);
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regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN);
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break;
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@ -1610,7 +1654,7 @@ mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data)
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int shift = 0;
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int reg = 0;
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for (i=0;i<count;i++) {
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for (i = 0; i < count; i++) {
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bork = data[i];
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latch |= (bork << shift);
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if (shift == 24) {
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