Add Alchemy PSC SPI bus protocol driver. Not activated on any boards yet,
that requires an evbmips commit.
This commit is contained in:
gdamore
parent
533076c8ff
commit
bcad08160c
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@ -0,0 +1,439 @@
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/* $NetBSD: auspi.c,v 1.1 2006/10/02 08:00:07 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
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* Copyright (c) 2006 Garrett D'Amore.
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* All rights reserved.
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*
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* Portions of this code were written by Garrett D'Amore for the
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* Champaign-Urbana Community Wireless Network Project.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. All advertising materials mentioning features or use of this
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* software must display the following acknowledgements:
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* This product includes software developed by the Urbana-Champaign
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* Independent Media Center.
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* This product includes software developed by Garrett D'Amore.
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* 4. Urbana-Champaign Independent Media Center's name and Garrett
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* D'Amore's name may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT
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* MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT
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* MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: auspi.c,v 1.1 2006/10/02 08:00:07 gdamore Exp $");
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#include "locators.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/proc.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <mips/alchemy/include/aubusvar.h>
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#include <mips/alchemy/include/auvar.h>
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#include <mips/alchemy/dev/aupscreg.h>
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#include <mips/alchemy/dev/aupscvar.h>
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#include <mips/alchemy/dev/auspireg.h>
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#include <mips/alchemy/dev/auspivar.h>
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#include <dev/spi/spivar.h>
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struct auspi_softc {
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struct device sc_dev;
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struct aupsc_controller sc_psc; /* parent controller ops */
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struct spi_controller sc_spi; /* SPI implementation ops */
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struct auspi_machdep sc_md; /* board-specific support */
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struct auspi_job *sc_job; /* current job */
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struct spi_chunk *sc_wchunk;
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struct spi_chunk *sc_rchunk;
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void *sc_ih; /* interrupt handler */
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struct spi_transfer *sc_transfer;
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boolean_t sc_running; /* is it processing stuff? */
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SIMPLEQ_HEAD(,spi_transfer) sc_q;
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};
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#define auspi_select(sc, slave) \
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(sc)->sc_md.am_select((sc)->sc_md.am_cookie, (slave))
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#define STATIC
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STATIC int auspi_match(struct device *, struct cfdata *, void *);
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STATIC void auspi_attach(struct device *, struct device *, void *);
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STATIC int auspi_intr(void *);
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CFATTACH_DECL(auspi, sizeof(struct auspi_softc),
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auspi_match, auspi_attach, NULL, NULL);
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/* SPI service routines */
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STATIC int auspi_configure(void *, int, int, int);
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STATIC int auspi_transfer(void *, struct spi_transfer *);
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/* internal stuff */
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STATIC void auspi_done(struct auspi_softc *, int);
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STATIC void auspi_send(struct auspi_softc *);
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STATIC void auspi_recv(struct auspi_softc *);
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STATIC void auspi_sched(struct auspi_softc *);
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#define GETREG(sc, x) \
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bus_space_read_4(sc->sc_psc.psc_bust, sc->sc_psc.psc_bush, x)
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#define PUTREG(sc, x, v) \
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bus_space_write_4(sc->sc_psc.psc_bust, sc->sc_psc.psc_bush, x, v)
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int
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auspi_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct aupsc_attach_args *aa = aux;
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if (strcmp(aa->aupsc_name, cf->cf_name) != 0)
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return 0;
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return 1;
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}
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void
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auspi_attach(struct device *parent, struct device *self, void *aux)
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{
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struct auspi_softc *sc = device_private(self);
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struct aupsc_attach_args *aa = aux;
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struct spibus_attach_args sba;
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const struct auspi_machdep *md;
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if ((md = auspi_machdep(aa->aupsc_addr)) != NULL) {
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sc->sc_md = *md;
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}
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aprint_normal(": Alchemy PSC SPI protocol\n");
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sc->sc_psc = aa->aupsc_ctrl;
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/*
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* Initialize SPI controller
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*/
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sc->sc_spi.sct_cookie = sc;
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sc->sc_spi.sct_configure = auspi_configure;
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sc->sc_spi.sct_transfer = auspi_transfer;
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/* fix this! */
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sc->sc_spi.sct_nslaves = sc->sc_md.am_nslaves;
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sba.sba_controller = &sc->sc_spi;
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/* enable SPI mode */
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sc->sc_psc.psc_enable(sc, AUPSC_SEL_SPI);
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/* initialize the queue */
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SIMPLEQ_INIT(&sc->sc_q);
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/* make sure interrupts disabled at the SPI */
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PUTREG(sc, AUPSC_SPIMSK, SPIMSK_ALL);
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/* enable device interrupts */
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sc->sc_ih = au_intr_establish(aa->aupsc_irq, 0, IPL_SERIAL, IST_LEVEL,
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auspi_intr, sc);
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(void) config_found_ia(&sc->sc_dev, "spibus", &sba, spibus_print);
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}
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int
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auspi_configure(void *arg, int slave, int mode, int speed)
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{
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struct auspi_softc *sc = arg;
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int brg, i;
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uint32_t reg;
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/* setup interrupt registers */
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PUTREG(sc, AUPSC_SPIMSK, SPIMSK_NORM);
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reg = GETREG(sc, AUPSC_SPICFG);
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reg &= ~(SPICFG_BRG_MASK); /* clear BRG */
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reg &= ~(SPICFG_DIV_MASK); /* use pscn_mainclock/2 */
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reg &= ~(SPICFG_PSE); /* disable port swap */
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reg &= ~(SPICFG_BI); /* clear bit clock invert */
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reg &= ~(SPICFG_CDE); /* clear clock phase delay */
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reg &= ~(SPICFG_CGE); /* clear clock gate enable */
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//reg |= SPICFG_MO; /* master-only mode */
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reg |= SPICFG_DE; /* device enable */
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reg |= SPICFG_DD; /* disable DMA */
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reg |= SPICFG_RT_1; /* 1 byte rx fifo threshold */
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reg |= SPICFG_TT_1; /* 1 byte tx fifo threshold */
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reg |= ((8-1) << SPICFG_LEN_SHIFT);/* always work in 8-bit chunks */
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/*
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* We assume a base clock of 48MHz has been established by the
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* platform code. The clock divider reduces this to 24MHz.
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* Next we have to figure out the BRG
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*/
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#define BASECLK 24000000
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for (brg = 0; brg < 64; brg++) {
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if (speed >= (BASECLK / ((brg + 1) * 2))) {
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break;
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}
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}
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/*
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* Does the device want to go even slower? Our minimum speed without
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* changing other assumptions, and complicating the code even further,
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* is 24MHz/128, or 187.5kHz. That should be slow enough for any
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* device we're likely to encounter.
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*/
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if (speed < (BASECLK / ((brg + 1) * 2))) {
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return EINVAL;
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}
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reg &= ~SPICFG_BRG_MASK;
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reg |= (brg << SPICFG_BRG_SHIFT);
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/*
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* I'm not entirely confident that these values are correct.
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* But at least mode 0 appears to work properly with the
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* devices I have tested. The documentation seems to suggest
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* that I have the meaning of the clock delay bit inverted.
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*/
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switch (mode) {
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case SPI_MODE_0:
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reg |= 0; /* CPHA = 0, CPOL = 0 */
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break;
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case SPI_MODE_1:
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reg |= SPICFG_CDE; /* CPHA = 1, CPOL = 0 */
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break;
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case SPI_MODE_2:
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reg |= SPICFG_BI; /* CPHA = 0, CPOL = 1 */
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break;
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case SPI_MODE_3:
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reg |= SPICFG_CDE | SPICFG_BI; /* CPHA = 1, CPOL = 1 */
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break;
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default:
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return EINVAL;
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}
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PUTREG(sc, AUPSC_SPICFG, reg);
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for (i = 1000000; i; i -= 10) {
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if (GETREG(sc, AUPSC_SPISTAT) & SPISTAT_DR) {
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return 0;
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}
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}
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return ETIMEDOUT;
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}
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void
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auspi_send(struct auspi_softc *sc)
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{
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uint32_t data;
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struct spi_chunk *chunk;
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/* fill the fifo */
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while ((chunk = sc->sc_wchunk) != NULL) {
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while (chunk->chunk_wresid) {
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/* transmit fifo full? */
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if (GETREG(sc, AUPSC_SPISTAT) & SPISTAT_TF) {
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return;
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}
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if (chunk->chunk_wptr) {
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data = *chunk->chunk_wptr++;
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} else {
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data = 0;
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}
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chunk->chunk_wresid--;
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/* if the last outbound character, mark it */
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if ((chunk->chunk_wresid == 0) &&
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(chunk->chunk_next == NULL)) {
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data |= SPITXRX_LC;
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}
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PUTREG(sc, AUPSC_SPITXRX, data);
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}
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/* advance to next transfer */
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sc->sc_wchunk = sc->sc_wchunk->chunk_next;
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}
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}
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void
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auspi_recv(struct auspi_softc *sc)
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{
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uint32_t data;
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struct spi_chunk *chunk;
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while ((chunk = sc->sc_rchunk) != NULL) {
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while (chunk->chunk_rresid) {
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/* rx fifo empty? */
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if ((GETREG(sc, AUPSC_SPISTAT) & SPISTAT_RE) != 0) {
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return;
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}
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/* collect rx data */
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data = GETREG(sc, AUPSC_SPITXRX);
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if (chunk->chunk_rptr) {
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*chunk->chunk_rptr++ = data & 0xff;
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}
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chunk->chunk_rresid--;
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}
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/* advance next to next transfer */
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sc->sc_rchunk = sc->sc_rchunk->chunk_next;
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}
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}
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void
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auspi_sched(struct auspi_softc *sc)
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{
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struct spi_transfer *st;
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int err;
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while ((st = spi_transq_first(&sc->sc_q)) != NULL) {
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/* remove the item */
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spi_transq_dequeue(&sc->sc_q);
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/* note that we are working on it */
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sc->sc_transfer = st;
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if ((err = auspi_select(sc, st->st_slave)) != 0) {
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spi_done(st, err);
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continue;
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}
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/* clear the fifos */
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PUTREG(sc, AUPSC_SPIPCR, SPIPCR_RC | SPIPCR_TC);
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/* setup chunks */
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sc->sc_rchunk = sc->sc_wchunk = st->st_chunks;
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auspi_send(sc);
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/* now kick the master start to get the chip running */
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PUTREG(sc, AUPSC_SPIPCR, SPIPCR_MS);
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sc->sc_running = TRUE;
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return;
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}
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auspi_select(sc, -1);
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sc->sc_running = FALSE;
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}
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void
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auspi_done(struct auspi_softc *sc, int err)
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{
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struct spi_transfer *st;
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/* called from interrupt handler */
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if ((st = sc->sc_transfer) != NULL) {
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sc->sc_transfer = NULL;
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spi_done(st, err);
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}
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/* make sure we clear these bits out */
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sc->sc_wchunk = sc->sc_rchunk = NULL;
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auspi_sched(sc);
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}
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int
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auspi_intr(void *arg)
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{
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struct auspi_softc *sc = arg;
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uint32_t ev;
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int err = 0;
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if ((GETREG(sc, AUPSC_SPISTAT) & SPISTAT_DI) == 0) {
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return 0;
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}
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ev = GETREG(sc, AUPSC_SPIEVNT);
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if (ev & SPIMSK_MM) {
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printf("%s: multiple masters detected!\n",
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sc->sc_dev.dv_xname);
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err = EIO;
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}
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if (ev & SPIMSK_RO) {
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printf("%s: receive overflow\n", sc->sc_dev.dv_xname);
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err = EIO;
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}
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if (ev & SPIMSK_TU) {
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printf("%s: transmit underflow\n", sc->sc_dev.dv_xname);
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err = EIO;
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}
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if (err) {
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/* clear errors */
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PUTREG(sc, AUPSC_SPIEVNT,
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ev & (SPIMSK_MM | SPIMSK_RO | SPIMSK_TU));
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/* clear the fifos */
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PUTREG(sc, AUPSC_SPIPCR, SPIPCR_RC | SPIPCR_TC);
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auspi_done(sc, err);
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} else {
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/* do all data exchanges */
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auspi_send(sc);
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auspi_recv(sc);
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/*
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* if the master done bit is set, make sure we do the
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* right processing.
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*/
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if (ev & SPIMSK_MD) {
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if ((sc->sc_wchunk != NULL) ||
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(sc->sc_rchunk != NULL)) {
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printf("%s: partial transfer?\n",
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sc->sc_dev.dv_xname);
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err = EIO;
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}
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auspi_done(sc, err);
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}
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/* clear interrupts */
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PUTREG(sc, AUPSC_SPIEVNT,
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ev & (SPIMSK_TR | SPIMSK_RR | SPIMSK_MD));
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}
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return 1;
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}
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int
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auspi_transfer(void *arg, struct spi_transfer *st)
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{
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struct auspi_softc *sc = arg;
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int s;
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/* make sure we select the right chip */
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s = splserial();
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spi_transq_enqueue(&sc->sc_q, st);
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if (sc->sc_running == 0) {
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auspi_sched(sc);
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}
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splx(s);
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return 0;
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}
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@ -0,0 +1,109 @@
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/* $NetBSD: auspireg.h,v 1.1 2006/10/02 08:00:07 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
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* Copyright (c) 2006 Garrett D'Amore.
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* All rights reserved.
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*
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* Portions of this code were written by Garrett D'Amore for the
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* Champaign-Urbana Community Wireless Network Project.
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*
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* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
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* conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above
|
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* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
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* with the distribution.
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* 3. All advertising materials mentioning features or use of this
|
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* software must display the following acknowledgements:
|
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* This product includes software developed by the Urbana-Champaign
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* Independent Media Center.
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* This product includes software developed by Garrett D'Amore.
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* 4. Urbana-Champaign Independent Media Center's name and Garrett
|
||||
* D'Amore's name may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT
|
||||
* MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT
|
||||
* MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_ALCHEMY_AUSPIREG_H_
|
||||
#define _MIPS_ALCHEMY_AUSPIREG_H_
|
||||
|
||||
#define SPICFG_RT_8 (0x3 << 30)
|
||||
#define SPICFG_RT_4 (0x2 << 30)
|
||||
#define SPICFG_RT_2 (0x1 << 30)
|
||||
#define SPICFG_RT_1 (0x0 << 30)
|
||||
#define SPICFG_TT_8 (0x3 << 28)
|
||||
#define SPICFG_TT_4 (0x2 << 28)
|
||||
#define SPICFG_TT_2 (0x1 << 28)
|
||||
#define SPICFG_TT_1 (0x0 << 28)
|
||||
#define SPICFG_DD (1 << 27) /* disable DMA */
|
||||
#define SPICFG_DE (1 << 26) /* device enable */
|
||||
#define SPICFG_BRG_MASK (0x3f << 15) /* baud rate generator */
|
||||
#define SPICFG_BRG_SHIFT 15
|
||||
#define SPICFG_DIV_MASK (0x3 << 13) /* psc clock divider */
|
||||
#define SPICFG_DIV_SHIFT 13
|
||||
#define SPICFG_BI (1 << 12) /* bit clock invert */
|
||||
#define SPICFG_PSE (1 << 11) /* port swap enable */
|
||||
#define SPICFG_CGE (1 << 10) /* clock gate enable */
|
||||
#define SPICFG_CDE (1 << 9) /* clock phase delay enable */
|
||||
#define SPICFG_LEN_MASK (0x1f << 4) /* data length */
|
||||
#define SPICFG_LEN_SHIFT 4
|
||||
#define SPICFG_LB (1 << 3) /* loopback mode */
|
||||
#define SPICFG_MLF (1 << 2) /* msb/lsb data first */
|
||||
#define SPICFG_MO (1 << 0) /* master only mode */
|
||||
|
||||
/* and also SPIEVNT */
|
||||
#define SPIMSK_MM (1 << 16) /* multiple master error */
|
||||
#define SPIMSK_RR (1 << 13) /* rx fifo request */
|
||||
#define SPIMSK_RO (1 << 12) /* rx fifo overflow */
|
||||
#define SPIMSK_RU (1 << 11) /* rx fifo underflow */
|
||||
#define SPIMSK_TR (1 << 10) /* tx fifo request */
|
||||
#define SPIMSK_TO (1 << 9) /* tx fifo overflow */
|
||||
#define SPIMSK_TU (1 << 8) /* tx fifo underflow */
|
||||
#define SPIMSK_SD (1 << 5) /* slave done */
|
||||
#define SPIMSK_MD (1 << 4) /* master done */
|
||||
#define SPIMSK_ALL (SPIMSK_MM | SPIMSK_RR | SPIMSK_RO | \
|
||||
SPIMSK_RU | SPIMSK_TR | SPIMSK_TO | \
|
||||
SPIMSK_TU | SPIMSK_SD | SPIMSK_MD)
|
||||
#define SPIMSK_NORM (SPIMSK_RU | SPIMSK_TO | SPIMSK_TR | SPIMSK_SD)
|
||||
|
||||
#define SPIPCR_RC (1 << 6) /* rx data clear */
|
||||
#define SPIPCR_SP (1 << 5) /* slave stop */
|
||||
#define SPIPCR_SS (1 << 4) /* slave start */
|
||||
#define SPIPCR_TC (1 << 2) /* tx data clear */
|
||||
#define SPIPCR_MS (1 << 0) /* master start*/
|
||||
|
||||
#define SPISTAT_RF (1 << 13) /* rx fifo full */
|
||||
#define SPISTAT_RE (1 << 12) /* rx fifo empty */
|
||||
#define SPISTAT_RR (1 << 11) /* rx request */
|
||||
#define SPISTAT_TF (1 << 10) /* tx fifo full */
|
||||
#define SPISTAT_TE (1 << 9) /* tx fifo empty */
|
||||
#define SPISTAT_TR (1 << 8) /* tx request */
|
||||
#define SPISTAT_SB (1 << 5) /* slave busy */
|
||||
#define SPISTAT_MB (1 << 4) /* master busy */
|
||||
#define SPISTAT_DI (1 << 2) /* device interrupt */
|
||||
#define SPISTAT_DR (1 << 1) /* device ready */
|
||||
#define SPISTAT_SR (1 << 0) /* psc ready */
|
||||
|
||||
#define SPITXRX_LC (1 << 29) /* last character */
|
||||
#define SPITXRX_ST (1 << 28) /* select togle */
|
||||
#define SPITXRX_DATA_MASK (0xffffff)
|
||||
#define SPITXRX_DATA_SHIFT 0
|
||||
|
||||
#endif /* _MIPS_ALCHEMY_AUSPIREG_H_ */
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/* $NetBSD: auspivar.h,v 1.1 2006/10/02 08:00:07 gdamore Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
|
||||
* Copyright (c) 2006 Garrett D'Amore.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Portions of this code were written by Garrett D'Amore for the
|
||||
* Champaign-Urbana Community Wireless Network Project.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
||||
* with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this
|
||||
* software must display the following acknowledgements:
|
||||
* This product includes software developed by the Urbana-Champaign
|
||||
* Independent Media Center.
|
||||
* This product includes software developed by Garrett D'Amore.
|
||||
* 4. Urbana-Champaign Independent Media Center's name and Garrett
|
||||
* D'Amore's name may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT
|
||||
* MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT
|
||||
* MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_ALCHEMY_AUSPIVAR_H_
|
||||
#define _MIPS_ALCHEMY_AUSPIVAR_H_
|
||||
|
||||
struct auspi_machdep {
|
||||
int am_nslaves;
|
||||
void *am_cookie;
|
||||
int (*am_select)(void *, int);
|
||||
};
|
||||
|
||||
const struct auspi_machdep *auspi_machdep(bus_addr_t);
|
||||
|
||||
#endif /* _MIPS_ALCHEMY_AUSPIVAR_H_ */
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: files.alchemy,v 1.12 2006/07/13 22:56:01 gdamore Exp $
|
||||
# $NetBSD: files.alchemy,v 1.13 2006/10/02 08:00:07 gdamore Exp $
|
||||
|
||||
defflag opt_alchemy.h ALCHEMY_AU1000
|
||||
ALCHEMY_AU1100
|
||||
|
|
@ -66,6 +66,11 @@ device ausmbus: i2cbus, i2c_bitbang
|
|||
attach ausmbus at aupsc
|
||||
file arch/mips/alchemy/dev/ausmbus_psc.c ausmbus
|
||||
|
||||
# On-chip PSC SPI Protocol
|
||||
device auspi: spibus
|
||||
attach auspi at aupsc
|
||||
file arch/mips/alchemy/dev/auspi.c auspi needs-flag
|
||||
|
||||
# On-chip PCMCIA
|
||||
#
|
||||
# XXX: NOTE: As of Feb. 22, 2006, the aupcmcia bus is not quite
|
||||
|
|
|
|||
Loading…
Reference in New Issue