Make pciide(4)-only configurations (without other DMA-capable driver) compile.
This commit is contained in:
itohy
parent
65a8f1c211
commit
bb09c44e46
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@ -1,4 +1,4 @@
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/* $NetBSD: pciide_common.c,v 1.32 2006/10/12 01:31:33 christos Exp $ */
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/* $NetBSD: pciide_common.c,v 1.33 2006/10/17 13:45:05 itohy Exp $ */
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/*
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@ -76,7 +76,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.32 2006/10/12 01:31:33 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.33 2006/10/17 13:45:05 itohy Exp $");
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#include <sys/param.h>
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#include <sys/malloc.h>
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@ -95,8 +95,10 @@ __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.32 2006/10/12 01:31:33 christos
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int atadebug_pciide_mask = 0;
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#endif
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#if NATA_DMA
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static const char dmaerrfmt[] =
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"%s:%d: unable to %s table DMA map for drive %d, error=%d\n";
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#endif
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/* Default product description for devices not known from this controller */
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const struct pciide_product_desc default_product_desc = {
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@ -128,7 +130,9 @@ pciide_common_attach(sc, pa, pp)
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{
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pci_chipset_tag_t pc = pa->pa_pc;
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pcitag_t tag = pa->pa_tag;
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#if NATA_DMA
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pcireg_t csr;
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#endif
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char devinfo[256];
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const char *displaydev;
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@ -155,9 +159,11 @@ pciide_common_attach(sc, pa, pp)
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sc->sc_pc = pa->pa_pc;
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sc->sc_tag = pa->pa_tag;
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#if NATA_DMA
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/* Set up DMA defaults; these might be adjusted by chip_map. */
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sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX;
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sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN;
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#endif
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#ifdef ATADEBUG
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if (atadebug_pciide_mask & DEBUG_PROBE)
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@ -165,11 +171,13 @@ pciide_common_attach(sc, pa, pp)
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#endif
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sc->sc_pp->chip_map(sc, pa);
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#if NATA_DMA
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if (sc->sc_dma_ok) {
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csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
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csr |= PCI_COMMAND_MASTER_ENABLE;
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pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
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}
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#endif
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ATADEBUG_PRINT(("pciide: command/status register=%x\n",
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pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE);
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}
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@ -338,6 +346,7 @@ bad:
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return;
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}
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#if NATA_DMA
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void
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pciide_mapreg_dma(sc, pa)
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struct pciide_softc *sc;
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@ -440,6 +449,7 @@ pciide_mapreg_dma(sc, pa)
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}
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}
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}
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#endif /* NATA_DMA */
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int
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pciide_compat_intr(arg)
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@ -487,6 +497,7 @@ pciide_pci_intr(arg)
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return (rv);
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}
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#if NATA_DMA
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void
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pciide_channel_dma_setup(cp)
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struct pciide_channel *cp;
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@ -768,6 +779,7 @@ pciide_irqack(chp)
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bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
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bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0));
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}
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#endif /* NATA_DMA */
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/* some common code used by several chip_map */
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int
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@ -855,8 +867,11 @@ default_chip_map(sc, pa)
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struct pciide_channel *cp;
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pcireg_t interface = PCI_INTERFACE(pa->pa_class);
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pcireg_t csr;
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int channel, drive;
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int channel;
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#if NATA_DMA
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int drive;
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u_int8_t idedma_ctl;
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#endif
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bus_size_t cmdsize, ctlsize;
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const char *failreason;
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struct wdc_regs *wdr;
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@ -865,6 +880,7 @@ default_chip_map(sc, pa)
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return;
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if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) {
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#if NATA_DMA
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aprint_normal("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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if (sc->sc_pp == &default_product_desc &&
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@ -878,18 +894,28 @@ default_chip_map(sc, pa)
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aprint_normal(", used without full driver "
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"support");
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}
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#else
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aprint_normal("%s: bus-master DMA support present, but unused (no driver support)",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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#endif /* NATA_DMA */
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} else {
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aprint_normal("%s: hardware does not support DMA",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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#if NATA_DMA
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sc->sc_dma_ok = 0;
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#endif
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}
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aprint_normal("\n");
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#if NATA_DMA
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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}
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#endif
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
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#if NATA_DMA
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 0;
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#endif
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
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@ -959,6 +985,7 @@ next:
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}
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}
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#if NATA_DMA
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if (sc->sc_dma_ok == 0)
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return;
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@ -992,12 +1019,14 @@ next:
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cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl);
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}
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}
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#endif /* NATA_DMA */
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}
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void
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sata_setup_channel(chp)
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struct ata_channel *chp;
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{
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#if NATA_DMA
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struct ata_drive_datas *drvp;
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int drive, s;
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u_int32_t idedma_ctl;
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@ -1014,13 +1043,16 @@ sata_setup_channel(chp)
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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#if NATA_UDMA
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if (drvp->drive_flags & DRIVE_UDMA) {
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/* use Ultra/DMA */
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s = splbio();
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drvp->drive_flags &= ~DRIVE_DMA;
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splx(s);
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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} else if (drvp->drive_flags & DRIVE_DMA) {
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} else
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#endif /* NATA_UDMA */
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if (drvp->drive_flags & DRIVE_DMA) {
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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}
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}
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@ -1035,4 +1067,5 @@ sata_setup_channel(chp)
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bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
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idedma_ctl);
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}
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#endif /* NATA_DMA */
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: pciidevar.h,v 1.34 2006/06/17 17:05:20 jmcneill Exp $ */
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/* $NetBSD: pciidevar.h,v 1.35 2006/10/17 13:45:05 itohy Exp $ */
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/*
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* Copyright (c) 1998 Christopher G. Demetriou. All rights reserved.
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@ -79,6 +79,7 @@ struct pciide_softc {
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pci_chipset_tag_t sc_pc; /* PCI registers info */
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pcitag_t sc_tag;
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void *sc_pci_ih; /* PCI interrupt handle */
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#if NATA_DMA
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int sc_dma_ok; /* bus-master DMA info */
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/*
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* sc_dma_ioh may only be used to allocate the dma_iohs
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@ -115,6 +116,7 @@ struct pciide_softc {
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bus_space_tag_t sc_ba5_st;
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bus_space_handle_t sc_ba5_sh;
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int sc_ba5_en;
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#endif /* NATA_DMA */
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/* Vendor info (for interpreting Chip description) */
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pcireg_t sc_pci_id;
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@ -129,6 +131,7 @@ struct pciide_softc {
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int compat; /* is it compat? */
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void *ih; /* compat or pci handle */
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bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */
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#if NATA_DMA
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/* DMA tables and DMA map for xfer, for each drive */
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struct pciide_dma_maps {
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bus_dmamap_t dmamap_table;
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@ -144,6 +147,7 @@ struct pciide_softc {
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* required.
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*/
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uint8_t idedma_cmd;
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#endif /* NATA_DMA */
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} pciide_channels[PCIIDE_MAX_CHANNELS];
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/* Power management */
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