Fix device timeout problem.
- Change the synching order of descriptors. First, sync descriptors except first and then sync the first descriptor. - To recover from an race condition, reduce the if_timer from 5 to 1 and when timeout occur write MVGBE_TQC_ENQ bit again.
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@ -1,4 +1,4 @@
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/* $NetBSD: if_mvgbe.c,v 1.19 2012/09/06 03:45:02 msaitoh Exp $ */
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/* $NetBSD: if_mvgbe.c,v 1.20 2012/09/21 00:26:15 msaitoh Exp $ */
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/*
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* Copyright (c) 2007, 2008 KIYOHARA Takashi
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* All rights reserved.
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@ -25,7 +25,7 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.19 2012/09/06 03:45:02 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.20 2012/09/21 00:26:15 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -206,6 +206,7 @@ struct mvgbe_softc {
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struct mvgbe_ring_data *sc_rdata;
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bus_dmamap_t sc_ring_map;
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int sc_if_flags;
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int sc_wdogsoft;
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LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead;
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LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead;
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@ -903,7 +904,8 @@ mvgbe_start(struct ifnet *ifp)
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/*
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* Set a timeout in case the chip goes out to lunch.
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*/
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ifp->if_timer = 5;
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ifp->if_timer = 1;
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sc->sc_wdogsoft = 1;
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}
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}
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@ -1162,11 +1164,22 @@ mvgbe_watchdog(struct ifnet *ifp)
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*/
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mvgbe_txeof(sc);
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if (sc->sc_cdata.mvgbe_tx_cnt != 0) {
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aprint_error_ifnet(ifp, "watchdog timeout\n");
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if (sc->sc_wdogsoft) {
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/*
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* There is race condition between CPU and DMA
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* engine. When DMA engine encounters queue end,
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* it clears MVGBE_TQC_ENQ bit.
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*/
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MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ);
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ifp->if_timer = 5;
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sc->sc_wdogsoft = 0;
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} else {
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aprint_error_ifnet(ifp, "watchdog timeout\n");
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ifp->if_oerrors++;
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ifp->if_oerrors++;
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mvgbe_init(ifp);
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mvgbe_init(ifp);
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}
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}
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}
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@ -1589,7 +1602,8 @@ do_defrag:
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f = &sc->sc_rdata->mvgbe_tx_ring[current];
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f->bufptr = txseg[i].ds_addr;
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f->bytecnt = txseg[i].ds_len;
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f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA;
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if (i != 0)
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f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA;
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last = current;
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current = MVGBE_TX_RING_NEXT(current);
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}
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@ -1610,7 +1624,6 @@ do_defrag:
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}
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if (txmap->dm_nsegs == 1)
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f->cmdsts = cmdsts |
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MVGBE_BUFFER_OWNED_BY_DMA |
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MVGBE_TX_GENERATE_CRC |
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MVGBE_TX_ENABLE_INTERRUPT |
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MVGBE_TX_ZERO_PADDING |
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@ -1619,7 +1632,6 @@ do_defrag:
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else {
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f = &sc->sc_rdata->mvgbe_tx_ring[first];
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f->cmdsts = cmdsts |
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MVGBE_BUFFER_OWNED_BY_DMA |
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MVGBE_TX_GENERATE_CRC |
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MVGBE_TX_FIRST_DESC;
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@ -1629,14 +1641,22 @@ do_defrag:
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MVGBE_TX_ENABLE_INTERRUPT |
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MVGBE_TX_ZERO_PADDING |
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MVGBE_TX_LAST_DESC;
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/* Sync descriptors except first */
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MVGBE_CDTXSYNC(sc,
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(MVGBE_TX_RING_CNT - 1 == *txidx) ? 0 : (*txidx) + 1,
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txmap->dm_nsegs - 1,
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BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
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}
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sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head;
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SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link);
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sc->sc_cdata.mvgbe_tx_map[last] = entry;
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/* Sync descriptors before handing to chip */
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MVGBE_CDTXSYNC(sc, *txidx, txmap->dm_nsegs,
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/* Finally, sync first descriptor */
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sc->sc_rdata->mvgbe_tx_ring[first].cmdsts |=
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MVGBE_BUFFER_OWNED_BY_DMA;
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MVGBE_CDTXSYNC(sc, *txidx, 1,
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BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
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sc->sc_cdata.mvgbe_tx_cnt += i;
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