Enormous pile of changes from mark's (uncommitted) work on this driver.
About the only bit of his code not here is the transmit routines, which I'll merge in separately. Also a few bug-fixes, so (for instance) multicast on an 8005 doesn't immediately fall back to IFF_ALLMULTI.
This commit is contained in:
bjh21
parent
2dbd96c75c
commit
b94b953e92
@ -1,8 +1,8 @@
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/* $NetBSD: seeq8005.c,v 1.10 2001/03/24 13:40:41 bjh21 Exp $ */
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/* $NetBSD: seeq8005.c,v 1.11 2001/03/24 20:38:41 bjh21 Exp $ */
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/*
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* Copyright (c) 2000 Ben Harris
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* Copyright (c) 1995 Mark Brinicombe
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* Copyright (c) 1995-1998 Mark Brinicombe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -15,7 +15,8 @@
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe.
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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@ -39,6 +40,13 @@
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* This driver currently supports the following chip:
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* SEEQ 8005 Advanced Ethernet Data Link Controller
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*/
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/*
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* More information on the 8004 and 8005 AEDLC controllers can be found in
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* the SEEQ Technology Inc 1992 Data Comm Devices data book.
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*
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* This data book may no longer be available as these are rather old chips
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* (1991 - 1993)
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*/
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/*
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* This driver is based on the arm32 ea(4) driver, hence the names of many
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* of the functions.
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@ -46,9 +54,7 @@
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/*
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* Bugs/possible improvements:
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* - Does not currently support DMA
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* - Does not currently support multicasts
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* - Does not transmit multiple packets in one go
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* - Does not support big-endian hosts
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* - Does not support 8-bit busses
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*/
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@ -58,7 +64,7 @@
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#include <sys/types.h>
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#include <sys/param.h>
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__RCSID("$NetBSD: seeq8005.c,v 1.10 2001/03/24 13:40:41 bjh21 Exp $");
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__RCSID("$NetBSD: seeq8005.c,v 1.11 2001/03/24 20:38:41 bjh21 Exp $");
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#include <sys/systm.h>
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#include <sys/endian.h>
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@ -73,6 +79,7 @@ __RCSID("$NetBSD: seeq8005.c,v 1.10 2001/03/24 13:40:41 bjh21 Exp $");
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#include <net/if_dl.h>
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#include <net/if_types.h>
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#include <net/if_ether.h>
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#include <net/if_media.h>
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#ifdef INET
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#include <netinet/in.h>
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@ -99,24 +106,24 @@ __RCSID("$NetBSD: seeq8005.c,v 1.10 2001/03/24 13:40:41 bjh21 Exp $");
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#include <dev/ic/seeq8005reg.h>
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#include <dev/ic/seeq8005var.h>
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#ifndef SEEQ_TIMEOUT
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#define SEEQ_TIMEOUT 60
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#endif
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#define SEEQ_TX_BUFFER_SIZE 0x4000
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#define SEEQ_RX_BUFFER_SIZE 0xC000
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/*#define SEEQ_TX_DEBUG*/
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/*#define SEEQ_RX_DEBUG*/
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/*#define SEEQ_DEBUG*/
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/*#define SEEQ_PACKET_DEBUG*/
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/* for debugging convenience */
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#ifdef SEEQ_DEBUG
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#define dprintf(x) printf x
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#define SEEQ_DEBUG_MISC 1
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#define SEEQ_DEBUG_TX 2
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#define SEEQ_DEBUG_RX 4
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#define SEEQ_DEBUG_PKT 8
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#define SEEQ_DEBUG_TXINT 16
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#define SEEQ_DEBUG_RXINT 32
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int seeq_debug = 0;
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#define DPRINTF(f, x) { if (seeq_debug & (f)) printf x; }
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#else
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#define dprintf(x)
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#define DPRINTF(f, x)
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#endif
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#define dprintf(x) DPRINTF(SEEQ_DEBUG_MISC, x)
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#define SEEQ_TX_BUFFER_SIZE 0x600 /* (> MAX_ETHER_LEN) */
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/*
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* prototypes
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@ -133,74 +140,33 @@ static int ea_stoprx(struct seeq8005_softc *);
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static void ea_stop(struct ifnet *, int);
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static void ea_await_fifo_empty(struct seeq8005_softc *);
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static void ea_await_fifo_full(struct seeq8005_softc *);
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static void ea_writebuf(struct seeq8005_softc *, u_char *, u_int, size_t);
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static void ea_readbuf(struct seeq8005_softc *, u_char *, u_int, size_t);
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static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t);
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static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t);
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static void ea_select_buffer(struct seeq8005_softc *, int);
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static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *);
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static void earead(struct seeq8005_softc *, int, int);
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static struct mbuf *eaget(struct seeq8005_softc *, int, int, struct ifnet *);
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static void eagetpackets(struct seeq8005_softc *);
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static void ea_read(struct seeq8005_softc *, int, int);
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static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *);
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static void ea_getpackets(struct seeq8005_softc *);
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static void eatxpacket(struct seeq8005_softc *);
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static void ea_mc_reset(struct seeq8005_softc *);
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static void ea_mc_reset_8004(struct seeq8005_softc *);
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static void ea_mc_reset_8005(struct seeq8005_softc *);
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static int ea_mediachange(struct ifnet *);
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static void ea_mediastatus(struct ifnet *, struct ifmediareq *);
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#ifdef SEEQ_PACKET_DEBUG
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void ea_dump_buffer(struct seeq8005_softc *, int);
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#endif
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#ifdef SEEQ_PACKET_DEBUG
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/*
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* Dump the interface buffer
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*/
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void
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ea_dump_buffer(struct seeq8005_softc *sc, u_int offset)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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u_int addr;
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int loop, ctrl, ptr;
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size_t size;
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addr = offset;
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do {
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bus_space_write_2(iot, ioh, SEEQ_COMMAND,
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sc->sc_command | SEEQ_CMD_FIFO_READ);
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bus_space_write_2(iot, ioh, SEEQ_CONFIG1,
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sc->sc_config1 | SEEQ_BUFCODE_LOCAL_MEM);
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bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr);
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ptr = bus_space_read_2(iot, ioh, SEEQ_BUFWIN);
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ctrl = bus_space_read_2(iot, ioh, SEEQ_BUFWIN);
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ptr = ((ptr & 0xff) << 8) | ((ptr >> 8) & 0xff);
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if (ptr == 0) break;
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size = ptr - addr;
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printf("addr=%04x size=%04x ", addr, size);
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printf("cmd=%02x st=%02x\n", ctrl & 0xff, ctrl >> 8);
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for (loop = 0; loop < size - 4; loop += 2)
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printf("%04x ",
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bus_space_read_2(iot, ioh, SEEQ_BUFWIN));
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printf("\n");
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addr = ptr;
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} while (size != 0);
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}
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#endif
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/*
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* Attach chip.
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*/
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void
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seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr)
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seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media,
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int nmedia, int defmedia)
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{
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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u_int id;
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KASSERT(myaddr != NULL);
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printf(" address %s", ether_sprintf(myaddr));
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/* Stop the board. */
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@ -212,11 +178,51 @@ seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr)
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ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID);
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id = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN);
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if ((id & 0xf0) == 0xa0) {
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sc->sc_flags |= SEEQ8005_80C04;
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printf(", SEEQ 80C04 rev %02x", id);
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} else
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printf(", SEEQ 8005");
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switch (id & SEEQ_PRODUCTID_MASK) {
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case SEEQ_PRODUCTID_8004:
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sc->sc_variant = SEEQ_8004;
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break;
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default: /* XXX */
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sc->sc_variant = SEEQ_8005;
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break;
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}
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switch (sc->sc_variant) {
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case SEEQ_8004:
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printf(", SEEQ80C04 rev %x\n",
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id & SEEQ_PRODUCTID_REV_MASK);
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break;
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case SEEQ_8005:
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if (id != 0xff)
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printf(", SEEQ8005 rev %x\n", id);
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else
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printf(", SEEQ8005\n");
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break;
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default:
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printf(", Unknown ethernet controller\n");
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return;
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}
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/* Both the 8004 and 8005 are designed for 64K Buffer memory */
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sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE;
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/*
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* Set up tx and rx buffers.
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*
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* We use approximately a third of the packet memory for TX
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* buffers and the rest for RX buffers
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*/
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sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 3;
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sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE;
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sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize;
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sc->sc_enabled = 0;
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/* Test the RAM */
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ea_ramtest(sc);
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printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB",
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sc->sc_dev.dv_xname, sc->sc_buffersize >> 10,
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sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10);
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/* Initialise ifnet structure. */
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@ -228,19 +234,61 @@ seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr)
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ifp->if_stop = ea_stop;
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ifp->if_watchdog = ea_watchdog;
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ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS;
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if (sc->sc_variant == SEEQ_8004)
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ifp->if_flags |= IFF_SIMPLEX;
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IFQ_SET_READY(&ifp->if_snd);
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/* Initialize media goo. */
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ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus);
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if (media != NULL) {
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int i;
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for (i = 0; i < nmedia; i++)
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ifmedia_add(&sc->sc_media, media[i], 0, NULL);
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ifmedia_set(&sc->sc_media, defmedia);
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} else {
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ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
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ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
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}
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/* Now we can attach the interface. */
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if_attach(ifp);
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ether_ifattach(ifp, myaddr);
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/* Test the RAM */
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ea_ramtest(sc);
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printf("\n");
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}
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/*
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* Media change callback.
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*/
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static int
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ea_mediachange(struct ifnet *ifp)
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{
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struct seeq8005_softc *sc = ifp->if_softc;
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if (sc->sc_mediachange)
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return ((*sc->sc_mediachange)(sc));
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return (EINVAL);
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}
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/*
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* Media status callback.
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*/
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static void
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ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
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{
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struct seeq8005_softc *sc = ifp->if_softc;
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if (sc->sc_enabled == 0) {
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ifmr->ifm_active = IFM_ETHER | IFM_NONE;
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ifmr->ifm_status = 0;
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return;
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}
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if (sc->sc_mediastatus)
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(*sc->sc_mediastatus)(sc, ifmr);
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}
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/*
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* Test the RAM on the ethernet card.
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@ -311,7 +359,9 @@ ea_stoptx(struct seeq8005_softc *sc)
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int timeout;
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int status;
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dprintf(("ea_stoptx()\n"));
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DPRINTF(SEEQ_DEBUG_TX, ("seeq_stoptx()\n"));
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sc->sc_enabled = 0;
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status = bus_space_read_2(iot, ioh, SEEQ_STATUS);
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if (!(status & SEEQ_STATUS_TX_ON))
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@ -324,9 +374,11 @@ ea_stoptx(struct seeq8005_softc *sc)
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timeout = 20000;
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do {
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status = bus_space_read_2(iot, ioh, SEEQ_STATUS);
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delay(1);
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} while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0);
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if (timeout == 0)
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dprintf(("ea_stoptx: timeout waiting for tx termination\n"));
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if (timeout == 0)
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log(LOG_ERR, "%s: timeout waiting for tx termination\n",
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sc->sc_dev.dv_xname);
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/* Clear any pending tx interrupt */
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bus_space_write_2(iot, ioh, SEEQ_COMMAND,
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@ -349,7 +401,7 @@ ea_stoprx(struct seeq8005_softc *sc)
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int timeout;
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int status;
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dprintf(("ea_stoprx()\n"));
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DPRINTF(SEEQ_DEBUG_RX, ("seeq_stoprx()\n"));
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status = bus_space_read_2(iot, ioh, SEEQ_STATUS);
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if (!(status & SEEQ_STATUS_RX_ON))
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@ -365,7 +417,8 @@ ea_stoprx(struct seeq8005_softc *sc)
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status = bus_space_read_2(iot, ioh, SEEQ_STATUS);
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} while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0);
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if (timeout == 0)
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dprintf(("ea_stoprx: timeout waiting for rx termination\n"));
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log(LOG_ERR, "%s: timeout waiting for rx termination\n",
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sc->sc_dev.dv_xname);
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/* Clear any pending rx interrupt */
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@ -387,7 +440,7 @@ ea_stop(struct ifnet *ifp, int disable)
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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dprintf(("ea_stop()\n"));
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DPRINTF(SEEQ_DEBUG_MISC, ("seeq_stop()\n"));
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/* Stop all IO */
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ea_stoptx(sc);
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@ -401,7 +454,13 @@ ea_stop(struct ifnet *ifp, int disable)
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sc->sc_command | SEEQ_CMD_RX_INTACK |
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SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK |
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SEEQ_CMD_BW_INTACK);
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dprintf(("st=%08x", bus_space_read_2(iot, ioh, SEEQ_STATUS)));
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if (sc->sc_variant == SEEQ_8004) {
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/* Put the chip to sleep */
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ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3);
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bus_space_write_2(iot, ioh, SEEQ_BUFWIN,
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sc->sc_config3 | SEEQ_CFG3_SLEEP);
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}
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/* Cancel any watchdog timer */
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sc->sc_ethercom.ec_if.if_timer = 0;
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@ -419,7 +478,7 @@ ea_chipreset(struct seeq8005_softc *sc)
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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dprintf(("ea_chipreset()\n"));
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DPRINTF(SEEQ_DEBUG_MISC, ("seeq_chipreset()\n"));
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/* Reset the controller. Min of 4us delay here */
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@ -429,6 +488,7 @@ ea_chipreset(struct seeq8005_softc *sc)
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sc->sc_command = 0;
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sc->sc_config1 = 0;
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sc->sc_config2 = 0;
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sc->sc_config3 = 0;
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}
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@ -482,7 +542,7 @@ ea_await_fifo_full(struct seeq8005_softc *sc)
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*/
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static void
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ea_writebuf(struct seeq8005_softc *sc, u_char *buf, u_int addr, size_t len)
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ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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@ -501,12 +561,14 @@ ea_writebuf(struct seeq8005_softc *sc, u_char *buf, u_int addr, size_t len)
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if (len % 2 != 0)
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len++;
|
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|
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ea_await_fifo_empty(sc);
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if (addr != -1) {
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ea_await_fifo_empty(sc);
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|
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ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM);
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bus_space_write_2(iot, ioh, SEEQ_COMMAND,
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sc->sc_command | SEEQ_CMD_FIFO_WRITE);
|
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bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr);
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ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM);
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bus_space_write_2(iot, ioh, SEEQ_COMMAND,
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sc->sc_command | SEEQ_CMD_FIFO_WRITE);
|
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bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr);
|
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}
|
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|
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if (len > 0)
|
||||
bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN,
|
||||
@ -526,7 +588,7 @@ ea_writebuf(struct seeq8005_softc *sc, u_char *buf, u_int addr, size_t len)
|
||||
*/
|
||||
|
||||
static void
|
||||
ea_readbuf(struct seeq8005_softc *sc, u_char *buf, u_int addr, size_t len)
|
||||
ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len)
|
||||
{
|
||||
|
||||
bus_space_tag_t iot = sc->sc_iot;
|
||||
@ -546,14 +608,16 @@ ea_readbuf(struct seeq8005_softc *sc, u_char *buf, u_int addr, size_t len)
|
||||
if (len % 2 != 0)
|
||||
len++;
|
||||
|
||||
ea_await_fifo_empty(sc);
|
||||
if (addr != -1) {
|
||||
ea_await_fifo_empty(sc);
|
||||
|
||||
ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM);
|
||||
bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr);
|
||||
bus_space_write_2(iot, ioh, SEEQ_COMMAND,
|
||||
sc->sc_command | SEEQ_CMD_FIFO_READ);
|
||||
ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM);
|
||||
bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr);
|
||||
bus_space_write_2(iot, ioh, SEEQ_COMMAND,
|
||||
sc->sc_command | SEEQ_CMD_FIFO_READ);
|
||||
|
||||
ea_await_fifo_full(sc);
|
||||
ea_await_fifo_full(sc);
|
||||
}
|
||||
|
||||
if (len > 0)
|
||||
bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN,
|
||||
@ -605,28 +669,34 @@ ea_init(struct ifnet *ifp)
|
||||
|
||||
/* Set up defaults for the registers */
|
||||
|
||||
sc->sc_command = 0x00;
|
||||
sc->sc_config1 = 0x00; /* XXX DMA settings? */
|
||||
sc->sc_command = 0;
|
||||
sc->sc_config1 = 0;
|
||||
#if BYTE_ORDER == BIG_ENDIAN
|
||||
sc->sc_config2 = SEEQ_CFG2_BYTESWAP
|
||||
sc->sc_config2 = SEEQ_CFG2_BYTESWAP;
|
||||
#else
|
||||
sc->sc_config2 = 0;
|
||||
#endif
|
||||
sc->sc_config3 = 0;
|
||||
|
||||
bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command);
|
||||
bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1);
|
||||
bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2);
|
||||
|
||||
/* Split board memory into Rx and Tx. */
|
||||
ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP);
|
||||
bus_space_write_2(iot, ioh, SEEQ_BUFWIN,
|
||||
(SEEQ_TX_BUFFER_SIZE >> 8) - 1);
|
||||
if (sc->sc_variant == SEEQ_8004) {
|
||||
ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3);
|
||||
bus_space_write_2(iot, ioh, SEEQ_BUFWIN, sc->sc_config3);
|
||||
}
|
||||
|
||||
/* Write the station address - the receiver must be off */
|
||||
ea_set_address(sc, 0, LLADDR(ifp->if_sadl));
|
||||
|
||||
/* Split board memory into Rx and Tx. */
|
||||
ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP);
|
||||
bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1);
|
||||
|
||||
if (sc->sc_variant == SEEQ_8004)
|
||||
sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE;
|
||||
|
||||
/* Configure rx. */
|
||||
dprintf(("Configuring rx...\n"));
|
||||
if (ifp->if_flags & IFF_PROMISC)
|
||||
sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS;
|
||||
else if (ifp->if_flags & IFF_ALLMULTI)
|
||||
@ -637,7 +707,7 @@ ea_init(struct ifnet *ifp)
|
||||
bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1);
|
||||
|
||||
/* Setup the Rx pointers */
|
||||
sc->sc_rx_ptr = SEEQ_TX_BUFFER_SIZE;
|
||||
sc->sc_rx_ptr = sc->sc_tx_bufsize;
|
||||
|
||||
bus_space_write_2(iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr);
|
||||
bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8);
|
||||
@ -650,12 +720,6 @@ ea_init(struct ifnet *ifp)
|
||||
bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000);
|
||||
|
||||
|
||||
/* Turn on Rx */
|
||||
sc->sc_command |= SEEQ_CMD_RX_INTEN;
|
||||
bus_space_write_2(iot, ioh, SEEQ_COMMAND,
|
||||
sc->sc_command | SEEQ_CMD_RX_ON);
|
||||
|
||||
|
||||
/* Configure TX. */
|
||||
dprintf(("Configuring tx...\n"));
|
||||
|
||||
@ -664,6 +728,10 @@ ea_init(struct ifnet *ifp)
|
||||
sc->sc_config2 |= SEEQ_CFG2_OUTPUT;
|
||||
bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2);
|
||||
|
||||
/* Reset tx buffer pointers */
|
||||
sc->sc_tx_cur = 0;
|
||||
sc->sc_tx_used = 0;
|
||||
sc->sc_tx_next = 0;
|
||||
|
||||
/* Place a NULL header at the beginning of the transmit area */
|
||||
ea_writebuf(sc, NULL, 0x0000, 0);
|
||||
@ -674,16 +742,18 @@ ea_init(struct ifnet *ifp)
|
||||
sc->sc_command |= SEEQ_CMD_TX_INTEN;
|
||||
bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command);
|
||||
|
||||
/* Turn on Rx */
|
||||
sc->sc_command |= SEEQ_CMD_RX_INTEN;
|
||||
bus_space_write_2(iot, ioh, SEEQ_COMMAND,
|
||||
sc->sc_command | SEEQ_CMD_RX_ON);
|
||||
|
||||
/* TX_ON gets set by ea_txpacket when there's something to transmit. */
|
||||
|
||||
|
||||
/* Set flags appropriately. */
|
||||
ifp->if_flags |= IFF_RUNNING;
|
||||
ifp->if_flags &= ~IFF_OACTIVE;
|
||||
|
||||
dprintf(("init: st=%04x\n",
|
||||
bus_space_read_2(iot, ioh, SEEQ_STATUS)));
|
||||
|
||||
sc->sc_enabled = 1;
|
||||
|
||||
/* And start output. */
|
||||
ea_start(ifp);
|
||||
@ -692,7 +762,6 @@ ea_init(struct ifnet *ifp)
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Start output on interface. Get datagrams from the queue and output them,
|
||||
* giving the receiver a chance between datagrams. Call only from splnet or
|
||||
@ -850,7 +919,7 @@ seeq8005intr(void *arg)
|
||||
bus_space_tag_t iot = sc->sc_iot;
|
||||
bus_space_handle_t ioh = sc->sc_ioh;
|
||||
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
|
||||
int status, s, handled;
|
||||
int status, handled;
|
||||
u_int8_t txhdr[4];
|
||||
u_int txstatus;
|
||||
|
||||
@ -881,39 +950,69 @@ seeq8005intr(void *arg)
|
||||
txstatus = txhdr[3];
|
||||
|
||||
/*
|
||||
* Did it succeed ? Did we collide ?
|
||||
* If SEEQ_TXSTAT_COLLISION is set then we received at least
|
||||
* one collision. On the 8004 we can find out exactly how many
|
||||
* collisions occurred.
|
||||
*
|
||||
* The exact proceedure here is not clear. We should get
|
||||
* an interrupt on a sucessfull tx or on a collision.
|
||||
* The done flag is set after successfull tx or 16 collisions
|
||||
* We should thus get a interrupt for each of collision
|
||||
* and the done bit should not be set. However it does appear
|
||||
* to be set at the same time as the collision bit ...
|
||||
* The SEEQ_PKTSTAT_DONE will be set if the transmission has
|
||||
* completed.
|
||||
*
|
||||
* So we will count collisions and output errors and will
|
||||
* assume that if the done bit is set the packet was
|
||||
* transmitted. Stats may be wrong if 16 collisions occur on
|
||||
* a packet as the done flag should be set but the packet
|
||||
* may not have been transmitted. so the output count might
|
||||
* not require incrementing if the 16 collisions flags is
|
||||
* set. I don;t know abou this until it happens.
|
||||
* If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions
|
||||
* occurred and the packet transmission was aborted.
|
||||
* This situation is untested as present.
|
||||
*
|
||||
* The SEEQ_TXSTAT_BABBLE should never be set and is untested
|
||||
* as we should never xmit oversized packets.
|
||||
*/
|
||||
if (txstatus & SEEQ_TXSTAT_COLLISION) {
|
||||
switch (sc->sc_variant) {
|
||||
case SEEQ_8004: {
|
||||
int colls;
|
||||
|
||||
if (txstatus & SEEQ_TXSTAT_COLLISION)
|
||||
ifp->if_collisions++;
|
||||
else if (txstatus &
|
||||
(SEEQ_TXSTAT_BABBLE | SEEQ_TXSTAT_COLLISION16))
|
||||
/*
|
||||
* The 8004 contains a 4 bit collision count
|
||||
* in the status register.
|
||||
*/
|
||||
|
||||
/* This appears to be broken on 80C04.AE */
|
||||
/* ifp->if_collisions +=
|
||||
(txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT)
|
||||
& SEEQ_TXSTAT_COLLISION_MASK;*/
|
||||
|
||||
/* Use the TX Collision register */
|
||||
ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS);
|
||||
colls = bus_space_read_1(iot, ioh,
|
||||
SEEQ_BUFWIN);
|
||||
ifp->if_collisions += colls;
|
||||
break;
|
||||
}
|
||||
case SEEQ_8005:
|
||||
/* We known there was at least 1 collision */
|
||||
ifp->if_collisions++;
|
||||
break;
|
||||
}
|
||||
} else if (txstatus & SEEQ_TXSTAT_COLLISION16) {
|
||||
printf("seeq_intr: col16 %x\n", txstatus);
|
||||
ifp->if_collisions += 16;
|
||||
ifp->if_oerrors++;
|
||||
} else if (txstatus & SEEQ_TXSTAT_BABBLE) {
|
||||
ifp->if_oerrors++;
|
||||
}
|
||||
|
||||
/* Have we completed transmission on the packet ? */
|
||||
if (txstatus & SEEQ_PKTSTAT_DONE) {
|
||||
/* Clear watchdog timer. */
|
||||
ifp->if_timer = 0;
|
||||
ifp->if_flags &= ~IFF_OACTIVE;
|
||||
|
||||
/* Update stats */
|
||||
ifp->if_opackets++;
|
||||
|
||||
/* Tx next packet */
|
||||
|
||||
s = splnet();
|
||||
eatxpacket(sc);
|
||||
splx(s);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
@ -926,11 +1025,8 @@ seeq8005intr(void *arg)
|
||||
bus_space_write_2(iot, ioh, SEEQ_COMMAND,
|
||||
sc->sc_command | SEEQ_CMD_RX_INTACK);
|
||||
|
||||
/* Install a watchdog timer needed atm to fixed rx lockups */
|
||||
ifp->if_timer = SEEQ_TIMEOUT;
|
||||
|
||||
/* Processes the received packets */
|
||||
eagetpackets(sc);
|
||||
ea_getpackets(sc);
|
||||
|
||||
|
||||
#if 0
|
||||
@ -953,7 +1049,7 @@ seeq8005intr(void *arg)
|
||||
|
||||
|
||||
void
|
||||
eagetpackets(struct seeq8005_softc *sc)
|
||||
ea_getpackets(struct seeq8005_softc *sc)
|
||||
{
|
||||
bus_space_tag_t iot = sc->sc_iot;
|
||||
bus_space_handle_t ioh = sc->sc_ioh;
|
||||
@ -997,7 +1093,7 @@ eagetpackets(struct seeq8005_softc *sc)
|
||||
len = (ptr - addr) - 4;
|
||||
|
||||
if (len < 0)
|
||||
len += SEEQ_RX_BUFFER_SIZE;
|
||||
len += sc->sc_rx_bufsize;
|
||||
|
||||
#ifdef SEEQ_RX_DEBUG
|
||||
dprintf(("len=%04x\n", len));
|
||||
@ -1012,7 +1108,7 @@ eagetpackets(struct seeq8005_softc *sc)
|
||||
* Did we have any errors? then note error and go to
|
||||
* next packet
|
||||
*/
|
||||
if (__predict_false(status & 0x0f)) {
|
||||
if (__predict_false(status & SEEQ_RXSTAT_ERROR_MASK)) {
|
||||
++ifp->if_ierrors;
|
||||
log(LOG_WARNING,
|
||||
"%s: rx packet error (%02x) - dropping packet\n",
|
||||
@ -1041,7 +1137,7 @@ eagetpackets(struct seeq8005_softc *sc)
|
||||
|
||||
ifp->if_ipackets++;
|
||||
/* Pass data up to upper levels. */
|
||||
earead(sc, addr + 4, len);
|
||||
ea_read(sc, addr + 4, len);
|
||||
|
||||
addr = ptr;
|
||||
++pack;
|
||||
@ -1071,7 +1167,7 @@ eagetpackets(struct seeq8005_softc *sc)
|
||||
*/
|
||||
|
||||
static void
|
||||
earead(struct seeq8005_softc *sc, int addr, int len)
|
||||
ea_read(struct seeq8005_softc *sc, int addr, int len)
|
||||
{
|
||||
struct mbuf *m;
|
||||
struct ifnet *ifp;
|
||||
@ -1079,7 +1175,7 @@ earead(struct seeq8005_softc *sc, int addr, int len)
|
||||
ifp = &sc->sc_ethercom.ec_if;
|
||||
|
||||
/* Pull packet off interface. */
|
||||
m = eaget(sc, addr, len, ifp);
|
||||
m = ea_get(sc, addr, len, ifp);
|
||||
if (m == 0)
|
||||
return;
|
||||
|
||||
@ -1107,7 +1203,7 @@ earead(struct seeq8005_softc *sc, int addr, int len)
|
||||
*/
|
||||
|
||||
struct mbuf *
|
||||
eaget(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp)
|
||||
ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp)
|
||||
{
|
||||
struct mbuf *top, **mp, *m;
|
||||
int len;
|
||||
@ -1162,8 +1258,8 @@ eaget(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp)
|
||||
m->m_data = newdata;
|
||||
}
|
||||
ea_readbuf(sc, mtod(m, u_char *),
|
||||
cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - SEEQ_RX_BUFFER_SIZE,
|
||||
len);
|
||||
cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize,
|
||||
len);
|
||||
cp += len;
|
||||
*mp = m;
|
||||
mp = &m->m_next;
|
||||
@ -1205,15 +1301,104 @@ ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
|
||||
}
|
||||
|
||||
/* Must be called at splnet() */
|
||||
|
||||
static void
|
||||
ea_mc_reset(struct seeq8005_softc *sc)
|
||||
{
|
||||
|
||||
switch (sc->sc_variant) {
|
||||
case SEEQ_8004:
|
||||
ea_mc_reset_8004(sc);
|
||||
return;
|
||||
case SEEQ_8005:
|
||||
ea_mc_reset_8005(sc);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
ea_mc_reset_8004(struct seeq8005_softc *sc)
|
||||
{
|
||||
struct ethercom *ec = &sc->sc_ethercom;
|
||||
struct ifnet *ifp = &ec->ec_if;
|
||||
struct ether_multi *enm;
|
||||
u_int8_t *cp, c;
|
||||
u_int32_t crc;
|
||||
int i, len;
|
||||
struct ether_multistep step;
|
||||
u_int8_t af[8];
|
||||
|
||||
/*
|
||||
* Set up multicast address filter by passing all multicast addresses
|
||||
* through a crc generator, and then using bits 2 - 7 as an index
|
||||
* into the 64 bit logical address filter. The high order bits
|
||||
* selects the word, while the rest of the bits select the bit within
|
||||
* the word.
|
||||
*/
|
||||
|
||||
if (ifp->if_flags & IFF_PROMISC) {
|
||||
ifp->if_flags |= IFF_ALLMULTI;
|
||||
for (i = 0; i < 8; i++)
|
||||
af[i] = 0xff;
|
||||
return;
|
||||
}
|
||||
for (i = 0; i < 8; i++)
|
||||
af[i] = 0;
|
||||
ETHER_FIRST_MULTI(step, ec, enm);
|
||||
while (enm != NULL) {
|
||||
if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
|
||||
sizeof(enm->enm_addrlo)) != 0) {
|
||||
/*
|
||||
* We must listen to a range of multicast addresses.
|
||||
* For now, just accept all multicasts, rather than
|
||||
* trying to set only those filter bits needed to match
|
||||
* the range. (At this time, the only use of address
|
||||
* ranges is for IP multicast routing, for which the
|
||||
* range is big enough to require all bits set.)
|
||||
*/
|
||||
ifp->if_flags |= IFF_ALLMULTI;
|
||||
for (i = 0; i < 8; i++)
|
||||
af[i] = 0xff;
|
||||
return;
|
||||
}
|
||||
cp = enm->enm_addrlo;
|
||||
crc = 0xffffffff;
|
||||
for (len = sizeof(enm->enm_addrlo); --len >= 0;) {
|
||||
c = *cp++;
|
||||
for (i = 8; --i >= 0;) {
|
||||
if (((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01)) {
|
||||
crc <<= 1;
|
||||
crc ^= 0x04c11db6 | 1;
|
||||
} else
|
||||
crc <<= 1;
|
||||
c >>= 1;
|
||||
}
|
||||
}
|
||||
/* Just want the 6 most significant bits. */
|
||||
crc = (crc >> 2) & 0x3f;
|
||||
|
||||
/* Turn on the corresponding bit in the filter. */
|
||||
af[crc >> 3] |= 1 << (crc & 0x7);
|
||||
|
||||
ETHER_NEXT_MULTI(step, enm);
|
||||
}
|
||||
ifp->if_flags &= ~IFF_ALLMULTI;
|
||||
|
||||
ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST);
|
||||
for (i = 0; i < 8; ++i)
|
||||
bus_space_write_1(sc->sc_iot, sc->sc_ioh,
|
||||
SEEQ_BUFWIN, af[i]);
|
||||
}
|
||||
|
||||
static void
|
||||
ea_mc_reset_8005(struct seeq8005_softc *sc)
|
||||
{
|
||||
struct ether_multi *enm;
|
||||
struct ether_multistep step;
|
||||
int naddr, maxaddrs;
|
||||
|
||||
naddr = 0;
|
||||
maxaddrs = (sc->sc_flags & SEEQ8005_80C04) ? 5 : 0;
|
||||
maxaddrs = 5;
|
||||
ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm);
|
||||
while (enm != NULL) {
|
||||
/* Have we got space? */
|
||||
@ -1223,13 +1408,13 @@ ea_mc_reset(struct seeq8005_softc *sc)
|
||||
ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL);
|
||||
return;
|
||||
}
|
||||
ea_set_address(sc, naddr, enm->enm_addrlo);
|
||||
sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0 << naddr;
|
||||
ea_set_address(sc, 1 + naddr, enm->enm_addrlo);
|
||||
sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr;
|
||||
naddr++;
|
||||
ETHER_NEXT_MULTI(step, enm);
|
||||
}
|
||||
for (; naddr < maxaddrs; naddr++)
|
||||
sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR0 << naddr);
|
||||
sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr);
|
||||
bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1,
|
||||
sc->sc_config1);
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: seeq8005var.h,v 1.2 2000/09/21 22:20:38 bjh21 Exp $ */
|
||||
/* $NetBSD: seeq8005var.h,v 1.3 2001/03/24 20:38:41 bjh21 Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000 Ben Harris
|
||||
@ -36,27 +36,52 @@
|
||||
#ifndef _SEEQ8005VAR_H_
|
||||
#define _SEEQ8005VAR_H_
|
||||
|
||||
#include <net/if_media.h>
|
||||
|
||||
/* Enumerate the possible cip variants */
|
||||
enum seeq_variant {
|
||||
SEEQ_8004, SEEQ_8005
|
||||
};
|
||||
|
||||
/*
|
||||
* per-line info and status
|
||||
*/
|
||||
|
||||
struct seeq8005_softc {
|
||||
struct device sc_dev;
|
||||
|
||||
/* These fields should be initialised by the board driver. */
|
||||
bus_space_tag_t sc_iot; /* I/O base addr */
|
||||
bus_space_handle_t sc_ioh;
|
||||
|
||||
int (*sc_mediachange)(struct seeq8005_softc *);
|
||||
void (*sc_mediastatus)(struct seeq8005_softc *, struct ifmediareq *);
|
||||
|
||||
/* These fields are used internally by the seeq8005 driver. */
|
||||
struct ethercom sc_ethercom; /* Ethernet common */
|
||||
struct ifmedia sc_media; /* supported media information */
|
||||
|
||||
int sc_config1; /* Current config1 bits */
|
||||
int sc_config2; /* Current config2 bits */
|
||||
int sc_config3; /* Current config3 bits 8004 only */
|
||||
int sc_command; /* Current command bits */
|
||||
u_int sc_rx_ptr; /* Receive buffer pointer */
|
||||
u_int sc_tx_ptr; /* Transmit buffer pointer */
|
||||
u_int sc_flags; /* Assorted flags: */
|
||||
#define SEEQ8005_80C04 0x01 /* Chip is actually an 80C04. */
|
||||
|
||||
u_int sc_tx_bufs; /* Number of tx buffers */
|
||||
u_int sc_tx_used; /* Number of tx buffers in use */
|
||||
u_int sc_tx_cur; /* Next tx buffer to transmit */
|
||||
u_int sc_tx_next; /* Next tx buffer to fill */
|
||||
|
||||
u_int sc_buffersize; /* Size of packet buffer */
|
||||
u_int sc_tx_bufsize; /* Size of TX packet buffer */
|
||||
u_int sc_rx_bufsize; /* Size of RX packet buffer */
|
||||
|
||||
int sc_enabled; /* Enabled state */
|
||||
enum seeq_variant sc_variant; /* Chip variant */
|
||||
};
|
||||
|
||||
extern void seeq8005_attach(struct seeq8005_softc *, const u_int8_t *);
|
||||
extern void seeq8005_attach(struct seeq8005_softc *, const u_int8_t *, int *,
|
||||
int, int);
|
||||
extern int seeq8005intr(void *);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user