De-obfuscate somewhat; define and use register bit constants, etc.
This commit is contained in:
thorpej
parent
709cef492e
commit
b8e4c037bd
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@ -1,4 +1,4 @@
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/* $NetBSD: pvr.c,v 1.11 2002/03/24 18:21:23 uch Exp $ */
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/* $NetBSD: pvr.c,v 1.12 2002/05/03 04:42:08 thorpej Exp $ */
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/*-
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* Copyright (c) 2001 Marcus Comstedt.
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@ -65,7 +65,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: pvr.c,v 1.11 2002/03/24 18:21:23 uch Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pvr.c,v 1.12 2002/05/03 04:42:08 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -75,6 +75,7 @@ __KERNEL_RCSID(0, "$NetBSD: pvr.c,v 1.11 2002/03/24 18:21:23 uch Exp $");
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#include <sys/buf.h>
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#include <sys/ioctl.h>
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#include <machine/vmparam.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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@ -93,9 +94,76 @@ __KERNEL_RCSID(0, "$NetBSD: pvr.c,v 1.11 2002/03/24 18:21:23 uch Exp $");
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#include "mkbd.h"
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#define PVRREG_FBSTART 0x05000000
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#define PVRREG_REGSTART 0x005f8000
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#define PVRREG_BRDCOLR 0x40
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#define BRDCOLR_BLUE(x) ((x) << 0)
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#define BRDCOLR_GREEN(x) ((x) << 8)
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#define BRDCOLR_RED(x) ((x) << 16)
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#define PVRREG_DIWMODE 0x44
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#define DIWMODE_DE (1U << 0) /* display enable */
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#define DIWMODE_SD (1U << 1) /* scan double enable */
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#define DIWMODE_COL(x) ((x) << 2)
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#define DIWMODE_COL_RGB555 DIWMODE_COL(0) /* RGB555, 16-bit */
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#define DIWMODE_COL_RGB565 DIWMODE_COL(1) /* RGB565, 16-bit */
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#define DIWMODE_COL_RGB888 DIWMODE_COL(2) /* RGB888, 24-bit */
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#define DIWMODE_COL_ARGB888 DIWMODE_COL(3) /* RGB888, 32-bit */
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#define DIWMODE_C (1U << 23) /* 2x clock enable (VGA) */
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#define PVRREG_DIWADDRL 0x50
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#define PVRREG_DIWADDRS 0x54
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#define PVRREG_DIWSIZE 0x5c
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#define DIWSIZE_DPL(x) ((x) << 0) /* pixel data per line */
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#define DIWSIZE_LPF(x) ((x) << 10) /* lines per field */
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#define DIWSIZE_MODULO(x) ((x) << 20) /* words to skip + 1 */
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#define PVRREG_RASEVTPOS 0xcc
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#define RASEVTPOS_BOTTOM(x) ((x) << 0)
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#define RASEVTPOS_TOP(x) ((x) << 16)
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#define PVRREG_SYNCCONF 0xd0
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#define SYNCCONF_VP (1U << 0) /* V-sync polarity */
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#define SYNCCONF_HP (1U << 1) /* H-sync polarity */
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#define SYNCCONF_I (1U << 4) /* interlace */
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#define SYNCCONF_BC(x) (1U << 6) /* broadcast standard */
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#define SYNCCONF_VO (1U << 8) /* video output enable */
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#define PVRREG_BRDHORZ 0xd4
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#define BRDHORZ_STOP(x) ((x) << 0)
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#define BRDHORZ_START(x) ((x) << 16)
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#define PVRREG_SYNCSIZE 0xd8
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#define SYNCSIZE_H(x) ((x) << 0)
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#define SYNCSIZE_V(x) ((x) << 16)
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#define PVRREG_BRDVERT 0xdc
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#define BRDVERT_STOP(x) ((x) << 0)
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#define BRDVERT_START(x) ((x) << 16)
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#define PVRREG_DIWCONF 0xe8
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#define DIWCONF_LR (1U << 8) /* low-res */
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#define DIWCONF_MAGIC (22 << 16)
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#define PVRREG_DIWHSTRT 0xec
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#define PVRREG_DIWVSTRT 0xf0
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#define DIWVSTRT_V1(x) ((x) << 0)
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#define DIWVSTRT_V2(x) ((x) << 16)
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#define PVR_REG_READ(dc, reg) \
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((__volatile uint32_t *)(dc)->dc_regvaddr)[(reg) >> 2]
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#define PVR_REG_WRITE(dc, reg, val) \
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((__volatile uint32_t *)(dc)->dc_regvaddr)[(reg) >> 2] = (val)
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struct fb_devconfig {
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vaddr_t dc_vaddr; /* framebuffer virtual address */
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vaddr_t dc_paddr; /* framebuffer physical address */
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vaddr_t dc_regvaddr; /* registers virtual address */
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vaddr_t dc_regpaddr; /* registers physical address */
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int dc_wid; /* width of frame buffer */
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int dc_ht; /* height of frame buffer */
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int dc_depth; /* depth, bits per pixel */
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@ -182,9 +250,12 @@ pvr_getdevconfig(struct fb_devconfig *dc)
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{
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int i, cookie;
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dc->dc_paddr = 0x05000000;
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dc->dc_paddr = PVRREG_FBSTART;
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dc->dc_vaddr = SH3_PHYS_TO_P2SEG(dc->dc_paddr);
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dc->dc_regpaddr = PVRREG_REGSTART;
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dc->dc_regvaddr = SH3_PHYS_TO_P2SEG(dc->dc_regpaddr);
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dc->dc_wid = 640;
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dc->dc_ht = 480;
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dc->dc_depth = 16;
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@ -398,6 +469,7 @@ pvr_check_cable(struct fb_devconfig *dc)
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static void
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pvr_check_tvsys(struct fb_devconfig *dc)
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{
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/* XXX should use flashmem device when one exists */
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dc->dc_tvsystem = (*(__volatile u_int8_t *)0xa021a004) & 3;
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}
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@ -405,60 +477,111 @@ pvr_check_tvsys(struct fb_devconfig *dc)
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void
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pvrinit(struct fb_devconfig *dc)
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{
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__volatile u_int32_t *pvr = (__volatile u_int32_t *)
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SH3_PHYS_TO_P2SEG(0x005f8000);
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int display_lines_per_field = 240;
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int v_absolute_size = 525;
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int h_absolute_size = 857;
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int modulo = 1, voffset, hoffset = 164, border = (126 << 16) | 837;
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int display_lines_per_field;
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int v_absolute_size;
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int h_absolute_size;
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int vborder_start, vborder_stop;
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int hborder_start, hborder_stop;
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int modulo = 1, voffset, hoffset;
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pvr_check_cable(dc);
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pvr_check_tvsys(dc);
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pvr[8/4] = 0; /* reset */
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pvr[0x40/4] = 0; /* black border */
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PVR_REG_WRITE(dc, 8, 0); /* reset */
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PVR_REG_WRITE(dc, PVRREG_BRDCOLR, 0); /* black border */
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if (dc->dc_dispflags & PVR_VGAMODE) {
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pvr[0x44/4] = 0x800004; /* 31kHz, RGB565 */
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pvr[0xd0/4] = 0x100; /* video output */
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v_absolute_size = 524;
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h_absolute_size = 857;
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display_lines_per_field = 480;
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hoffset = 164;
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voffset = 36;
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hborder_start = 126;
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hborder_stop = 837;
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vborder_start = 40;
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vborder_stop = 444; /* XXX */
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/* 31kHz, RGB565 */
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PVR_REG_WRITE(dc, PVRREG_DIWMODE,
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DIWMODE_C | DIWMODE_COL_RGB565);
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/* video output */
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PVR_REG_WRITE(dc, PVRREG_SYNCCONF, SYNCCONF_VO);
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} else {
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if(dc->dc_tvsystem & 1) {
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/* 50 Hz */
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v_absolute_size = 625;
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if (dc->dc_tvsystem & 1) {
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/* 50 Hz PAL */
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v_absolute_size = 624;
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h_absolute_size = 863;
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display_lines_per_field = 240;
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hoffset = 174;
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border = (116 << 16) | 843;
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voffset = 18;
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hborder_start = 116;
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hborder_stop = 843;
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vborder_start = 44;
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vborder_stop = 536; /* XXX */
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} else {
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/* 60 Hz NTSC */
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v_absolute_size = 524;
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h_absolute_size = 857;
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display_lines_per_field = 240;
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hoffset = 170;
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voffset = 28;
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hborder_start = 126;
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hborder_stop = 837;
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vborder_start = 18;
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vborder_stop = 506; /* XXX */
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}
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pvr[0x44/4] = 0x000004; /* 15kHz, RGB565 */
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/* video output, PAL/NTSC, interlace */
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pvr[0xd0/4] = 0x110|(dc->dc_tvsystem<<6);
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modulo += 640 * 2 / 4; /* interlace -> skip every other line */
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voffset = 18;
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/* 15kHz, RGB565 */
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PVR_REG_WRITE(dc, PVRREG_DIWMODE,
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DIWMODE_COL_RGB565);
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/* video output, PAL/NTSC, interlace */
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PVR_REG_WRITE(dc, PVRREG_SYNCCONF,
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SYNCCONF_VO | SYNCCONF_I | SYNCCONF_BC(dc->dc_tvsystem));
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}
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pvr[0x50/4] = 0; /* video base address, long field */
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pvr[0x54/4] = 640 * 2; /* video base address, short field */
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/* video base address, long field */
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PVR_REG_WRITE(dc, PVRREG_DIWADDRL, 0);
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pvr[0x5c/4] = (modulo << 20) | ((display_lines_per_field - 1) << 10) |
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(640 * 2 / 4 - 1);
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/* video base address, short field */
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PVR_REG_WRITE(dc, PVRREG_DIWADDRS, 640 * 2);
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voffset = (voffset << 16) | voffset;
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/* video size */
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PVR_REG_WRITE(dc, PVRREG_DIWSIZE, DIWSIZE_MODULO(modulo) |
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DIWSIZE_LPF(display_lines_per_field - 1) |
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DIWSIZE_DPL(640 * 2 / 4 - 1));
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pvr[0xf0/4] = voffset; /* V start */
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pvr[0xdc/4] = voffset + display_lines_per_field;/* V border */
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pvr[0xec/4] = hoffset; /* H start */
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pvr[0xd8/4] = (v_absolute_size<<16) | h_absolute_size; /* HV counter */
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pvr[0xd4/4] = border; /* H border */
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pvr[0xe8/4] = 22 << 16;
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PVR_REG_WRITE(dc, PVRREG_DIWVSTRT, /* V start */
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DIWVSTRT_V1(voffset) | DIWVSTRT_V2(voffset));
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PVR_REG_WRITE(dc, PVRREG_BRDVERT, /* V border */
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BRDVERT_START(vborder_start) | BRDVERT_STOP(vborder_stop));
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PVR_REG_WRITE(dc, PVRREG_DIWHSTRT, hoffset); /* H start */
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PVR_REG_WRITE(dc, PVRREG_SYNCSIZE, /* HV counter */
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SYNCSIZE_V(v_absolute_size) | SYNCSIZE_H(h_absolute_size));
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PVR_REG_WRITE(dc, PVRREG_BRDHORZ, /* H border */
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BRDHORZ_START(hborder_start) | BRDHORZ_STOP(hborder_stop));
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PVR_REG_WRITE(dc, PVRREG_DIWCONF, DIWCONF_MAGIC);
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/* RGB / composite */
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*(__volatile u_int32_t *)
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SH3_PHYS_TO_P2SEG(0x00702c00) =
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((dc->dc_dispflags & PVR_RGBMODE) ? 0 : 3) << 8;
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pvr[0x44/4] |= 1; /* display on */
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/* display on */
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PVR_REG_WRITE(dc, PVRREG_DIWMODE,
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PVR_REG_READ(dc, PVRREG_DIWMODE) | DIWMODE_DE);
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}
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/* Console support. */
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