Pull up following revision(s) (requested by martin in ticket #189):
sys/dev/ic/dwc_gmac.c: revision 1.1-1.24 sys/dev/ic/dwc_gmac_reg.h: revision 1.1-1.12 sys/dev/ic/dwc_gmac_var.h: revision 1.1-1.5 Add support for Synopsis Designware GMAC ethernet core, as found on various Allwiner boards and used by the awge(4) driver.
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snj
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/* $NetBSD: dwc_gmac_reg.h,v 1.12.2.2 2014/11/09 19:06:57 snj Exp $ */
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/*-
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* Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry and Martin Husemann.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define AWIN_GMAC_MAC_CONF 0x0000
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#define AWIN_GMAC_MAC_FFILT 0x0004
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#define AWIN_GMAC_MAC_HTHIGH 0x0008
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#define AWIN_GMAC_MAC_HTLOW 0x000c
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#define AWIN_GMAC_MAC_MIIADDR 0x0010
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#define AWIN_GMAC_MAC_MIIDATA 0x0014
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#define AWIN_GMAC_MAC_FLOWCTRL 0x0018
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#define AWIN_GMAC_MAC_VLANTAG 0x001c
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#define AWIN_GMAC_MAC_VERSION 0x0020 /* not always implemented? */
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#define AWIN_GMAC_MAC_INTR 0x0038
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#define AWIN_GMAC_MAC_INTMASK 0x003c
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#define AWIN_GMAC_MAC_ADDR0HI 0x0040
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#define AWIN_GMAC_MAC_ADDR0LO 0x0044
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#define AWIN_GMAC_MII_STATUS 0x00D8
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#define AWIN_GMAC_MAC_CONF_FRAMEBURST __BIT(21) /* allow TX frameburst when
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in half duplex mode */
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#define AWIN_GMAC_MAC_CONF_MIISEL __BIT(15) /* select MII phy */
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#define AWIN_GMAC_MAC_CONF_FES100 __BIT(14) /* 100 mbit mode */
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#define AWIN_GMAC_MAC_CONF_DISABLERXOWN __BIT(13) /* do not receive our own
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TX frames in half duplex
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mode */
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#define AWIN_GMAC_MAC_CONF_FULLDPLX __BIT(11) /* select full duplex */
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#define AWIN_GMAC_MAC_CONF_TXENABLE __BIT(3) /* enable TX dma engine */
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#define AWIN_GMAC_MAC_CONF_RXENABLE __BIT(2) /* enable RX dma engine */
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#define AWIN_GMAC_MAC_FFILT_RA __BIT(31) /* receive all mode */
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#define AWIN_GMAC_MAC_FFILT_HPF __BIT(10) /* hash or perfect filter */
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#define AWIN_GMAC_MAC_FFILT_SAF __BIT(9) /* source address filter */
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#define AWIN_GMAC_MAC_FFILT_SAIF __BIT(8) /* inverse filtering */
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#define AWIN_GMAC_MAC_FFILT_DBF __BIT(5) /* disable broadcast frames */
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#define AWIN_GMAC_MAC_FFILT_PM __BIT(4) /* promiscious multicast */
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#define AWIN_GMAC_MAC_FFILT_DAIF __BIT(3) /* DA inverse filtering */
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#define AWIN_GMAC_MAC_FFILT_HMC __BIT(2) /* multicast hash compare */
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#define AWIN_GMAC_MAC_FFILT_HUC __BIT(1) /* unicast hash compare */
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#define AWIN_GMAC_MAC_FFILT_PR __BIT(0) /* promiscious mode */
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#define AWIN_GMAC_MAC_INT_LPI __BIT(10)
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#define AWIN_GMAC_MAC_INT_TSI __BIT(9)
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#define AWIN_GMAC_MAC_INT_ANEG __BIT(2)
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#define AWIN_GMAC_MAC_INT_LINKCHG __BIT(1)
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#define AWIN_GMAC_MAC_INT_RGSMII __BIT(0)
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#define AWIN_GMAC_DMA_BUSMODE 0x1000
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#define AWIN_GMAC_DMA_TXPOLL 0x1004
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#define AWIN_GMAC_DMA_RXPOLL 0x1008
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#define AWIN_GMAC_DMA_RX_ADDR 0x100c
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#define AWIN_GMAC_DMA_TX_ADDR 0x1010
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#define AWIN_GMAC_DMA_STATUS 0x1014
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#define AWIN_GMAC_DMA_OPMODE 0x1018
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#define AWIN_GMAC_DMA_INTENABLE 0x101c
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#define AWIN_GMAC_DMA_CUR_TX_DESC 0x1048
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#define AWIN_GMAC_DMA_CUR_RX_DESC 0x104c
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#define AWIN_GMAC_DMA_CUR_TX_BUFADDR 0x1050
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#define AWIN_GMAC_DMA_CUR_RX_BUFADDR 0x1054
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#define AWIN_GMAC_DMA_HWFEATURES 0x1058 /* not always implemented? */
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#define GMAC_MII_PHY_SHIFT 11
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#define GMAC_MII_PHY_MASK __BITS(15,11)
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#define GMAC_MII_REG_SHIFT 6
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#define GMAC_MII_REG_MASK __BITS(10,6)
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#define GMAC_MII_BUSY __BIT(0)
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#define GMAC_MII_WRITE __BIT(1)
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#define GMAC_MII_CLK_60_100M_DIV42 0x0
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#define GMAC_MII_CLK_100_150M_DIV62 0x1
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#define GMAC_MII_CLK_25_35M_DIV16 0x2
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#define GMAC_MII_CLK_35_60M_DIV26 0x3
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#define GMAC_MII_CLK_150_250M_DIV102 0x4
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#define GMAC_MII_CLK_250_300M_DIV124 0x5
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#define GMAC_MII_CLK_DIV4 0x8
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#define GMAC_MII_CLK_DIV6 0x9
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#define GMAC_MII_CLK_DIV8 0xa
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#define GMAC_MII_CLK_DIV10 0xb
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#define GMAC_MII_CLK_DIV12 0xc
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#define GMAC_MII_CLK_DIV14 0xd
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#define GMAC_MII_CLK_DIV16 0xe
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#define GMAC_MII_CLK_DIV18 0xf
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#define GMAC_MII_CLKMASK __BITS(5,2)
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#define GMAC_BUSMODE_FIXEDBURST __BIT(16)
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#define GMAC_BUSMODE_PRIORXTX __BITS(15,14)
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#define GMAC_BUSMODE_PRIORXTX_41 3
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#define GMAC_BUSMODE_PRIORXTX_31 2
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#define GMAC_BUSMODE_PRIORXTX_21 1
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#define GMAC_BUSMODE_PRIORXTX_11 0
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#define GMCA_BUSMODE_PBL __BITS(13,8) /* possible DMA
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burst len */
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#define GMAC_BUSMODE_RESET __BIT(0)
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#define AWIN_GMAC_MII_IRQ __BIT(0)
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#define GMAC_DMA_OP_STOREFORWARD __BIT(21) /* start TX when a
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full frame is available */
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#define GMAC_DMA_OP_FLUSHTX __BIT(20) /* flush TX fifo */
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#define GMAC_DMA_OP_TXSTART __BIT(13) /* start TX DMA engine */
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#define GMAC_DMA_OP_RXSTART __BIT(1) /* start RX DMA engine */
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#define GMAC_DMA_INT_NIE __BIT(16) /* Normal/Summary */
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#define GMAC_DMA_INT_AIE __BIT(15) /* Abnormal/Summary */
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#define GMAC_DMA_INT_ERE __BIT(14) /* Early receive */
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#define GMAC_DMA_INT_FBE __BIT(13) /* Fatal bus error */
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#define GMAC_DMA_INT_ETE __BIT(10) /* Early transmit */
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#define GMAC_DMA_INT_RWE __BIT(9) /* Receive watchdog */
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#define GMAC_DMA_INT_RSE __BIT(8) /* Receive stopped */
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#define GMAC_DMA_INT_RUE __BIT(7) /* Receive buffer unavail. */
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#define GMAC_DMA_INT_RIE __BIT(6) /* Receive interrupt */
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#define GMAC_DMA_INT_UNE __BIT(5) /* Tx underflow */
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#define GMAC_DMA_INT_OVE __BIT(4) /* Receive overflow */
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#define GMAC_DMA_INT_TJE __BIT(3) /* Transmit jabber */
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#define GMAC_DMA_INT_TUE __BIT(2) /* Transmit buffer unavail. */
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#define GMAC_DMA_INT_TSE __BIT(1) /* Transmit stopped */
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#define GMAC_DMA_INT_TIE __BIT(0) /* Transmit interrupt */
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#define GMAC_DMA_INT_MASK __BITS(0,16) /* all possible intr bits */
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struct dwc_gmac_dev_dmadesc {
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uint32_t ddesc_status;
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/* both: */
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#define DDESC_STATUS_OWNEDBYDEV __BIT(31)
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/* for RX descriptors */
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#define DDESC_STATUS_DAFILTERFAIL __BIT(30)
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#define DDESC_STATUS_FRMLENMSK __BITS(29,16)
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#define DDESC_STATUS_FRMLENSHIFT 16
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#define DDESC_STATUS_RXERROR __BIT(15)
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#define DDESC_STATUS_RXTRUNCATED __BIT(14)
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#define DDESC_STATUS_SAFILTERFAIL __BIT(13)
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#define DDESC_STATUS_RXIPC_GIANTFRAME __BIT(12)
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#define DDESC_STATUS_RXDAMAGED __BIT(11)
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#define DDESC_STATUS_RXVLANTAG __BIT(10)
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#define DDESC_STATUS_RXFIRST __BIT(9)
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#define DDESC_STATUS_RXLAST __BIT(8)
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#define DDESC_STATUS_RXIPC_GIANT __BIT(7)
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#define DDESC_STATUS_RXCOLLISION __BIT(6)
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#define DDESC_STATUS_RXFRAMEETHER __BIT(5)
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#define DDESC_STATUS_RXWATCHDOG __BIT(4)
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#define DDESC_STATUS_RXMIIERROR __BIT(3)
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#define DDESC_STATUS_RXDRIBBLING __BIT(2)
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#define DDESC_STATUS_RXCRC __BIT(1)
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uint32_t ddesc_cntl;
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/* for TX descriptors */
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#define DDESC_CNTL_TXINT __BIT(31)
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#define DDESC_CNTL_TXLAST __BIT(30)
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#define DDESC_CNTL_TXFIRST __BIT(29)
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#define DDESC_CNTL_TXCHECKINSCTRL __BIT(27)
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#define DDESC_CNTL_TXCRCDIS __BIT(26)
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#define DDESC_CNTL_TXRINGEND __BIT(25)
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#define DDESC_CNTL_TXCHAIN __BIT(24)
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/* for RX descriptors */
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#define DDESC_CNTL_RXINTDIS __BIT(31)
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#define DDESC_CNTL_RXRINGEND __BIT(25)
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#define DDESC_CNTL_RXCHAIN __BIT(24)
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/* both */
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#define DDESC_CNTL_SIZE1MASK __BITS(10,0)
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#define DDESC_CNTL_SIZE1SHIFT 0
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#define DDESC_CNTL_SIZE2MASK __BITS(21,11)
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#define DDESC_CNTL_SIZE2SHIFT 11
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uint32_t ddesc_data; /* pointer to buffer data */
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uint32_t ddesc_next; /* link to next descriptor */
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};
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@ -0,0 +1,94 @@
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/* $NetBSD: dwc_gmac_var.h,v 1.5.2.2 2014/11/09 19:06:57 snj Exp $ */
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/*-
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* Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry and Martin Husemann.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* We could use 1024 DMA descriptors to fill up an 8k page (each is 16 byte).
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* However, on TX we probably will not need that many, and on RX we allocate
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* a full mbuf cluster for each, so secondary memory consumption will grow
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* rapidly.
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* So currently we waste half a page of dma memory and consume 512k Byte of
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* RAM for mbuf clusters.
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* XXX Maybe fine-tune later, or reconsider unsharing of RX/TX dmamap.
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*/
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#define AWGE_RX_RING_COUNT 256
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#define AWGE_TX_RING_COUNT 256
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#define AWGE_TOTAL_RING_COUNT \
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(AWGE_RX_RING_COUNT + AWGE_TX_RING_COUNT)
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#define AWGE_MAX_PACKET (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)
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struct dwc_gmac_rx_data {
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bus_dmamap_t rd_map;
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struct mbuf *rd_m;
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};
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struct dwc_gmac_tx_data {
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bus_dmamap_t td_map;
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bus_dmamap_t td_active;
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struct mbuf *td_m;
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};
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struct dwc_gmac_tx_ring {
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bus_addr_t t_physaddr; /* PA of TX ring start */
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struct dwc_gmac_dev_dmadesc *t_desc; /* VA of TX ring start */
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struct dwc_gmac_tx_data t_data[AWGE_TX_RING_COUNT];
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int t_cur, t_next, t_queued;
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};
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struct dwc_gmac_rx_ring {
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bus_addr_t r_physaddr; /* PA of RX ring start */
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struct dwc_gmac_dev_dmadesc *r_desc; /* VA of RX ring start */
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struct dwc_gmac_rx_data r_data[AWGE_RX_RING_COUNT];
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int r_cur, r_next;
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kmutex_t r_mtx;
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};
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struct dwc_gmac_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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bus_dma_tag_t sc_dmat;
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struct ethercom sc_ec;
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struct mii_data sc_mii;
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kmutex_t sc_mdio_lock;
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bus_dmamap_t sc_dma_ring_map; /* common dma memory for RX */
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bus_dma_segment_t sc_dma_ring_seg; /* and TX ring */
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struct dwc_gmac_rx_ring sc_rxq;
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struct dwc_gmac_tx_ring sc_txq;
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short sc_if_flags; /* shadow of ether flags */
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uint16_t sc_mii_clk;
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};
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void dwc_gmac_attach(struct dwc_gmac_softc*, uint32_t /*mii_clk*/);
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int dwc_gmac_intr(struct dwc_gmac_softc*);
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