support OpenPIC variant found in PowerMac G5s
from Phileas Fogg
This commit is contained in:
macallan
parent
ddb0cef57c
commit
b762205fe6
@ -1,4 +1,4 @@
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# $NetBSD: files.macppc,v 1.99 2012/01/24 04:33:11 macallan Exp $
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# $NetBSD: files.macppc,v 1.100 2013/04/18 16:42:46 macallan Exp $
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#
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# macppc-specific configuration info
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@ -25,13 +25,16 @@ file arch/macppc/dev/dbdma.c
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# interrupt controllers
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define pic_ohare
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define pic_heathrow
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define pic_u3_ht
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defflag opt_interrupt.h PIC_OHARE: pic_ohare
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defflag opt_interrupt.h OHARE_DEBUG
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defflag opt_interrupt.h PIC_HEATHROW: pic_heathrow
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defflag opt_interrupt.h PIC_U3_HT: pic_u3_ht
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file arch/macppc/macppc/pic_ohare.c pic_ohare needs-flag
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file arch/macppc/macppc/pic_heathrow.c pic_heathrow needs-flag
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file arch/macppc/macppc/pic_u3_ht.c pic_u3_ht needs-flag
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# IPI interface
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define ipi_hammerhead
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@ -108,7 +111,7 @@ device grackle: pcibus, pic_heathrow
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attach grackle at mainbus
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file arch/macppc/pci/grackle.c grackle
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device uninorth: pcibus, pic_openpic, ipi_openpic
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device uninorth: pcibus, pic_openpic, ipi_openpic, pic_u3_ht
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attach uninorth at mainbus
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file arch/macppc/pci/uninorth.c uninorth
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@ -121,7 +124,7 @@ file arch/macppc/dev/uni-n.c uni_n
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include "dev/usb/files.usb"
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include "dev/bluetooth/files.bluetooth"
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device ibmcpc: pcibus, pic_openpic, ipi_openpic
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device ibmcpc: pcibus, pic_openpic, ipi_openpic, pic_u3_ht
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attach ibmcpc at mainbus
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file arch/macppc/pci/u3.c ibmcpc
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.h,v 1.30 2011/06/17 23:36:17 matt Exp $ */
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/* $NetBSD: intr.h,v 1.31 2013/04/18 16:42:46 macallan Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -52,6 +52,7 @@ struct cpu_info;
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/* probe for a PIC and set it up, return TRUE on success */
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int init_ohare(void);
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int init_heathrow(void);
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int init_u3_ht(void);
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int init_grandcentral(void);
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void setup_hammerhead_ipi(void);
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: interrupts.c,v 1.4 2010/11/14 03:57:17 uebayasi Exp $ */
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/* $NetBSD: interrupts.c,v 1.5 2013/04/18 16:42:46 macallan Exp $ */
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/*-
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* Copyright (c) 2007 Michael Lorenz
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@ -27,7 +27,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: interrupts.c,v 1.4 2010/11/14 03:57:17 uebayasi Exp $");
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__KERNEL_RCSID(0, "$NetBSD: interrupts.c,v 1.5 2013/04/18 16:42:46 macallan Exp $");
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#include "opt_multiprocessor.h"
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@ -47,6 +47,7 @@ __KERNEL_RCSID(0, "$NetBSD: interrupts.c,v 1.4 2010/11/14 03:57:17 uebayasi Exp
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#include "pic_openpic.h"
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#include "pic_ohare.h"
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#include "pic_heathrow.h"
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#include "pic_u3_ht.h"
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#include "opt_ipi.h"
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#include "ipi_openpic.h"
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#include "ipi_hammerhead.h"
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@ -119,6 +120,10 @@ init_interrupt(void)
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if (init_heathrow())
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goto done;
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#endif
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#if NPIC_U3_HT > 0
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if (init_u3_ht())
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goto done;
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#endif
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#if NPIC_OPENPIC > 0
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if (init_openpic(0))
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goto done;
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522
sys/arch/macppc/macppc/pic_u3_ht.c
Normal file
522
sys/arch/macppc/macppc/pic_u3_ht.c
Normal file
@ -0,0 +1,522 @@
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/*-
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* Copyright (c) 2013 Phileas Fogg
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include "opt_openpic.h"
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#include "opt_interrupt.h"
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#include <sys/param.h>
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#include <sys/kmem.h>
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#include <sys/kernel.h>
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#include <machine/pio.h>
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#include <powerpc/openpic.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/pci/pcireg.h>
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#include <machine/autoconf.h>
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#include <arch/powerpc/pic/picvar.h>
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struct u3_ht_irqmap {
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int im_index;
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int im_level;
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volatile uint8_t *im_base;
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volatile uint8_t *im_apple_base;
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uint32_t im_data;
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};
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struct u3_ht_ops {
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struct pic_ops pic;
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volatile uint8_t *ht_base;
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struct u3_ht_irqmap ht_irqmap[128];
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uint32_t (*ht_read)(struct u3_ht_ops *, u_int);
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void (*ht_write)(struct u3_ht_ops *, u_int, uint32_t);
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};
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#define u3_ht_read(ptr,reg) (ptr)->ht_read(ptr, reg)
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#define u3_ht_write(ptr,reg,val) (ptr)->ht_write(ptr, reg, val)
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static struct u3_ht_ops *setup_u3_ht(uint32_t, uint32_t, int);
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static int setup_u3_ht_workarounds(struct u3_ht_ops *);
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static void u3_ht_enable_irq(struct pic_ops *, int, int);
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static void u3_ht_disable_irq(struct pic_ops *, int);
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static int u3_ht_get_irq(struct pic_ops *, int);
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static void u3_ht_ack_irq(struct pic_ops *, int);
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static void u3_ht_establish_irq(struct pic_ops *, int, int, int);
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static void u3_ht_finish_setup(struct pic_ops *);
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static int u3_ht_is_ht_irq(struct u3_ht_ops *, int);
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static void u3_ht_establish_ht_irq(struct u3_ht_ops *, int, int);
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static void u3_ht_enable_ht_irq(struct u3_ht_ops *, int);
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static void u3_ht_ack_ht_irq(struct u3_ht_ops *, int);
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static void u3_ht_set_priority(struct u3_ht_ops *, int, int);
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static int u3_ht_read_irq(struct u3_ht_ops *, int);
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static void u3_ht_eoi(struct u3_ht_ops *, int);
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static uint32_t u3_ht_read_be(struct u3_ht_ops *, u_int);
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static void u3_ht_write_be(struct u3_ht_ops *, u_int, uint32_t);
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static uint32_t u3_ht_read_le(struct u3_ht_ops *, u_int);
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static void u3_ht_write_le(struct u3_ht_ops *, u_int, uint32_t);
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static const char *u3_compat[] = {
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"u3",
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NULL
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};
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const char *pic_compat[] = {
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"chrp,open-pic",
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"open-pic",
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"openpic",
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NULL
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};
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int init_u3_ht(void)
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{
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int u4, pic;
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uint32_t reg[2];
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uint32_t base, len, tmp;
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int bigendian;
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volatile uint8_t *unin_reg;
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u4 = OF_finddevice("/u4");
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if (u4 == -1)
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return FALSE;
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if (of_compatible(u4, u3_compat) == -1)
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return FALSE;
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pic = OF_child(u4);
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while ((pic != 0) && (of_compatible(pic, pic_compat) == -1))
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pic = OF_peer(pic);
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if ((pic == -1) || (pic == 0))
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return FALSE;
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if (OF_getprop(u4, "reg", reg, sizeof(reg)) != 8)
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return FALSE;
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base = reg[1];
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/* Enable and reset PIC */
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unin_reg = mapiodev(base, PAGE_SIZE, false);
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KASSERT(unin_reg != NULL);
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tmp = in32(unin_reg + 0xe0);
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tmp |= 0x06;
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out32(unin_reg + 0xe0, tmp);
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bigendian = 0;
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if (OF_getprop(pic, "big-endian", reg, 4) > -1)
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bigendian = 1;
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if (OF_getprop(pic, "reg", reg, 8) != 8)
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return FALSE;
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base = reg[0];
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len = reg[1];
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aprint_normal("found U3/U4 HT PIC at %08x\n", base);
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setup_u3_ht(base, len, bigendian);
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return TRUE;
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}
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static struct u3_ht_ops *
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setup_u3_ht(uint32_t addr, uint32_t len, int bigendian)
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{
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struct u3_ht_ops *u3_ht;
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struct pic_ops *pic;
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int irq;
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u_int x;
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u3_ht = kmem_alloc(sizeof(struct u3_ht_ops), KM_SLEEP);
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KASSERT(u3_ht != NULL);
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bzero(u3_ht, sizeof(struct u3_ht_ops));
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pic = &u3_ht->pic;
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u3_ht->ht_base = mapiodev(addr, len, false);
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KASSERT(u3_ht->ht_base != NULL);
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if (bigendian) {
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u3_ht->ht_read = u3_ht_read_be;
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u3_ht->ht_write = u3_ht_write_be;
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} else {
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u3_ht->ht_read = u3_ht_read_le;
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u3_ht->ht_write = u3_ht_write_le;
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}
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setup_u3_ht_workarounds(u3_ht);
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/* Reset PIC */
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x = u3_ht_read(u3_ht, OPENPIC_CONFIG);
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u3_ht_write(u3_ht, OPENPIC_CONFIG, x | OPENPIC_CONFIG_RESET);
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do {
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x = u3_ht_read(u3_ht, OPENPIC_CONFIG);
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} while (x & OPENPIC_CONFIG_RESET);
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x = u3_ht_read(u3_ht, OPENPIC_FEATURE);
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aprint_normal("OpenPIC Version 1.%d: "
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"Supports %d CPUs and %d interrupt sources.\n",
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x & 0xff, ((x & 0x1f00) >> 8) + 1, ((x & 0x07ff0000) >> 16) + 1);
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pic->pic_numintrs = ((x & 0x07ff0000) >> 16) + 1;
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pic->pic_cookie = (void *) addr;
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pic->pic_enable_irq = u3_ht_enable_irq;
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pic->pic_reenable_irq = u3_ht_enable_irq;
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pic->pic_disable_irq = u3_ht_disable_irq;
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pic->pic_get_irq = u3_ht_get_irq;
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pic->pic_ack_irq = u3_ht_ack_irq;
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pic->pic_establish_irq = u3_ht_establish_irq;
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pic->pic_finish_setup = u3_ht_finish_setup;
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strcpy(pic->pic_name, "openpic");
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pic_add(pic);
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u3_ht_set_priority(u3_ht, 0, 15);
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for (irq = 0; irq < pic->pic_numintrs; irq++) {
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x = irq;
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x |= OPENPIC_IMASK;
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x |= OPENPIC_POLARITY_NEGATIVE;
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x |= OPENPIC_SENSE_LEVEL;
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x |= 8 << OPENPIC_PRIORITY_SHIFT;
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u3_ht_write(u3_ht, OPENPIC_SRC_VECTOR(irq), x);
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u3_ht_write(u3_ht, OPENPIC_IDEST(irq), 1 << 0);
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}
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x = u3_ht_read(u3_ht, OPENPIC_CONFIG);
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x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
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u3_ht_write(u3_ht, OPENPIC_CONFIG, x);
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u3_ht_write(u3_ht, OPENPIC_SPURIOUS_VECTOR, 0xff);
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u3_ht_set_priority(u3_ht, 0, 0);
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for (irq = 0; irq < pic->pic_numintrs; irq++) {
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u3_ht_read_irq(u3_ht, 0);
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u3_ht_eoi(u3_ht, 0);
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}
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return u3_ht;
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}
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static int
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setup_u3_ht_workarounds(struct u3_ht_ops *u3_ht)
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{
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struct u3_ht_irqmap *irqmap = u3_ht->ht_irqmap;
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int parent, child;
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uint32_t reg[5], tmp;
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uint8_t pos;
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uint16_t cr, ht_cr;
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int nirq, irq, i;
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volatile uint8_t *ht_reg, *dev_reg, *base;
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parent = OF_finddevice("/ht");
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if (parent == -1)
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return FALSE;
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if (OF_getprop(parent, "reg", reg, 12) != 12)
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return FALSE;
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ht_reg = mapiodev(reg[1], reg[2], false);
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KASSERT(ht_reg != NULL);
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for (child = OF_child(parent); child != 0; child = OF_peer(child)) {
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if (OF_getprop(child, "reg", reg, 4) != 4)
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continue;
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dev_reg = ht_reg + (reg[0] & (OFW_PCI_PHYS_HI_DEVICEMASK |
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OFW_PCI_PHYS_HI_FUNCTIONMASK));
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tmp = in32rb(dev_reg + PCI_COMMAND_STATUS_REG);
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if ((tmp & PCI_STATUS_CAPLIST_SUPPORT) == 0)
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continue;
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for (pos = in8rb(dev_reg + PCI_CAPLISTPTR_REG);
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pos != 0; pos = in8rb(dev_reg + pos + 0x01)) {
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cr = in16rb(dev_reg + pos);
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if (PCI_CAPLIST_CAP(cr) != 0x08)
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continue;
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ht_cr = in16rb(dev_reg + pos + 0x02);
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if ((ht_cr & 0xf800) == 0x8000)
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break;
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}
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if (pos == 0)
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continue;
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base = dev_reg + pos;
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out8rb(base + 0x02, 0x01);
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nirq = in32rb(base + 0x04);
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nirq = (nirq >> 16) & 0xff;
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for (i = 0; i <= nirq; i++) {
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out8rb(base + 0x02, 0x10 + (i << 1));
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tmp = in32rb(base + 0x04);
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irq = (tmp >> 16) & 0xff;
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tmp |= 0x01;
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out32rb(base + 0x04, tmp);
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irqmap[irq].im_index = i;
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irqmap[irq].im_level = 0;
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irqmap[irq].im_base = base;
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tmp = in32rb(dev_reg + PCI_ID_REG);
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if (PCI_VENDOR(tmp) == 0x106b)
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irqmap[irq].im_apple_base = dev_reg + 0x60;
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else
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irqmap[irq].im_apple_base = NULL;
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out8rb(base + 0x02, 0x11 + (i << 1));
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irqmap[irq].im_data = in32rb(base + 0x04);
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irqmap[irq].im_data |= (1 << 31);
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}
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}
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return TRUE;
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}
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static void
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u3_ht_enable_irq(struct pic_ops *pic, int irq, int type)
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{
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struct u3_ht_ops *u3_ht = (struct u3_ht_ops *)pic;
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u_int x;
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x = u3_ht_read(u3_ht, OPENPIC_SRC_VECTOR(irq));
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x &= ~OPENPIC_IMASK;
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u3_ht_write(u3_ht, OPENPIC_SRC_VECTOR(irq), x);
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if (u3_ht_is_ht_irq(u3_ht, irq))
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u3_ht_enable_ht_irq(u3_ht, irq);
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}
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static void
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u3_ht_disable_irq(struct pic_ops *pic, int irq)
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{
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struct u3_ht_ops *u3_ht = (struct u3_ht_ops *)pic;
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u_int x;
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x = u3_ht_read(u3_ht, OPENPIC_SRC_VECTOR(irq));
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x |= OPENPIC_IMASK;
|
||||
u3_ht_write(u3_ht, OPENPIC_SRC_VECTOR(irq), x);
|
||||
}
|
||||
|
||||
static int
|
||||
u3_ht_get_irq(struct pic_ops *pic, int mode)
|
||||
{
|
||||
struct u3_ht_ops *u3_ht = (struct u3_ht_ops *)pic;
|
||||
|
||||
return u3_ht_read_irq(u3_ht, curcpu()->ci_index);
|
||||
}
|
||||
|
||||
static void
|
||||
u3_ht_ack_irq(struct pic_ops *pic, int irq)
|
||||
{
|
||||
struct u3_ht_ops *u3_ht = (struct u3_ht_ops *)pic;
|
||||
|
||||
if (u3_ht_is_ht_irq(u3_ht, irq))
|
||||
u3_ht_ack_ht_irq(u3_ht, irq);
|
||||
|
||||
u3_ht_eoi(u3_ht, curcpu()->ci_index);
|
||||
}
|
||||
|
||||
static void
|
||||
u3_ht_establish_irq(struct pic_ops *pic, int irq, int type, int pri)
|
||||
{
|
||||
struct u3_ht_ops *u3_ht = (struct u3_ht_ops *)pic;
|
||||
int realpri = max(1, min(15, pri));
|
||||
uint32_t x;
|
||||
|
||||
x = irq;
|
||||
x |= OPENPIC_IMASK;
|
||||
|
||||
if (u3_ht_is_ht_irq(u3_ht, irq)) {
|
||||
x |= OPENPIC_POLARITY_POSITIVE |
|
||||
OPENPIC_SENSE_EDGE;
|
||||
} else {
|
||||
if (irq == 0 || type == IST_EDGE_RISING || type == IST_LEVEL_HIGH)
|
||||
x |= OPENPIC_POLARITY_POSITIVE;
|
||||
else
|
||||
x |= OPENPIC_POLARITY_NEGATIVE;
|
||||
|
||||
if (type == IST_EDGE_FALLING || type == IST_EDGE_RISING)
|
||||
x |= OPENPIC_SENSE_EDGE;
|
||||
else
|
||||
x |= OPENPIC_SENSE_LEVEL;
|
||||
}
|
||||
|
||||
x |= realpri << OPENPIC_PRIORITY_SHIFT;
|
||||
u3_ht_write(u3_ht, OPENPIC_SRC_VECTOR(irq), x);
|
||||
|
||||
if (u3_ht_is_ht_irq(u3_ht, irq))
|
||||
u3_ht_establish_ht_irq(u3_ht, irq, type);
|
||||
|
||||
aprint_debug("%s: setting IRQ %d to priority %d\n", __func__, irq,
|
||||
realpri);
|
||||
}
|
||||
|
||||
static void
|
||||
u3_ht_finish_setup(struct pic_ops *pic)
|
||||
{
|
||||
struct u3_ht_ops *u3_ht = (struct u3_ht_ops *)pic;
|
||||
uint32_t cpumask = 0;
|
||||
int i;
|
||||
|
||||
#ifdef OPENPIC_DISTRIBUTE
|
||||
for (i = 0; i < ncpu; i++)
|
||||
cpumask |= (1 << cpu_info[i].ci_cpuid);
|
||||
#else
|
||||
cpumask = 1;
|
||||
#endif
|
||||
|
||||
for (i = 0; i < pic->pic_numintrs; i++)
|
||||
u3_ht_write(u3_ht, OPENPIC_IDEST(i), cpumask);
|
||||
}
|
||||
|
||||
static int
|
||||
u3_ht_is_ht_irq(struct u3_ht_ops *u3_ht, int irq)
|
||||
{
|
||||
return (irq < 128) && (u3_ht->ht_irqmap[irq].im_base != NULL);
|
||||
}
|
||||
|
||||
static void
|
||||
u3_ht_establish_ht_irq(struct u3_ht_ops *u3_ht, int irq, int type)
|
||||
{
|
||||
struct u3_ht_irqmap *irqmap = &u3_ht->ht_irqmap[irq];
|
||||
u_int x;
|
||||
|
||||
out8rb(irqmap->im_base + 0x02, 0x10 + (irqmap->im_index << 1));
|
||||
|
||||
x = in32rb(irqmap->im_base + 0x04);
|
||||
x &= ~0x23;
|
||||
|
||||
if (type == IST_LEVEL_HIGH || type == IST_LEVEL_LOW) {
|
||||
irqmap->im_level = 1;
|
||||
x |= 0x22;
|
||||
} else {
|
||||
irqmap->im_level = 0;
|
||||
}
|
||||
|
||||
out32rb(irqmap->im_base + 0x04, x);
|
||||
}
|
||||
|
||||
static void
|
||||
u3_ht_enable_ht_irq(struct u3_ht_ops *u3_ht, int irq)
|
||||
{
|
||||
struct u3_ht_irqmap *irqmap = &u3_ht->ht_irqmap[irq];
|
||||
u_int x;
|
||||
|
||||
out8rb(irqmap->im_base + 0x02, 0x10 + (irqmap->im_index << 1));
|
||||
x = in32rb(irqmap->im_base + 0x04);
|
||||
x &= ~0x01;
|
||||
out32rb(irqmap->im_base + 0x04, x);
|
||||
|
||||
u3_ht_ack_ht_irq(u3_ht, irq);
|
||||
}
|
||||
|
||||
static void
|
||||
u3_ht_ack_ht_irq(struct u3_ht_ops *u3_ht, int irq)
|
||||
{
|
||||
struct u3_ht_irqmap *irqmap = &u3_ht->ht_irqmap[irq];
|
||||
|
||||
if (irqmap->im_level != 0) {
|
||||
if (irqmap->im_apple_base != NULL) {
|
||||
out32rb(irqmap->im_apple_base + ((irqmap->im_index >> 3) & ~0x03),
|
||||
1 << (irqmap->im_index & 0x1f));
|
||||
} else {
|
||||
out8rb(irqmap->im_base + 0x02, 0x11 + (irqmap->im_index << 1));
|
||||
out32rb(irqmap->im_base + 0x04, irqmap->im_data);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
u3_ht_set_priority(struct u3_ht_ops *u3_ht, int cpu, int pri)
|
||||
{
|
||||
u_int x;
|
||||
|
||||
x = u3_ht_read(u3_ht, OPENPIC_CPU_PRIORITY(cpu));
|
||||
x &= ~OPENPIC_CPU_PRIORITY_MASK;
|
||||
x |= pri;
|
||||
u3_ht_write(u3_ht, OPENPIC_CPU_PRIORITY(cpu), x);
|
||||
}
|
||||
|
||||
static int
|
||||
u3_ht_read_irq(struct u3_ht_ops *u3_ht, int cpu)
|
||||
{
|
||||
return u3_ht_read(u3_ht, OPENPIC_IACK(cpu)) & OPENPIC_VECTOR_MASK;
|
||||
}
|
||||
|
||||
static void
|
||||
u3_ht_eoi(struct u3_ht_ops *u3_ht, int cpu)
|
||||
{
|
||||
u3_ht_write(u3_ht, OPENPIC_EOI(cpu), 0);
|
||||
u3_ht_read(u3_ht, OPENPIC_EOI(cpu));
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
u3_ht_read_be(struct u3_ht_ops *u3_ht, u_int reg)
|
||||
{
|
||||
volatile uint8_t *addr = u3_ht->ht_base + reg;
|
||||
|
||||
return in32(addr);
|
||||
}
|
||||
|
||||
static void
|
||||
u3_ht_write_be(struct u3_ht_ops *u3_ht, u_int reg, uint32_t val)
|
||||
{
|
||||
volatile uint8_t *addr = u3_ht->ht_base + reg;
|
||||
|
||||
out32(addr, val);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
u3_ht_read_le(struct u3_ht_ops *u3_ht, u_int reg)
|
||||
{
|
||||
volatile uint8_t *addr = u3_ht->ht_base + reg;
|
||||
|
||||
return in32rb(addr);
|
||||
}
|
||||
|
||||
static void
|
||||
u3_ht_write_le(struct u3_ht_ops *u3_ht, u_int reg, uint32_t val)
|
||||
{
|
||||
volatile uint8_t *addr = u3_ht->ht_base + reg;
|
||||
|
||||
out32rb(addr, val);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user