From b74a1d3d8adbbce3b41cd40eeb9236e8eb93b8a4 Mon Sep 17 00:00:00 2001 From: skrll Date: Fri, 4 Dec 2020 07:11:35 +0000 Subject: [PATCH] Update stats in the coherent case. Reported by jmcneill. --- sys/arch/arm/arm32/bus_dma.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/sys/arch/arm/arm32/bus_dma.c b/sys/arch/arm/arm32/bus_dma.c index 8478ca5d17b3..def04b215221 100644 --- a/sys/arch/arm/arm32/bus_dma.c +++ b/sys/arch/arm/arm32/bus_dma.c @@ -1,4 +1,4 @@ -/* $NetBSD: bus_dma.c,v 1.124 2020/10/24 14:51:59 skrll Exp $ */ +/* $NetBSD: bus_dma.c,v 1.125 2020/12/04 07:11:35 skrll Exp $ */ /*- * Copyright (c) 1996, 1997, 1998, 2020 The NetBSD Foundation, Inc. @@ -36,7 +36,7 @@ #include "opt_cputypes.h" #include -__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.124 2020/10/24 14:51:59 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.125 2020/12/04 07:11:35 skrll Exp $"); #include @@ -1135,6 +1135,29 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, /* Skip cache frobbing if mapping was COHERENT */ if ((map->_dm_flags & _BUS_DMAMAP_COHERENT)) { + switch (ops) { + case BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE: + STAT_INCR(sync_prereadwrite); + break; + + case BUS_DMASYNC_PREREAD: + STAT_INCR(sync_preread); + break; + + case BUS_DMASYNC_PREWRITE: + STAT_INCR(sync_prewrite); + break; + + case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE: + STAT_INCR(sync_postreadwrite); + break; + + case BUS_DMASYNC_POSTREAD: + STAT_INCR(sync_postread); + break; + + /* BUS_DMASYNC_POSTWRITE was aleady handled as a fastpath */ + } /* * Drain the write buffer of DMA operators. * 1) when cpu->device (prewrite)