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Recognize some TI processors -- not that you'd want to use them.

This commit is contained in:
mycroft 2003-09-03 02:07:07 +00:00
parent 3713dfb05b
commit b715eaff3c
3 changed files with 12 additions and 6 deletions
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8
sys/arch/arm/arm/cpufunc.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc.c,v 1.61 2003/07/15 00:24:38 lukem Exp $ */ /* $NetBSD: cpufunc.c,v 1.62 2003/09/03 02:07:07 mycroft Exp $ */
/* /*
* arm7tdmi support code Copyright (c) 2001 John Fremlin * arm7tdmi support code Copyright (c) 2001 John Fremlin
@ -46,7 +46,7 @@
*/ */
#include <sys/cdefs.h> #include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.61 2003/07/15 00:24:38 lukem Exp $"); __KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.62 2003/09/03 02:07:07 mycroft Exp $");
#include "opt_compat_netbsd.h" #include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h" #include "opt_cpuoptions.h"
@ -896,7 +896,9 @@ set_cpufuncs()
} }
#endif /* CPU_ARM8 */ #endif /* CPU_ARM8 */
#ifdef CPU_ARM9 #ifdef CPU_ARM9
if (cputype == CPU_ID_ARM920T) { if (((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD ||
(cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_TI) &&
(cputype & 0x0000f000) == 0x00009000) {
cpufuncs = arm9_cpufuncs; cpufuncs = arm9_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
get_cachetype_cp15(); get_cachetype_cp15();

6
sys/arch/arm/arm32/cpu.c
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@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.51 2003/06/23 11:01:06 martin Exp $ */ /* $NetBSD: cpu.c,v 1.52 2003/09/03 02:07:08 mycroft Exp $ */
/* /*
* Copyright (c) 1995 Mark Brinicombe. * Copyright (c) 1995 Mark Brinicombe.
@ -46,7 +46,7 @@
#include <sys/param.h> #include <sys/param.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.51 2003/06/23 11:01:06 martin Exp $"); __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.52 2003/09/03 02:07:08 mycroft Exp $");
#include <sys/systm.h> #include <sys/systm.h>
#include <sys/malloc.h> #include <sys/malloc.h>
@ -296,6 +296,8 @@ const struct cpuidtab cpuids[] = {
generic_steppings }, generic_steppings },
{ CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S",
generic_steppings }, generic_steppings },
{ CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T",
generic_steppings },
{ CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110",
sa110_steppings }, sa110_steppings },

4
sys/arch/arm/include/armreg.h
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@ -1,4 +1,4 @@
/* $NetBSD: armreg.h,v 1.25 2003/05/13 11:45:52 ichiro Exp $ */ /* $NetBSD: armreg.h,v 1.26 2003/09/03 02:07:09 mycroft Exp $ */
/* /*
* Copyright (c) 1998, 2001 Ben Harris * Copyright (c) 1998, 2001 Ben Harris
@ -117,6 +117,7 @@
#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
#define CPU_ID_DEC 0x44000000 /* 'D' */ #define CPU_ID_DEC 0x44000000 /* 'D' */
#define CPU_ID_INTEL 0x69000000 /* 'i' */ #define CPU_ID_INTEL 0x69000000 /* 'i' */
#define CPU_ID_TI 0x54000000 /* 'T' */
/* How to decide what format the CPUID is in. */ /* How to decide what format the CPUID is in. */
#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000)
@ -189,6 +190,7 @@
#define CPU_ID_ARM1022ES 0x4105a220 #define CPU_ID_ARM1022ES 0x4105a220
#define CPU_ID_SA110 0x4401a100 #define CPU_ID_SA110 0x4401a100
#define CPU_ID_SA1100 0x4401a110 #define CPU_ID_SA1100 0x4401a110
#define CPU_ID_TI925T 0x54029250
#define CPU_ID_SA1110 0x6901b110 #define CPU_ID_SA1110 0x6901b110
#define CPU_ID_IXP1200 0x6901c120 #define CPU_ID_IXP1200 0x6901c120
#define CPU_ID_80200 0x69052000 #define CPU_ID_80200 0x69052000