From b682f09cbbc533150404f341082bb1ee54c1ff54 Mon Sep 17 00:00:00 2001
From: msaitoh <msaitoh@NetBSD.org>
Date: Mon, 27 Dec 1999 10:50:41 +0000
Subject: [PATCH] fix missing SCI IRQ mask/unmask code.

---
 sys/arch/evbsh3/evbsh3/shb.c | 11 +++++++----
 sys/arch/sh3/include/intr.h  | 16 +++++++++++++++-
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/sys/arch/evbsh3/evbsh3/shb.c b/sys/arch/evbsh3/evbsh3/shb.c
index e70ca22eea95..fddb8aedb42f 100644
--- a/sys/arch/evbsh3/evbsh3/shb.c
+++ b/sys/arch/evbsh3/evbsh3/shb.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: shb.c,v 1.4 1999/12/06 14:10:49 msaitoh Exp $	*/
+/*	$NetBSD: shb.c,v 1.5 1999/12/27 10:50:41 msaitoh Exp $	*/
 
 /*-
  * Copyright (c) 1993, 1994 Charles Hannum.  All rights reserved.
@@ -403,9 +403,11 @@ intrhandler(p1, p2, p3, p4, frame)
 	if (irl >= INTEVT_SOFT) {
 		/* This is software interrupt */
 		irq_num = (irl - INTEVT_SOFT);
-	} else if (irl == INTEVT_TMU1)
+	} else if (irl == INTEVT_TMU1) {
 		irq_num = TMU1_IRQ;
-	else
+	} else if (IS_INTEVT_SCI0(irl)) {	/* XXX TOO DIRTY */
+		irq_num = SCI_IRQ;
+	} else
 		irq_num = (irl - 0x200) >> 5;
 
 	mask_irq(irq_num);
@@ -524,7 +526,8 @@ mask_irq(irq)
 }
 
 void
-unmask_irq(int irq)
+unmask_irq(irq)
+	int irq;
 {
 
 	switch (irq) {
diff --git a/sys/arch/sh3/include/intr.h b/sys/arch/sh3/include/intr.h
index b9a44f1029ca..aeab3f814dc1 100644
--- a/sys/arch/sh3/include/intr.h
+++ b/sys/arch/sh3/include/intr.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.h,v 1.2 1999/09/14 10:22:35 tsubai Exp $	*/
+/*	$NetBSD: intr.h,v 1.3 1999/12/27 10:50:41 msaitoh Exp $	*/
 
 /*
  * Copyright (c) 1996, 1997 Charles M. Hannum.  All rights reserved.
@@ -170,4 +170,18 @@ softintr(mask)
 #define INTEVT_TMU1 0x420
 #define INTEVT_TMU2 0x440
 
+#define INTEVT_SCI0_ERI	0x4e0
+#define INTEVT_SCI0_RXI	0x500
+#define INTEVT_SCI0_TXI	0x520
+#define INTEVT_SCI0_TEI	0x540
+
+#define IS_INTEVT_SCI0(x) ((x == INTEVT_SCI0_ERI) || (x == INTEVT_SCI0_RXI) \
+			|| (x == INTEVT_SCI0_TXI) || (x == INTEVT_SCI0_TEI))
+
+#define	INTEVT_PRI	0x4a0	/* Periodic interrupt generated by RTC */
+
+#if defined(SH4)
+#define	INTEVT_SCIF	0x700
+#endif
+
 #endif /* !_SH3_INTR_H_ */