sync with latest Linux driver, avoid framing error on LMC1200 (T1/E1).
from hal@vailsys.com
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itojun
parent
44e529fecc
commit
b66f433b03
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@ -1,4 +1,4 @@
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/* $NetBSD: if_lmc_media.c,v 1.8 2001/07/19 16:14:50 itojun Exp $ */
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/* $NetBSD: if_lmc_media.c,v 1.9 2001/07/19 17:02:05 itojun Exp $ */
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/*-
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* Copyright (c) 1997-1999 LAN Media Corporation (LMC)
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@ -902,25 +902,65 @@ lmc_t1_init(lmc_softc_t * const sc)
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lmc_mii_writereg(sc, 0, 16, mii16 | LMC_MII16_T1_RST);
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lmc_mii_writereg(sc, 0, 16, mii16);
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/* set T1 or E1 line impedance */
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/* mii16 &= ~LMC_MII16_T1_Z; */
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/* set T1 line impedance */
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mii16 |= LMC_MII16_T1_Z;
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lmc_mii_writereg(sc, 0, 16, mii16);
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/* Standard LMC1200 init code */
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lmc_t1_write(sc, 0x01, 0x1B); /* CR0 - primary control */
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lmc_t1_write(sc, 0x02, 0x42); /* JAT_CR - jitter atten config */
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lmc_t1_write(sc, 0x14, 0x00); /* LOOP - loopback config */
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lmc_t1_write(sc, 0x15, 0x00); /* DL3_TS - xtrnl datalink timeslot */
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lmc_t1_write(sc, 0x18, 0xFF); /* PIO - programmable I/O */
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lmc_t1_write(sc, 0x19, 0x30); /* POE - programmable OE */
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lmc_t1_write(sc, 0x1A, 0x0F); /* CMUX - clock input mux */
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lmc_t1_write(sc, 0x20, 0x41); /* LIU_CR - RX LIU config */
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lmc_t1_write(sc, 0x22, 0x76); /* RLIU_CR - RX LIU config */
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/* CR0 - Set framing to ESF + Force CRC - Set T1 */
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lmc_t1_write(sc, 0x01, 0x1b);
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/* Reset Elastic store to center - 64 bit elastic store */
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lmc_t1_write(sc, 0x02, 0x4b);
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/* Release Elastic store reset */
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lmc_t1_write(sc, 0x02, 0x43);
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/* Disable all interrupts except BOP receive */
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lmc_t1_write(sc, 0x0C, 0x00);
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lmc_t1_write(sc, 0x0D, 0x00);
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lmc_t1_write(sc, 0x0E, 0x00);
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lmc_t1_write(sc, 0x0F, 0x00);
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lmc_t1_write(sc, 0x10, 0x00);
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lmc_t1_write(sc, 0x11, 0x00);
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lmc_t1_write(sc, 0x12, 0x80);
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lmc_t1_write(sc, 0x13, 0x00);
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lmc_t1_write(sc, 0x14, 0x00); /* LOOP - loopback config */
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lmc_t1_write(sc, 0x15, 0x00); /* DL3_TS - xtrnl datalink timeslot */
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lmc_t1_write(sc, 0x18, 0xFF); /* PIO - programmable I/O */
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lmc_t1_write(sc, 0x19, 0x30); /* POE - programmable OE */
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lmc_t1_write(sc, 0x1A, 0x0F); /* CMUX - clock input mux */
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lmc_t1_write(sc, 0x20, 0xC1); /* LIU_CR - RX LIU config */
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lmc_t1_write(sc, 0x20, 0x41); /* LIU_CR - RX LIU config */
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lmc_t1_write(sc, 0x22, 0xB1); /* RLIU_CR - RX LIU config */
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lmc_t1_write(sc, 0x24, 0x21); /* VGA_MAX -20db sesitivity */
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lmc_t1_write(sc, 0x2A, 0xA6); /* Force off the pre-equalizer */
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/* Equalizer Gain threshholds */
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lmc_t1_write(sc, 0x38, 0x24); /* RX_TH0 - RX gain threshold 0 */
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lmc_t1_write(sc, 0x39, 0x28); /* RX_TH1 - RX gain threshold 0 */
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lmc_t1_write(sc, 0x3A, 0x2C); /* RX_TH2 - RX gain threshold 0 */
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lmc_t1_write(sc, 0x3B, 0x30); /* RX_TH3 - RX gain threshold 0 */
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lmc_t1_write(sc, 0x3C, 0x34); /* RX_TH4 - RX gain threshold 0 */
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/* Reset LIU */
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lmc_t1_write(sc, 0x20, 0x81); /* LIU_CR - RX LIU (reset RLIU) */
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lmc_t1_write(sc, 0x20, 0x01); /* LIU_CR - RX LIU (clear reset) */
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lmc_t1_write(sc, 0x40, 0x03); /* RCR0 - RX config */
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lmc_t1_write(sc, 0x41, 0x00); /* Zero test pattern generator */
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lmc_t1_write(sc, 0x42, 0x09); /* DN_LEN is 8, UP_LEN is 5 */
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lmc_t1_write(sc, 0x43, 0x08); /* Loopback activate */
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lmc_t1_write(sc, 0x44, 0x24); /* Loopback deactivate */
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lmc_t1_write(sc, 0x45, 0x00); /* RALM - RX alarm config */
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lmc_t1_write(sc, 0x46, 0x05); /* LATCH - RX alarm/err/cntr latch */
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lmc_t1_write(sc, 0x68, 0x40); /* TLIU_CR - TX LIU config */
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lmc_t1_write(sc, 0x46, 0x08); /* LATCH - RX alarm/err/cntr latch */
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lmc_t1_write(sc, 0x68, 0x4E); /* TLIU_CR - TX LIU config */
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lmc_t1_write(sc, 0x70, 0x0D); /* TCR0 - TX framer config */
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lmc_t1_write(sc, 0x71, 0x05); /* TCR1 - TX config */
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lmc_t1_write(sc, 0x72, 0x0B); /* TFRM - TX frame format */
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@ -929,23 +969,44 @@ lmc_t1_init(lmc_softc_t * const sc)
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lmc_t1_write(sc, 0x75, 0x00); /* TALM - TX alarm signal config */
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lmc_t1_write(sc, 0x76, 0x00); /* TPATT - TX test pattern config */
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lmc_t1_write(sc, 0x77, 0x00); /* TLB - TX inband loopback confg */
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lmc_t1_write(sc, 0x90, 0x05); /* CLAD_CR - clock rate adapter confg */
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lmc_t1_write(sc, 0x90, 0x06); /* CLAD_CR - clock rate adapter confg */
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lmc_t1_write(sc, 0x91, 0x05); /* CSEL - clad freq sel */
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lmc_t1_write(sc, 0xA6, 0x00); /* DL1_CTL - DL1 control */
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lmc_t1_write(sc, 0x92, 0x00); /* CLAD Phase Det */
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lmc_t1_write(sc, 0x93, 0x00); /* No CLAD Test */
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/* Activate BOP */
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lmc_t1_write(sc, 0xA0, 0xea); /* BOP - Bit oriented protocol xcvr */
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lmc_t1_write(sc, 0xA4, 0x40); /* DL1_TS - DL1 time slot enable */
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lmc_t1_write(sc, 0xA5, 0x00); /* DL1_BIT - DL1 bit enable */
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lmc_t1_write(sc, 0xA6, 0x03); /* DL1_CTL - DL1 control */
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lmc_t1_write(sc, 0xA7, 0x00); /* RDL1_FFC - DL1 FIFO Size */
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lmc_t1_write(sc, 0xAB, 0x00); /* TDL1_FFC - DL1 Empty Control */
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lmc_t1_write(sc, 0xAA, 0x00); /* PRM - no perf report messages */
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lmc_t1_write(sc, 0xB1, 0x00); /* DL2_CTL - DL2 control */
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lmc_t1_write(sc, 0xD0, 0x47); /* SBI_CR - sys bus iface config */
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lmc_t1_write(sc, 0xD1, 0x70); /* RSB_CR - RX sys bus config */
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lmc_t1_write(sc, 0xD4, 0x30); /* TSB_CR - TX sys bus config */
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for (i = 0; i < 32; i++) {
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lmc_t1_write(sc, 0x0E0+i, 0x00); /*SBCn sysbus perchannel ctl */
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lmc_t1_write(sc, 0x100+i, 0x00); /* TPCn - TX per-channel ctl */
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lmc_t1_write(sc, 0x180+i, 0x00); /* RPCn - RX per-channel ctl */
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}
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for (i = 1; i < 25; i++) {
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/* SBCn - sys bus per-channel ctl */
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lmc_t1_write(sc, 0x0E0+i, 0x0D);
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/* SBCn - sys bus per-channel ctl */
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}
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/* PFM */
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lmc_t1_write(sc, 0xA4, 0x40); /* DL1_TS - DL1 time slot enable */
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lmc_t1_write(sc, 0xA5, 0x00); /* DL1_BIT - DL1 bit enable */
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lmc_t1_write(sc, 0xA6, 0x03); /* DL1_CTL - DL1 control */
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lmc_t1_write(sc, 0xA7, 0x00); /* RDL1_FFC - DL1 FIFO Size */
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lmc_t1_write(sc, 0xAB, 0x00); /* TDL1_FFC - DL1 Empty Control */
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mii16 |= LMC_MII16_T1_XOE;
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lmc_mii_writereg (sc, 0, 16, mii16);
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sc->lmc_miireg16 = mii16;
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