Unused files after the sfas driver is replaced by the MI ncr53c9x driver.
This commit is contained in:
veego
parent
1bb06f8aab
commit
b59e0fd6a7
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/* $NetBSD: bzscreg.h,v 1.2 1996/04/21 21:10:54 veego Exp $ */
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/*
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* Copyright (c) 1995 Daniel Widenfalk
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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||||||
* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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||||||
* notice, this list of conditions and the following disclaimer in the
|
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||||||
* documentation and/or other materials provided with the distribution.
|
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* 3. All advertising materials mentioning features or use of this software
|
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* must display the following acknowledgement:
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* This product includes software developed by Daniel Widenfalk
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* BlizzardII 1230 with FAS216 SCSI interface hardware description. */
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#ifndef _BZSCREG_H_
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#define _BZSCREG_H_
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#ifndef _SFARREG_H_
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#include <amiga/dev/sfasreg.h>
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#endif
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typedef struct bzsc_regmap {
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sfas_regmap_t FAS216;
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vu_char *cclkaddr;
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vu_char *epowaddr;
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} bzsc_regmap_t;
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typedef bzsc_regmap_t *bzsc_regmap_p;
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#define BZSC_DMA_WRITE 0x80000000
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#define BZSC_DMA_READ 0x00000000 /* Symmetric reasons */
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#endif
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/* $NetBSD: bztzscreg.h,v 1.1 1996/12/16 16:17:29 is Exp $ */
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/*
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* Copyright (c) 1996 Ignatios Souvatzis
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* Copyright (c) 1995 Daniel Widenfalk
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
|
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* must display the following acknowledgement:
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* This product includes software developed by Daniel Widenfalk
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Blizzard 2060 with FAS216 SCSI interface hardware
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* description.
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*/
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#ifndef _BZTZSCREG_H_
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#define _BZTZSCREG_H_
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#ifndef _SFASREG_H_
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#include <amiga/dev/sfasreg.h>
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#endif
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typedef struct bztzsc_regmap {
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sfas_regmap_t FAS216;
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vu_char *hardbits;
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vu_char *addrport;
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} bztzsc_regmap_t;
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typedef bztzsc_regmap_t *bztzsc_regmap_p;
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#endif
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/* $NetBSD: flscreg.h,v 1.2 1996/04/21 21:11:04 veego Exp $ */
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/*
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* Copyright (c) 1995 Daniel Widenfalk
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Daniel Widenfalk
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* FastlaneZ3 with FAS216 SCSI interface hardware description.
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*/
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#ifndef _FLSCREG_H_
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#define _FLSCREG_H_
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typedef struct flsc_regmap {
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sfas_regmap_t FAS216;
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vu_char *hardbits;
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vu_char *clear;
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vu_char *dmabase;
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} flsc_regmap_t;
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typedef flsc_regmap_t *flsc_regmap_p;
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#define FLSC_HB_DISABLED 0x01
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#define FLSC_HB_BUSID6 0x02
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#define FLSC_HB_SEAGATE 0x04
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#define FLSC_HB_SLOW 0x08
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#define FLSC_HB_SYNCHRON 0x10
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#define FLSC_HB_CREQ 0x20
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#define FLSC_HB_IACT 0x40
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#define FLSC_HB_MINT 0x80
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#define FLSC_PB_ESI 0x01
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#define FLSC_PB_EDI 0x02
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#define FLSC_PB_ENABLE_DMA 0x04
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#define FLSC_PB_DISABLE_DMA 0x00 /* Symmetric reasons */
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#define FLSC_PB_DMA_WRITE 0x08
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#define FLSC_PB_DMA_READ 0x00 /* Symmetric reasons */
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#define FLSC_PB_LED 0x10
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#define FLSC_PB_INT_BITS (FLSC_PB_ESI | FLSC_PB_EDI)
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#define FLSC_PB_DMA_BITS (FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE)
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#endif
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File diff suppressed because it is too large
Load Diff
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/* $NetBSD: sfasreg.h,v 1.2 1996/04/21 21:12:31 veego Exp $ */
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/*
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* Copyright (c) 1995 Daniel Widenfalk
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Daniel Widenfalk
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SFASREG_H_
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#define _SFASREG_H_
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/*
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* Emulex FAS216 SCSI interface hardware description.
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*/
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typedef volatile unsigned char vu_char;
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typedef struct {
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vu_char *sfas_tc_low; /* rw: Transfer count low */
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vu_char *sfas_tc_mid; /* rw: Transfer count mid */
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vu_char *sfas_fifo; /* rw: Data FIFO */
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vu_char *sfas_command; /* rw: Chip command reg */
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vu_char *sfas_dest_id; /* w: (Re)select bus ID */
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#define sfas_status sfas_dest_id /* r: Status */
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vu_char *sfas_timeout; /* w: (Re)select timeout */
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#define sfas_interrupt sfas_timeout /* r: Interrupt */
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vu_char *sfas_syncper; /* w: Synch. transfer period */
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#define sfas_seqstep sfas_syncper /* r: Sequence step */
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vu_char *sfas_syncoff; /* w: Synch. transfer offset */
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#define sfas_fifo_flags sfas_syncoff /* r: FIFO flags */
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vu_char *sfas_config1; /* rw: Config register #1 */
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vu_char *sfas_clkconv; /* w: Clock conv. factor */
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vu_char *sfas_test; /* w: Test register */
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vu_char *sfas_config2; /* rw: Config register #2 */
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vu_char *sfas_config3; /* rw: Config register #3 */
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vu_char *sfas_tc_high; /* rw: Transfer count high */
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vu_char *sfas_fifo_bot; /* w: FIFO bottom register */
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} sfas_regmap_t;
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typedef sfas_regmap_t *sfas_regmap_p;
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/* Commands for the FAS216 */
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#define SFAS_CMD_DMA 0x80
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#define SFAS_CMD_SEL_NO_ATN 0x41
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#define SFAS_CMD_SEL_ATN 0x42
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#define SFAS_CMD_SEL_ATN3 0x46
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#define SFAS_CMD_SEL_ATN_STOP 0x43
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#define SFAS_CMD_ENABLE_RESEL 0x44
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#define SFAS_CMD_DISABLE_RESEL 0x45
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#define SFAS_CMD_TRANSFER_INFO 0x10
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#define SFAS_CMD_TRANSFER_PAD 0x98
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#define SFAS_CMD_COMMAND_COMPLETE 0x11
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#define SFAS_CMD_MESSAGE_ACCEPTED 0x12
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#define SFAS_CMD_SET_ATN 0x1A
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#define SFAS_CMD_RESET_ATN 0x1B
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#define SFAS_CMD_NOP 0x00
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#define SFAS_CMD_FLUSH_FIFO 0x01
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#define SFAS_CMD_RESET_CHIP 0x02
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#define SFAS_CMD_RESET_SCSI_BUS 0x03
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#define SFAS_STAT_PHASE_MASK 0x07
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#define SFAS_STAT_PHASE_TRANS_CPLT 0x08
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#define SFAS_STAT_TRANSFER_COUNT_ZERO 0x10
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#define SFAS_STAT_PARITY_ERROR 0x20
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#define SFAS_STAT_GROSS_ERROR 0x40
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#define SFAS_STAT_INTERRUPT_PENDING 0x80
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#define SFAS_PHASE_DATA_OUT 0
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#define SFAS_PHASE_DATA_IN 1
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#define SFAS_PHASE_COMMAND 2
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#define SFAS_PHASE_STATUS 3
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#define SFAS_PHASE_MESSAGE_OUT 6
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#define SFAS_PHASE_MESSAGE_IN 7
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#define SFAS_DEST_ID_MASK 0x07
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#define SFAS_INT_SELECTED 0x01
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#define SFAS_INT_SELECTED_WITH_ATN 0x02
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#define SFAS_INT_RESELECTED 0x04
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#define SFAS_INT_FUNCTION_COMPLETE 0x08
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#define SFAS_INT_BUS_SERVICE 0x10
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#define SFAS_INT_DISCONNECT 0x20
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#define SFAS_INT_ILLEGAL_COMMAND 0x40
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#define SFAS_INT_SCSI_RESET_DETECTED 0x80
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#define SFAS_SYNCHRON_PERIOD_MASK 0x1F
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#define SFAS_FIFO_COUNT_MASK 0x1F
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#define SFAS_FIFO_SEQUENCE_STEP_MASK 0xE0
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#define SFAS_FIFO_SEQUENCE_SHIFT 5
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#define SFAS_SYNCHRON_OFFSET_MASK 0x0F
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#define SFAS_SYNC_ASSERT_MASK 0x30
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#define SFAS_SYNC_ASSERT_SHIFT 4
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#define SFAS_SYNC_DEASSERT_MASK 0x30
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#define SFAS_SYNC_DEASSERT_SHIFT 6
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#define SFAS_CFG1_BUS_ID_MASK 0x07
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#define SFAS_CFG1_CHIP_TEST_MODE 0x08
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#define SFAS_CFG1_SCSI_PARITY_ENABLE 0x10
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#define SFAS_CFG1_PARITY_TEST_MODE 0x20
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#define SFAS_CFG1_SCSI_RES_INT_DIS 0x40
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#define SFAS_CFG1_SLOW_CABLE_MODE 0x80
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#define SFAS_CLOCK_CONVERSION_MASK 0x07
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#define SFAS_TEST_TARGET_TEST_MODE 0x01
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#define SFAS_TEST_INITIATOR_TEST_MODE 0x02
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#define SFAS_TEST_TRISTATE_TEST_MODE 0x04
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#define SFAS_CFG2_DMA_PARITY_ENABLE 0x01
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#define SFAS_CFG2_REG_PARITY_ENABLE 0x02
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#define SFAS_CFG2_TARG_BAD_PARITY_ABORT 0x04
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#define SFAS_CFG2_SCSI_2_MODE 0x08
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#define SFAS_CFG2_TRISTATE_DMA_REQ 0x10
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#define SFAS_CFG2_BYTE_CONTROL_MODE 0x20
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#define SFAS_CFG2_FEATURES_ENABLE 0x40
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#define SFAS_CFG2_RESERVE_FIFO_BYTE 0x80
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#define SFAS_CFG3_THRESHOLD_8_MODE 0x01
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#define SFAS_CFG3_ALTERNATE_DMA_MODE 0x02
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#define SFAS_CFG3_SAVE_RESIDUAL_BYTE 0x04
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#define SFAS_CFG3_FASTCLK 0x08
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#define SFAS_CFG3_FASTSCSI 0x10
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#define SFAS_CFG3_CDB10 0x20
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#define SFAS_CFG3_QENB 0x40
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#define SFAS_CFG3_IDRESCHK 0x80
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#endif
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@ -1,305 +0,0 @@
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/* $NetBSD: sfasvar.h,v 1.5 1997/08/27 11:23:20 bouyer Exp $ */
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/*
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* Copyright (c) 1995 Daniel Widenfalk
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*
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|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* 3. All advertising materials mentioning features or use of this software
|
|
||||||
* must display the following acknowledgement:
|
|
||||||
* This product includes software developed by Daniel Widenfalk
|
|
||||||
* for the NetBSD Project.
|
|
||||||
* 4. The name of the author may not be used to endorse or promote products
|
|
||||||
* derived from this software without specific prior written permission
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|
||||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|
||||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
||||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
||||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|
||||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _SFASVAR_H_
|
|
||||||
#define _SFASVAR_H_
|
|
||||||
|
|
||||||
#ifndef _SFASREG_H_
|
|
||||||
#include <amiga/dev/sfasreg.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Do not define if we don't need the vm FIX
|
|
||||||
*/
|
|
||||||
#define SFAS_NEED_VM_PATCH 1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MAXCHAIN is the anticipated maximum number of chain blocks needed. This
|
|
||||||
* assumes that we are NEVER requested to transfer more than MAXPHYS bytes.
|
|
||||||
*/
|
|
||||||
#define MAXCHAIN (MAXPHYS/NBPG+2)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Maximum number of requests standing by. Could be anything, but I think 9
|
|
||||||
* looks nice :-) NOTE: This does NOT include requests already started!
|
|
||||||
*/
|
|
||||||
#define MAXPENDING 9 /* 7 IDs + 2 extra */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DMA chain block. If flg == SFAS_CHAIN_PRG or flg == SFAS_CHAIN_BUMP then
|
|
||||||
* ptr is a VIRTUAL adress. If flg == SFAS_CHAIN_DMA then ptr is a PHYSICAL
|
|
||||||
* adress.
|
|
||||||
*/
|
|
||||||
struct sfas_dma_chain {
|
|
||||||
vm_offset_t ptr;
|
|
||||||
u_short len;
|
|
||||||
short flg;
|
|
||||||
};
|
|
||||||
#define SFAS_CHAIN_DMA 0x00
|
|
||||||
#define SFAS_CHAIN_BUMP 0x01
|
|
||||||
#define SFAS_CHAIN_PRG 0x02
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This is the data that we need for the vm FIX. offset is the offset into
|
|
||||||
* the first page. pa is the physical adress of each page. pages is the number
|
|
||||||
* of slots used in pa. If pages == 0 the we don't need the FIX right now.
|
|
||||||
*/
|
|
||||||
#ifdef SFAS_NEED_VM_PATCH
|
|
||||||
struct vm_link_data {
|
|
||||||
vm_offset_t pa[MAXCHAIN];
|
|
||||||
short offset;
|
|
||||||
short pages;
|
|
||||||
};
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This struct contains the necessary info for a pending request. Pointer to
|
|
||||||
* a scsipi_xfer struct and an optional vm_link_data.
|
|
||||||
*/
|
|
||||||
struct sfas_pending {
|
|
||||||
TAILQ_ENTRY(sfas_pending) link;
|
|
||||||
struct scsipi_xfer *xs;
|
|
||||||
#ifdef SFAS_NEED_VM_PATCH
|
|
||||||
struct vm_link_data vm_link_data;
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* nexus contains all active data for one SCSI unit. Parts of the info in this
|
|
||||||
* struct survives between scsi commands.
|
|
||||||
*/
|
|
||||||
struct nexus {
|
|
||||||
struct scsipi_xfer *xs; /* Pointer to request */
|
|
||||||
|
|
||||||
u_char ID; /* ID message to be sent */
|
|
||||||
u_char clen; /* scsi command length + */
|
|
||||||
u_char cbuf[14]; /* the actual command bytes */
|
|
||||||
|
|
||||||
struct sfas_dma_chain dma[MAXCHAIN]; /* DMA chain blocks */
|
|
||||||
short max_link; /* Maximum used of above */
|
|
||||||
short cur_link; /* Currently handled block */
|
|
||||||
|
|
||||||
u_char *buf; /* Virtual adress of data */
|
|
||||||
int len; /* Bytes left to transfer */
|
|
||||||
|
|
||||||
vm_offset_t dma_buf; /* Current DMA adress */
|
|
||||||
int dma_len; /* Current DMA length */
|
|
||||||
|
|
||||||
vm_offset_t dma_blk_ptr; /* Current chain adress */
|
|
||||||
int dma_blk_len; /* Current chain length */
|
|
||||||
u_char dma_blk_flg; /* Current chain flags */
|
|
||||||
|
|
||||||
u_char state; /* Nexus state, see below */
|
|
||||||
u_short flags; /* Nexus flags, see below */
|
|
||||||
|
|
||||||
short period; /* Sync period to request */
|
|
||||||
u_char offset; /* Sync offset to request */
|
|
||||||
|
|
||||||
u_char syncper; /* FAS216 variable storage */
|
|
||||||
u_char syncoff; /* FAS216 variable storage */
|
|
||||||
u_char config3; /* FAS216 variable storage */
|
|
||||||
|
|
||||||
u_char lun_unit; /* (Lun<<4) | Unit of nexus */
|
|
||||||
u_char status; /* Status byte from unit*/
|
|
||||||
|
|
||||||
#ifdef SFAS_NEED_VM_PATCH
|
|
||||||
struct vm_link_data vm_link_data; /* Optional vm FIX data */
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
/* SCSI nexus_states */
|
|
||||||
#define SFAS_NS_IDLE 0 /* Nexus idle */
|
|
||||||
#define SFAS_NS_SELECTED 1 /* Last command was a SELECT command */
|
|
||||||
#define SFAS_NS_DATA_IN 2 /* Last command was a TRANSFER_INFO */
|
|
||||||
/* command during a data in phase */
|
|
||||||
#define SFAS_NS_DATA_OUT 3 /* Last command was a TRANSFER_INFO */
|
|
||||||
/* command during a data out phase */
|
|
||||||
#define SFAS_NS_STATUS 4 /* We have send a COMMAND_COMPLETE */
|
|
||||||
/* command and are awaiting status */
|
|
||||||
#define SFAS_NS_MSG_IN 5 /* Last phase was MESSAGE IN */
|
|
||||||
#define SFAS_NS_MSG_OUT 6 /* Last phase was MESSAGE OUT */
|
|
||||||
#define SFAS_NS_SVC 7 /* We have sent the command */
|
|
||||||
#define SFAS_NS_DISCONNECTING 8 /* We have recieved a disconnect msg */
|
|
||||||
#define SFAS_NS_DISCONNECTED 9 /* We are disconnected */
|
|
||||||
#define SFAS_NS_RESELECTED 10 /* We was reselected */
|
|
||||||
#define SFAS_NS_DONE 11 /* Done. Prephsase to FINISHED */
|
|
||||||
#define SFAS_NS_FINISHED 12 /* Realy done. Call scsi_done */
|
|
||||||
#define SFAS_NS_SENSE 13 /* We are requesting sense */
|
|
||||||
#define SFAS_NS_RESET 14 /* We are reseting this unit */
|
|
||||||
|
|
||||||
/* SCSI nexus flags */
|
|
||||||
#define SFAS_NF_UNIT_BUSY 0x0001 /* Unit is not available */
|
|
||||||
|
|
||||||
#define SFAS_NF_SELECT_ME 0x0002 /* Nexus is set up, waiting for bus */
|
|
||||||
|
|
||||||
#define SFAS_NF_REQUEST_SENSE 0x0004 /* We should request sense */
|
|
||||||
#define SFAS_NF_SENSING 0x0008 /* We are sensing */
|
|
||||||
|
|
||||||
#define SFAS_NF_HAS_MSG 0x0010 /* We have recieved a complete msg */
|
|
||||||
|
|
||||||
#define SFAS_NF_DO_SDTR 0x0020 /* We should send a SDTR */
|
|
||||||
#define SFAS_NF_SDTR_SENT 0x0040 /* We have sent a SDTR */
|
|
||||||
#define SFAS_NF_SYNC_TESTED 0x0080 /* We have negotiated sync */
|
|
||||||
|
|
||||||
#define SFAS_NF_RESET 0x0100 /* Reset this nexus */
|
|
||||||
#define SFAS_NF_IMMEDIATE 0x0200 /* We are operating from sfasicmd */
|
|
||||||
|
|
||||||
#define SFAS_NF_DEBUG 0x8000 /* As it says: DEBUG */
|
|
||||||
|
|
||||||
struct sfas_softc {
|
|
||||||
struct device sc_dev; /* System required struct */
|
|
||||||
struct scsipi_link sc_link; /* For sub devices */
|
|
||||||
struct isr sc_isr; /* Interrupt chain struct */
|
|
||||||
|
|
||||||
TAILQ_HEAD(,sfas_pending) sc_xs_pending;
|
|
||||||
TAILQ_HEAD(,sfas_pending) sc_xs_free;
|
|
||||||
struct sfas_pending sc_xs_store[MAXPENDING];
|
|
||||||
|
|
||||||
sfas_regmap_p sc_fas; /* FAS216 Address */
|
|
||||||
void *sc_spec; /* Board-specific data */
|
|
||||||
|
|
||||||
#ifdef SFAS_NEED_VM_PATCH
|
|
||||||
u_char *sc_vm_link;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
u_char *sc_bump_va; /* Bumpbuf virtual adr */
|
|
||||||
vm_offset_t sc_bump_pa; /* Bumpbuf physical adr */
|
|
||||||
int sc_bump_sz; /* Bumpbuf size */
|
|
||||||
|
|
||||||
/* Configuration registers, must be set BEFORE sfasinitialize */
|
|
||||||
u_char sc_clock_freq;
|
|
||||||
u_short sc_timeout;
|
|
||||||
u_char sc_host_id;
|
|
||||||
u_char sc_config_flags;
|
|
||||||
|
|
||||||
/* Generic DMA functions */
|
|
||||||
int (*sc_setup_dma)
|
|
||||||
__P((struct sfas_softc *sc,
|
|
||||||
vm_offset_t ptr, int len, int mode));
|
|
||||||
int (*sc_build_dma_chain)
|
|
||||||
__P((struct sfas_softc *sc,
|
|
||||||
struct sfas_dma_chain *chain,
|
|
||||||
void *p, int l));
|
|
||||||
int (*sc_need_bump)
|
|
||||||
__P((struct sfas_softc *sc,
|
|
||||||
vm_offset_t ptr, int len));
|
|
||||||
|
|
||||||
/* Generic Led data */
|
|
||||||
int sc_led_status;
|
|
||||||
void (*sc_led) __P((struct sfas_softc *sc, int mode));
|
|
||||||
|
|
||||||
/* Nexus list */
|
|
||||||
struct nexus sc_nexus[8];
|
|
||||||
struct nexus *sc_cur_nexus;
|
|
||||||
struct nexus *sc_sel_nexus;
|
|
||||||
|
|
||||||
/* Current transfer data */
|
|
||||||
#ifdef SFAS_NEED_VM_PATCH
|
|
||||||
short sc_vm_link_pages;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
u_char *sc_buf; /* va */
|
|
||||||
int sc_len;
|
|
||||||
|
|
||||||
vm_offset_t sc_dma_buf; /* pa */
|
|
||||||
int sc_dma_len;
|
|
||||||
vm_offset_t sc_dma_blk_ptr;
|
|
||||||
int sc_dma_blk_len;
|
|
||||||
short sc_dma_blk_flg;
|
|
||||||
|
|
||||||
struct sfas_dma_chain *sc_chain; /* Current DMA chain */
|
|
||||||
short sc_max_link;
|
|
||||||
short sc_cur_link;
|
|
||||||
|
|
||||||
/* Interrupt registers */
|
|
||||||
u_char sc_status;
|
|
||||||
u_char sc_interrupt;
|
|
||||||
u_char sc_resel[2];
|
|
||||||
|
|
||||||
u_char sc_units_disconnected;
|
|
||||||
|
|
||||||
/* Storage for FAS216 config registers (current values) */
|
|
||||||
u_char sc_config1;
|
|
||||||
u_char sc_config2;
|
|
||||||
u_char sc_config3;
|
|
||||||
u_char sc_clock_conv_fact;
|
|
||||||
u_char sc_timeout_val;
|
|
||||||
u_char sc_clock_period;
|
|
||||||
|
|
||||||
u_char sc_msg_in[7];
|
|
||||||
u_char sc_msg_in_len;
|
|
||||||
|
|
||||||
u_char sc_msg_out[7];
|
|
||||||
u_char sc_msg_out_len;
|
|
||||||
|
|
||||||
u_char sc_unit;
|
|
||||||
u_char sc_lun;
|
|
||||||
u_char sc_flags;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define SFAS_DMA_READ 0
|
|
||||||
#define SFAS_DMA_WRITE 1
|
|
||||||
#define SFAS_DMA_CLEAR 2
|
|
||||||
|
|
||||||
/* sc_flags */
|
|
||||||
#define SFAS_ACTIVE 0x01
|
|
||||||
#define SFAS_DONT_WAIT 0x02
|
|
||||||
#ifdef SFAS_NEED_VM_PATCH
|
|
||||||
#define SFAS_HAS_VM_LINK 0x04
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* SCSI Selection modes */
|
|
||||||
#define SFAS_SELECT 0x00 /* Normal selection: No sync, no resel */
|
|
||||||
#define SFAS_SELECT_R 0x01 /* Reselection allowed */
|
|
||||||
#define SFAS_SELECT_S 0x02 /* Synchronous transfer allowed */
|
|
||||||
#define SFAS_SELECT_I 0x04 /* Selection for sfasicmd */
|
|
||||||
#define SFAS_SELECT_K 0x08 /* Send a BUS DEVICE RESET message (Kill) */
|
|
||||||
|
|
||||||
/* Nice abbreviations of the above */
|
|
||||||
#define SFAS_SELECT_RS (SFAS_SELECT_R|SFAS_SELECT_S)
|
|
||||||
#define SFAS_SELECT_RI (SFAS_SELECT_R|SFAS_SELECT_I)
|
|
||||||
#define SFAS_SELECT_SI (SFAS_SELECT_S|SFAS_SELECT_I)
|
|
||||||
#define SFAS_SELECT_RSI (SFAS_SELECT_R|SFAS_SELECT_S|SFAS_SELECT_I)
|
|
||||||
|
|
||||||
/* sc_config_flags */
|
|
||||||
#define SFAS_NO_SYNCH 0x01 /* Disable synchronous transfer */
|
|
||||||
#define SFAS_NO_DMA 0x02 /* Do not use DMA! EVER! */
|
|
||||||
#define SFAS_NO_RESELECT 0x04 /* Do not allow relesection */
|
|
||||||
#define SFAS_SLOW_CABLE 0x08 /* Cable is "unsafe" for fast scsi-2 */
|
|
||||||
#define SFAS_SLOW_START 0x10 /* There are slow starters on the bus */
|
|
||||||
|
|
||||||
void sfasinitialize __P((struct sfas_softc *sc));
|
|
||||||
void sfas_minphys __P((struct buf *bp));
|
|
||||||
int sfas_scsicmd __P((struct scsipi_xfer *));
|
|
||||||
void sfasintr __P((struct sfas_softc *dev));
|
|
||||||
|
|
||||||
#endif /* _SFASVAR_H_ */
|
|
||||||
Loading…
Reference in New Issue