- adapt KURBOX/HG arrangements, requested and tested by kiyohara.
- make tlp.c suited for ADMTek/Infineon AN983B/BX.
This commit is contained in:
nisimura
parent
3d0db58d61
commit
b521313cab
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@ -1,4 +1,4 @@
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/* $NetBSD: brdsetup.c,v 1.7 2009/06/12 00:24:33 nisimura Exp $ */
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/* $NetBSD: brdsetup.c,v 1.8 2009/07/03 10:31:19 nisimura Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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@ -87,6 +87,22 @@ brdsetup(void)
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consname = "eumb";
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consport = 0x4600;
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consspeed = 57600;
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if (pcifinddev(0x10ec, 0x8169, &pcib) == 0) /* KURO-BOX/HG */
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ticks_per_sec = 133000000 / 4;
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/* Stop Watchdog */
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uartbase = 0xfc000000 + 0x4500;
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div = (ticks_per_sec * 4) / 9600 / 16;
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UART_WRITE(DCR, 0x01); /* 2 independent UART */
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UART_WRITE(LCR, 0x80); /* turn on DLAB bit */
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UART_WRITE(FCR, 0x00);
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UART_WRITE(DMB, div >> 8);
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UART_WRITE(DLB, div & 0xff);
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UART_WRITE(LCR, 0x03 | 0x18); /* 8 E 1 */
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UART_WRITE(MCR, 0x03); /* RTS DTR */
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UART_WRITE(FCR, 0x07); /* FIFO_EN | RXSR | TXSR */
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UART_WRITE(IER, 0x00); /* make sure INT disabled */
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printf("AAAAFFFFJJJJ>>>>VVVV>>>>ZZZZVVVVKKKK");
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}
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/* now prepare serial console */
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@ -94,7 +110,7 @@ brdsetup(void)
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uartbase = 0xfe000000 + consport; /* 0x3f8, 0x2f8 */
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else {
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uartbase = 0xfc000000 + consport; /* 0x4500, 0x4600 */
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div = (TICKS_PER_SEC * 4) / consspeed / 16;
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div = (ticks_per_sec * 4) / consspeed / 16;
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UART_WRITE(DCR, 0x01); /* 2 independent UART */
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UART_WRITE(LCR, 0x80); /* turn on DLAB bit */
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UART_WRITE(FCR, 0x00);
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@ -1,4 +1,4 @@
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/* $NetBSD: globals.h,v 1.9 2009/06/12 00:24:33 nisimura Exp $ */
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/* $NetBSD: globals.h,v 1.10 2009/07/03 10:31:19 nisimura Exp $ */
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/* clock feed */
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#ifndef TICKS_PER_SEC
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@ -17,6 +17,7 @@ extern int brdtype;
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extern char *consname;
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extern int consport;
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extern int consspeed;
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extern int ticks_per_sec;
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unsigned mpc107memsize(void);
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@ -1,4 +1,4 @@
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/* $NetBSD: main.c,v 1.22 2009/06/12 00:24:33 nisimura Exp $ */
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/* $NetBSD: main.c,v 1.23 2009/07/03 10:31:19 nisimura Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -58,6 +58,7 @@ int brdtype;
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char *consname = CONSNAME;
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int consport = CONSPORT;
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int consspeed = CONSSPEED;
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int ticks_per_sec = TICKS_PER_SEC;
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void
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main(void)
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@ -135,7 +136,7 @@ main(void)
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snprintf(bi_cons.devname, sizeof(bi_cons.devname), consname);
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bi_cons.addr = consport;
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bi_cons.speed = consspeed;
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bi_clk.ticks_per_sec = TICKS_PER_SEC;
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bi_clk.ticks_per_sec = ticks_per_sec;
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snprintf(bi_path.bootpath, sizeof(bi_path.bootpath), bootfile);
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snprintf(bi_rdev.devname, sizeof(bi_rdev.devname), rootdev);
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bi_rdev.cookie = tag; /* PCI tag for fxp netboot case */
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@ -1,4 +1,4 @@
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/* $NetBSD: tlp.c,v 1.22 2009/01/25 03:39:28 nisimura Exp $ */
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/* $NetBSD: tlp.c,v 1.23 2009/07/03 10:31:19 nisimura Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -41,13 +41,13 @@
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/*
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* - reverse endian access for CSR register.
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* - no vtophys() translation, vaddr_t == paddr_t.
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* - no vtophys() translation, vaddr_t == paddr_t.
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* - PIPT writeback cache aware.
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*/
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#define CSR_READ(l, r) in32rb((l)->csr+(r))
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#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
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#define VTOPHYS(va) (uint32_t)(va)
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#define DEVTOV(pa) (uint32_t)(pa)
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#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
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#define VTOPHYS(va) (uint32_t)(va)
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#define DEVTOV(pa) (uint32_t)(pa)
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#define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz))
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#define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz))
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#define DELAY(n) delay(n)
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@ -60,7 +60,6 @@ struct desc {
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#define T0_ES (1U<<15) /* Tx error summary */
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#define T1_LS (1U<<30) /* last segment */
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#define T1_FS (1U<<29) /* first segment */
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#define T1_SET (1U<<27) /* "setup packet" */
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#define T1_TER (1U<<25) /* end of ring mark */
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#define T1_TCH (1U<<24) /* TDES3 points the next desc */
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#define T1_TBS_MASK 0x7ff /* segment size 10:0 */
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@ -73,47 +72,40 @@ struct desc {
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#define R0_FLMASK 0x3fff0000 /* frame length 29:16 */
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#define R1_RBS_MASK 0x7ff /* segment size 10:0 */
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#define TLP_BMR 0x00 /* 0: bus mode */
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#define BMR_RST 01
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#define BMR_CAL8 0x00004000 /* 32B cache alignment */
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#define BMR_CAL16 0x00008000 /* 64B */
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#define BMR_CAL32 0x0000c000 /* 128B */
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#define BMR_CAL 0x0000c000
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#define TLP_TPD 0x08 /* 1: instruct Tx to start */
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#define TLP_RPD 0x10 /* 2: instruct Rx to start */
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#define TLP_RRBA 0x18 /* 3: Rx descriptor base */
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#define TLP_TRBA 0x20 /* 4: Tx descriptor base */
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#define TLP_STS 0x28 /* 5: status */
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#define STS_TS 0x00700000 /* Tx status */
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#define STS_RS 0x000e0000 /* Rx status */
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#define TLP_OMR 0x30 /* 6: operation mode */
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#define OMR_SDP (1U<<25) /* always ON */
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#define OMR_PS (1U<<18) /* port select */
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#define OMR_PM (1U<< 6) /* promiscuous */
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#define OMR_TEN (1U<<13) /* instruct start/stop Tx */
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#define OMR_REN (1U<< 1) /* instruct start/stop Rx */
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#define OMR_FD (1U<< 9) /* FDX */
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#define TLP_IEN 0x38 /* 7: interrupt enable mask */
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#define TLP_APROM 0x48 /* 9: SEEPROM and MII management */
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#define SROM_RD (1U <<14) /* read operation */
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#define SROM_WR (1U <<13) /* write openration */
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#define SROM_SR (1U <<11) /* SEEPROM select */
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#define TLP_CSR12 0x60 /* 12: SIA status */
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#define PAR_CSR0 0x00 /* bus mode */
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#define PAR_DEFAULTS 0x00001000 /* PDF sez it should be ... */
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#define PAR_SWR 01
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#define TDR_CSR1 0x08 /* T0_OWN poll demand */
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#define RDR_CSR2 0x10 /* R0_OWN poll demand */
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#define RDB_CSR3 0x18 /* Rx descriptor base */
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#define TDB_CSR4 0x20 /* Tx descriptor base */
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#define SR_CSR5 0x28 /* interrupt stauts */
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#define NAR_CSR6 0x30 /* operation mode */
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#define NAR_NOSQE (1U<<19) /* _not_ use SQE signal */
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#define NAR_TEN (1U<<13) /* instruct start/stop Tx */
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#define NAR_REN (1U<< 1) /* instruct start/stop Rx */
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#define IER_CSR7 0x38 /* interrupt enable mask */
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#define SPR_CSR9 0x48 /* SEEPROM and MII management */
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#define MII_MDI (1U<<19) /* 0/1 presense after read op */
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#define MII_MIDIR (1U<<18) /* 1 for PHY->HOST */
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#define MII_MDO (1U<<17) /* 0/1 for write op */
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#define MII_MDC (1U<<16) /* MDIO clock */
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#define SROM_RD (1U<<14) /* read operation */
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#define SROM_WR (1U<<13) /* write openration */
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#define SROM_SR (1U<<11) /* SEEPROM select */
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#define PAR0_CSR25 0xa4 /* MAC 3:0 */
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#define PAR1_CSR26 0xa8 /* MAC 5:4 */
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#define FRAMESIZE 1536
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struct local {
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struct desc txd;
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struct desc txd[2];
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struct desc rxd[2];
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uint8_t txstore[192];
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uint8_t rxstore[2][FRAMESIZE];
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unsigned csr, omr, rx;
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unsigned sromsft;
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unsigned csr, omr, tx, rx;
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unsigned phy, bmsr, anlpar;
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};
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static void size_srom(struct local *);
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static int read_srom(struct local *, int);
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static unsigned mii_read(struct local *, int, int);
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static void mii_write(struct local *, int, int, int);
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static void mii_initphy(struct local *);
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@ -126,7 +118,7 @@ tlp_match(unsigned tag, void *data)
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v = pcicfgread(tag, PCI_ID_REG);
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switch (v) {
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case PCI_DEVICE(0x1011, 0x0009):
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case PCI_DEVICE(0x1317, 0x0985): /* ADMTek/Infineon 983B/BX */
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return 1;
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}
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return 0;
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@ -139,39 +131,32 @@ tlp_init(unsigned tag, void *data)
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struct local *l;
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struct desc *txd, *rxd;
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uint8_t *en;
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uint32_t *p;
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l = ALLOC(struct local, sizeof(struct desc)); /* desc alignment */
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l = ALLOC(struct local, 2 * sizeof(struct desc)); /* desc alignment */
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memset(l, 0, sizeof(struct local));
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l->csr = DEVTOV(pcicfgread(tag, 0x14)); /* use mem space */
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val = CSR_READ(l, TLP_BMR);
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CSR_WRITE(l, TLP_BMR, val | BMR_RST);
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DELAY(1000);
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val &= ~BMR_CAL;
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switch (pcicfgread(tag, 0x0c) & 0xff) {
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case 32:
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val |= BMR_CAL32; break;
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case 16:
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val |= BMR_CAL16; break;
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case 8:
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default:
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val |= BMR_CAL8; break;
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}
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CSR_WRITE(l, TLP_BMR, val);
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DELAY(1000);
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(void)CSR_READ(l, TLP_BMR);
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CSR_WRITE(l, PAR_CSR0, PAR_SWR);
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i = 100;
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do {
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DELAY(10);
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} while (i-- > 0 && (CSR_READ(l, PAR_CSR0) & PAR_SWR) != 0);
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CSR_WRITE(l, PAR_CSR0, PAR_DEFAULTS);
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l->omr = OMR_PS | OMR_SDP;
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CSR_WRITE(l, TLP_OMR, l->omr);
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CSR_WRITE(l, TLP_STS, ~0);
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CSR_WRITE(l, TLP_IEN, 0);
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l->omr = NAR_NOSQE;
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CSR_WRITE(l, NAR_CSR6, l->omr);
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CSR_WRITE(l, SR_CSR5, ~0);
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CSR_WRITE(l, IER_CSR7, 0);
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size_srom(l);
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en = data;
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val = read_srom(l, 20/2+0); en[0] = val; en[1] = val >> 8;
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val = read_srom(l, 20/2+1); en[2] = val; en[3] = val >> 8;
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val = read_srom(l, 20/2+2); en[4] = val; en[5] = val >> 8;
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val = CSR_READ(l, PAR0_CSR25);
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en[0] = val & 0xff;
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en[1] = (val >> 8) & 0xff;
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en[2] = (val >> 16) & 0xff;
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en[3] = (val >> 24) & 0xff;
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val = CSR_READ(l, PAR1_CSR26);
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en[4] = val & 0xff;
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en[5] = (val >> 8) & 0xff;
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#if 1
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printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
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en[0], en[1], en[2], en[3], en[4], en[5]);
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@ -180,43 +165,25 @@ tlp_init(unsigned tag, void *data)
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mii_initphy(l);
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mii_dealan(l, 5);
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txd = &l->txd;
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txd = &l->txd[0];
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txd[1].xd1 = htole32(T1_TER);
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rxd = &l->rxd[0];
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rxd[0].xd0 = htole32(R0_OWN);
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rxd[0].xd1 = htole32(R1_RCH | FRAMESIZE);
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rxd[0].xd1 = htole32(FRAMESIZE);
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rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0]));
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rxd[0].xd3 = htole32(VTOPHYS(&rxd[1]));
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rxd[1].xd0 = htole32(R0_OWN);
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rxd[1].xd1 = htole32(R1_RER | FRAMESIZE);
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rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1]));
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/* R1_RER neglects xd3 */
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l->rx = 0;
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/* "setup frame" to have own station address */
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txd = &l->txd;
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txd->xd3 = htole32(VTOPHYS(txd));
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txd->xd2 = htole32(VTOPHYS(l->txstore));
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txd->xd1 = htole32(T1_SET | sizeof(l->txstore));
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txd->xd0 = htole32(T0_OWN);
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p = (uint32_t *)l->txstore;
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p[0] = htole32(en[1] << 8 | en[0]);
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p[1] = htole32(en[3] << 8 | en[2]);
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p[2] = htole32(en[5] << 8 | en[4]);
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for (i = 1; i < 16; i++)
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memcpy(&p[3 * i], &p[0], 3 * sizeof(p[0]));
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l->tx = l->rx = 0;
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/* make sure the entire descriptors transfered to memory */
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wbinv(l, sizeof(struct local));
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CSR_WRITE(l, TLP_TRBA, VTOPHYS(txd));
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CSR_WRITE(l, TLP_RRBA, VTOPHYS(rxd));
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CSR_WRITE(l, TDB_CSR4, VTOPHYS(txd));
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CSR_WRITE(l, RDB_CSR3, VTOPHYS(rxd));
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/* start Tx/Rx */
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l->omr |= OMR_FD | OMR_TEN | OMR_REN;
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CSR_WRITE(l, TLP_OMR, l->omr);
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CSR_WRITE(l, TLP_TPD, 01);
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/* could wait for "setup frame" completion */
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CSR_WRITE(l, TLP_RPD, 01);
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CSR_WRITE(l, NAR_CSR6, l->omr | NAR_TEN | NAR_REN);
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return l;
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}
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@ -228,14 +195,14 @@ tlp_send(void *dev, char *buf, unsigned len)
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volatile struct desc *txd;
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unsigned txstat, loop;
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/* send a single frame with no T1_TER|T1_TCH designation */
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wbinv(buf, len);
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txd = &l->txd;
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txd = &l->txd[l->tx];
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txd->xd2 = htole32(VTOPHYS(buf));
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txd->xd1 = htole32(T1_FS | T1_LS | (len & T1_TBS_MASK));
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txd->xd1 &= htole32(T1_TER);
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txd->xd1 |= htole32(T1_FS | T1_LS | (len & T1_TBS_MASK));
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txd->xd0 = htole32(T0_OWN);
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wbinv(txd, sizeof(struct desc));
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CSR_WRITE(l, TLP_TPD, 01);
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CSR_WRITE(l, TDR_CSR1, 01);
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loop = 100;
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do {
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txstat = le32toh(txd->xd0);
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@ -247,6 +214,7 @@ tlp_send(void *dev, char *buf, unsigned len)
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printf("xmit failed\n");
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return -1;
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done:
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l->tx ^= 1;
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return len;
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}
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@ -259,7 +227,9 @@ tlp_recv(void *dev, char *buf, unsigned maxlen, unsigned timo)
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uint8_t *ptr;
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bound = 1000 * timo;
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#if 0
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printf("recving with %u sec. timeout\n", timo);
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#endif
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again:
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rxd = &l->rxd[l->rx];
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do {
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@ -276,127 +246,68 @@ printf("recving with %u sec. timeout\n", timo);
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rxd->xd0 = htole32(R0_OWN);
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wbinv(rxd, sizeof(struct desc));
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l->rx ^= 1;
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CSR_WRITE(l, TLP_RPD, 01);
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goto again;
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}
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/* good frame */
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len = ((rxstat & R0_FLMASK) >> 16) - 4 /* HASFCS */;
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if (len > maxlen)
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len = maxlen;
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len = ((rxstat & R0_FLMASK) >> 16) - 4 /* HASFCS */;
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if (len > maxlen)
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len = maxlen;
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ptr = l->rxstore[l->rx];
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inv(ptr, len);
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memcpy(buf, ptr, len);
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inv(ptr, len);
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memcpy(buf, ptr, len);
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rxd->xd0 = htole32(R0_OWN);
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wbinv(rxd, sizeof(struct desc));
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l->rx ^= 1;
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CSR_WRITE(l, TLP_OMR, l->omr); /* necessary? */
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return len;
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}
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static void
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size_srom(struct local *l)
|
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{
|
||||
/* determine 8/6 bit addressing SEEPROM */
|
||||
l->sromsft = 8;
|
||||
l->sromsft = (read_srom(l, 255) & 0x40000) ? 8 : 6;
|
||||
}
|
||||
|
||||
/*
|
||||
* bare SEEPROM access with bitbang'ing
|
||||
*/
|
||||
#define R110 6 /* SEEPROM/MDIO read op */
|
||||
#define W101 5 /* SEEPROM/MDIO write op */
|
||||
#define CS (1U << 0) /* hold chip select */
|
||||
#define CLK (1U << 1) /* clk bit */
|
||||
#define D1 (1U << 2) /* bit existence */
|
||||
#define VV (1U << 3) /* taken 0/1 from SEEPROM */
|
||||
|
||||
static int
|
||||
read_srom(struct local *l, int off)
|
||||
{
|
||||
unsigned data, v, i;
|
||||
|
||||
data = off & 0xff; /* A7-A0 */
|
||||
data |= R110 << l->sromsft; /* 110 for READ */
|
||||
|
||||
v = SROM_RD | SROM_SR;
|
||||
CSR_WRITE(l, TLP_APROM, v);
|
||||
v |= CS; /* hold CS */
|
||||
CSR_WRITE(l, TLP_APROM, v);
|
||||
|
||||
/* instruct R110 op. at off in MSB first order */
|
||||
for (i = (1 << (l->sromsft + 2)); i != 0; i >>= 1) {
|
||||
if (data & i)
|
||||
v |= D1;
|
||||
else
|
||||
v &= ~D1;
|
||||
CSR_WRITE(l, TLP_APROM, v);
|
||||
DELAY(10);
|
||||
CSR_WRITE(l, TLP_APROM, v | CLK);
|
||||
DELAY(10);
|
||||
}
|
||||
v &= ~D1;
|
||||
|
||||
/* read 16bit quantity in MSB first order */
|
||||
data = 0;
|
||||
for (i = 0; i < 16; i++) {
|
||||
CSR_WRITE(l, TLP_APROM, v);
|
||||
DELAY(10);
|
||||
CSR_WRITE(l, TLP_APROM, v | CLK);
|
||||
DELAY(10);
|
||||
data = (data << 1) | !!(CSR_READ(l, TLP_APROM) & VV);
|
||||
}
|
||||
/* turn off chip select */
|
||||
CSR_WRITE(l, TLP_APROM, 0);
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
/*
|
||||
* bare MII access with bitbang'ing
|
||||
*/
|
||||
#define MDI (1U << 19) /* taken 0/1 from MDIO */
|
||||
#define MII (1U << 18) /* read operation */
|
||||
#define MDO (1U << 17) /* bit existence */
|
||||
#define MDC (1U << 16) /* clock bit */
|
||||
#define R110 6 /* SEEPROM/MDIO read op */
|
||||
#define W101 5 /* SEEPROM/MDIO write op */
|
||||
#define CS (1U << 0) /* hold chip select */
|
||||
#define CLK (1U << 1) /* clk bit */
|
||||
#define D1 (1U << 2) /* bit existence */
|
||||
#define VV (1U << 3) /* taken 0/1 from SEEPROM */
|
||||
|
||||
static unsigned
|
||||
mii_read(struct local *l, int phy, int reg)
|
||||
{
|
||||
unsigned data, v, i;
|
||||
unsigned data, rv, v, i;
|
||||
|
||||
data = (R110 << 10) | (phy << 5) | reg;
|
||||
CSR_WRITE(l, TLP_APROM, MDO);
|
||||
CSR_WRITE(l, SPR_CSR9, MII_MDO);
|
||||
for (i = 0; i < 32; i++) {
|
||||
CSR_WRITE(l, TLP_APROM, MDO | MDC);
|
||||
CSR_WRITE(l, SPR_CSR9, MII_MDO | MII_MDC);
|
||||
DELAY(1);
|
||||
CSR_WRITE(l, TLP_APROM, MDO);
|
||||
CSR_WRITE(l, SPR_CSR9, MII_MDO);
|
||||
DELAY(1);
|
||||
}
|
||||
CSR_WRITE(l, TLP_APROM, 0);
|
||||
CSR_WRITE(l, SPR_CSR9, 0);
|
||||
v = 0; /* 4OP + 5ADDR + 5REG */
|
||||
for (i = (1 << 13); i != 0; i >>= 1) {
|
||||
if (data & i)
|
||||
v |= MDO;
|
||||
v |= MII_MDO;
|
||||
else
|
||||
v &= ~MDO;
|
||||
CSR_WRITE(l, TLP_APROM, v);
|
||||
v &= ~MII_MDO;
|
||||
CSR_WRITE(l, SPR_CSR9, v);
|
||||
DELAY(1);
|
||||
CSR_WRITE(l, TLP_APROM, v | MDC);
|
||||
CSR_WRITE(l, SPR_CSR9, v | MII_MDC);
|
||||
DELAY(1);
|
||||
CSR_WRITE(l, TLP_APROM, v);
|
||||
CSR_WRITE(l, SPR_CSR9, v);
|
||||
DELAY(1);
|
||||
}
|
||||
data = 0; /* 2TA + 16MDI */
|
||||
rv = 0; /* 2TA + 16MDI */
|
||||
for (i = 0; i < 18; i++) {
|
||||
CSR_WRITE(l, TLP_APROM, MII);
|
||||
CSR_WRITE(l, SPR_CSR9, MII_MIDIR);
|
||||
DELAY(1);
|
||||
data = (data << 1) | !!(CSR_READ(l, TLP_APROM) & MDI);
|
||||
CSR_WRITE(l, TLP_APROM, MII | MDC);
|
||||
rv = (data << 1) | !!(CSR_READ(l, SPR_CSR9) & MII_MDI);
|
||||
CSR_WRITE(l, SPR_CSR9, MII_MIDIR | MII_MDC);
|
||||
DELAY(1);
|
||||
}
|
||||
CSR_WRITE(l, TLP_APROM, 0);
|
||||
return data & 0xffff;
|
||||
CSR_WRITE(l, SPR_CSR9, 0);
|
||||
return rv & 0xffff;
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -406,28 +317,28 @@ mii_write(struct local *l, int phy, int reg, int val)
|
|||
|
||||
data = (W101 << 28) | (phy << 23) | (reg << 18) | (02 << 16);
|
||||
data |= val & 0xffff;
|
||||
CSR_WRITE(l, TLP_APROM, MDO);
|
||||
CSR_WRITE(l, SPR_CSR9, MII_MDO);
|
||||
for (i = 0; i < 32; i++) {
|
||||
CSR_WRITE(l, TLP_APROM, MDO | MDC);
|
||||
CSR_WRITE(l, SPR_CSR9, MII_MDO | MII_MDC);
|
||||
DELAY(1);
|
||||
CSR_WRITE(l, TLP_APROM, MDO);
|
||||
CSR_WRITE(l, SPR_CSR9, MII_MDO);
|
||||
DELAY(1);
|
||||
}
|
||||
CSR_WRITE(l, TLP_APROM, 0);
|
||||
CSR_WRITE(l, SPR_CSR9, 0);
|
||||
v = 0; /* 4OP + 5ADDR + 5REG + 2TA + 16DATA */
|
||||
for (i = (1 << 31); i != 0; i >>= 1) {
|
||||
if (data & i)
|
||||
v |= MDO;
|
||||
v |= MII_MDO;
|
||||
else
|
||||
v &= ~MDO;
|
||||
CSR_WRITE(l, TLP_APROM, v);
|
||||
v &= ~MII_MDO;
|
||||
CSR_WRITE(l, SPR_CSR9, v);
|
||||
DELAY(1);
|
||||
CSR_WRITE(l, TLP_APROM, v | MDC);
|
||||
CSR_WRITE(l, SPR_CSR9, v | MII_MDC);
|
||||
DELAY(1);
|
||||
CSR_WRITE(l, TLP_APROM, v);
|
||||
CSR_WRITE(l, SPR_CSR9, v);
|
||||
DELAY(1);
|
||||
}
|
||||
CSR_WRITE(l, TLP_APROM, 0);
|
||||
CSR_WRITE(l, SPR_CSR9, 0);
|
||||
}
|
||||
|
||||
#define MII_BMCR 0x00 /* Basic mode control register (rw) */
|
||||
|
|
|
|||
Loading…
Reference in New Issue