Split device_t/softc for dmac_*_xfer().
Rename some variables to avoid confusing.
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@ -1,4 +1,4 @@
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/* $NetBSD: dmacvar.h,v 1.9 2008/06/25 08:14:59 isaki Exp $ */
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/* $NetBSD: dmacvar.h,v 1.10 2008/06/25 13:30:24 isaki Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -78,7 +78,7 @@ struct dmac_channel_stat {
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struct dmac_dma_xfer ch_xfer;
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struct dmac_sg_array *ch_map; /* transfer map for arraychain mode */
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bus_dma_segment_t ch_seg[1];
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device_t ch_softc; /* device softc link */
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struct dmac_softc *ch_softc; /* device softc link */
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};
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/*
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@ -106,11 +106,12 @@ int dmac_free_channel(device_t, int, void *);
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/* ch, channel */
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struct dmac_dma_xfer *dmac_alloc_xfer(struct dmac_channel_stat *,
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bus_dma_tag_t, bus_dmamap_t);
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int dmac_load_xfer(device_t, struct dmac_dma_xfer *);
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int dmac_load_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
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int dmac_start_xfer(device_t, struct dmac_dma_xfer *);
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int dmac_start_xfer_offset(device_t, struct dmac_dma_xfer *, u_int, u_int);
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int dmac_abort_xfer(device_t, struct dmac_dma_xfer *);
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int dmac_start_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
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int dmac_start_xfer_offset(struct dmac_softc *, struct dmac_dma_xfer *,
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u_int, u_int);
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int dmac_abort_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
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/* Compatibility function: alloc, fill defaults, load */
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struct dmac_dma_xfer *dmac_prepare_xfer(struct dmac_channel_stat *,
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bus_dma_tag_t, bus_dmamap_t, int, int, void *);
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@ -1,4 +1,4 @@
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/* $NetBSD: intio_dmac.c,v 1.30 2008/06/25 08:14:59 isaki Exp $ */
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/* $NetBSD: intio_dmac.c,v 1.31 2008/06/25 13:30:24 isaki Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -34,7 +34,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: intio_dmac.c,v 1.30 2008/06/25 08:14:59 isaki Exp $");
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__KERNEL_RCSID(0, "$NetBSD: intio_dmac.c,v 1.31 2008/06/25 13:30:24 isaki Exp $");
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#include "opt_m680x0.h"
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@ -141,7 +141,7 @@ dmac_init_channels(struct dmac_softc *sc)
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for (i=0; i<DMAC_NCHAN; i++) {
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sc->sc_channels[i].ch_channel = i;
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sc->sc_channels[i].ch_name[0] = 0;
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sc->sc_channels[i].ch_softc = sc->sc_dev;
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sc->sc_channels[i].ch_softc = sc;
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bus_space_subregion(sc->sc_bst, sc->sc_bht,
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DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE,
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&sc->sc_channels[i].ch_bht);
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@ -241,11 +241,11 @@ dmac_alloc_channel(device_t self, int ch, const char *name, int normalv,
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}
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int
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dmac_free_channel(struct device *self, int ch, void *channel)
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dmac_free_channel(device_t self, int ch, void *channel)
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{
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struct intio_softc *intio = (void *)self;
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struct dmac_softc *sc = (void *)intio->sc_dmac;
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struct dmac_channel_stat *chan = &sc->sc_channels[ch];
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struct intio_softc *intio = device_private(self);
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struct dmac_softc *dmac = device_private(intio->sc_dmac);
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struct dmac_channel_stat *chan = &dmac->sc_channels[ch];
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DPRINTF(3, ("dmac_free_channel, %d\n", ch));
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DPRINTF(3, ("dmamap=%p\n", (void *)chan->ch_xfer.dx_dmamap));
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@ -288,9 +288,8 @@ dmac_alloc_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat,
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}
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int
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dmac_load_xfer(struct device *self, struct dmac_dma_xfer *xf)
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dmac_load_xfer(struct dmac_softc *dmac, struct dmac_dma_xfer *xf)
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{
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struct dmac_softc *sc = (void *)self;
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struct dmac_channel_stat *chan = xf->dx_channel;
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DPRINTF(3, ("dmac_load_xfer\n"));
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@ -304,11 +303,11 @@ dmac_load_xfer(struct device *self, struct dmac_dma_xfer *xf)
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xf->dx_nextsize = ~0;
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}
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bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
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bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr);
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bus_space_write_1(sc->sc_bst, chan->ch_bht,
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bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
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bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr);
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bus_space_write_1(dmac->sc_bst, chan->ch_bht,
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DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr));
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bus_space_write_4(sc->sc_bst, chan->ch_bht,
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bus_space_write_4(dmac->sc_bst, chan->ch_bht,
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DMAC_REG_DAR, (int) xf->dx_device);
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return 0;
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@ -319,7 +318,7 @@ dmac_prepare_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat,
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bus_dmamap_t dmamap, int dir, int scr, void *dar)
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{
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struct dmac_dma_xfer *xf;
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struct dmac_softc *sc = (struct dmac_softc *)chan->ch_softc;
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struct dmac_softc *dmac = chan->ch_softc;
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xf = dmac_alloc_xfer(chan, dmat, dmamap);
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@ -327,7 +326,7 @@ dmac_prepare_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat,
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xf->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK);
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xf->dx_device = dar;
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dmac_load_xfer(sc->sc_dev, xf);
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dmac_load_xfer(dmac, xf);
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return xf;
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}
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@ -340,16 +339,15 @@ static struct dmac_channel_stat *debugchan = 0;
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* Do the actual transfer.
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*/
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int
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dmac_start_xfer(struct device *self, struct dmac_dma_xfer *xf)
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dmac_start_xfer(struct dmac_softc *dmac, struct dmac_dma_xfer *xf)
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{
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return dmac_start_xfer_offset(self, xf, 0, 0);
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return dmac_start_xfer_offset(dmac, xf, 0, 0);
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}
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int
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dmac_start_xfer_offset(struct device *self, struct dmac_dma_xfer *xf,
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dmac_start_xfer_offset(struct dmac_softc *dmac, struct dmac_dma_xfer *xf,
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u_int offset, u_int size)
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{
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struct dmac_softc *sc = (void *)self;
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struct dmac_channel_stat *chan = xf->dx_channel;
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struct x68k_bus_dmamap *dmamap = xf->dx_dmamap;
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int go = DMAC_CCR_STR|DMAC_CCR_INT;
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@ -398,11 +396,11 @@ dmac_start_xfer_offset(struct device *self, struct dmac_dma_xfer *xf,
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go |= DMAC_CCR_CNT;
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xf->dx_nextoff += size;
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} else {
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bus_space_write_4(sc->sc_bst, chan->ch_bht,
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bus_space_write_4(dmac->sc_bst, chan->ch_bht,
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DMAC_REG_MAR,
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(int) dmamap->dm_segs[0].ds_addr
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+ offset);
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bus_space_write_2(sc->sc_bst, chan->ch_bht,
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bus_space_write_2(dmac->sc_bst, chan->ch_bht,
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DMAC_REG_MTCR, (int) size);
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xf->dx_nextoff = offset;
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xf->dx_nextsize = size;
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@ -413,16 +411,16 @@ dmac_start_xfer_offset(struct device *self, struct dmac_dma_xfer *xf,
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} else {
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#ifdef DMAC_ARRAYCHAIN
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c = dmac_program_arraychain(self, xf, offset, size);
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bus_space_write_4(sc->sc_bst, chan->ch_bht,
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bus_space_write_4(dmac->sc_bst, chan->ch_bht,
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DMAC_REG_BAR, (int) chan->ch_seg[0].ds_addr);
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bus_space_write_2(sc->sc_bst, chan->ch_bht,
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bus_space_write_2(dmac->sc_bst, chan->ch_bht,
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DMAC_REG_BTCR, c);
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#else
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panic("DMAC: unexpected use of arraychaining mode");
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#endif
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}
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bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
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bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
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/* START!! */
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DDUMPREGS(3, ("first start\n"));
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@ -435,12 +433,12 @@ dmac_start_xfer_offset(struct device *self, struct dmac_dma_xfer *xf,
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sizeof(struct dmac_sg_array) * c);
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#endif
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#endif
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bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, go);
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bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CCR, go);
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if (xf->dx_nextoff != ~0) {
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bus_space_write_4(sc->sc_bst, chan->ch_bht,
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bus_space_write_4(dmac->sc_bst, chan->ch_bht,
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DMAC_REG_BAR, xf->dx_nextoff);
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bus_space_write_2(sc->sc_bst, chan->ch_bht,
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bus_space_write_2(dmac->sc_bst, chan->ch_bht,
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DMAC_REG_BTCR, xf->dx_nextsize);
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}
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@ -449,7 +447,7 @@ dmac_start_xfer_offset(struct device *self, struct dmac_dma_xfer *xf,
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#ifdef DMAC_ARRAYCHAIN
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static int
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dmac_program_arraychain(struct device *self, struct dmac_dma_xfer *xf,
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dmac_program_arraychain(device_t self, struct dmac_dma_xfer *xf,
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u_int offset, u_int size)
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{
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struct dmac_channel_stat *chan = xf->dx_channel;
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@ -485,7 +483,7 @@ static int
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dmac_done(void *arg)
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{
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struct dmac_channel_stat *chan = arg;
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struct dmac_softc *sc = (void *)chan->ch_softc;
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struct dmac_softc *sc = chan->ch_softc;
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#ifdef DMAC_ARRAYCHAIN
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struct dmac_dma_xfer *xf = &chan->ch_xfer;
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struct x68k_bus_dmamap *map = xf->dx_dmamap;
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@ -531,7 +529,7 @@ static int
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dmac_error(void *arg)
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{
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struct dmac_channel_stat *chan = arg;
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struct dmac_softc *sc = (void *)chan->ch_softc;
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struct dmac_softc *sc = chan->ch_softc;
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printf("DMAC transfer error CSR=%02x, CER=%02x\n",
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bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR),
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@ -549,14 +547,13 @@ dmac_error(void *arg)
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}
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int
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dmac_abort_xfer(struct device *self, struct dmac_dma_xfer *xf)
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dmac_abort_xfer(struct dmac_softc *dmac, struct dmac_dma_xfer *xf)
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{
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struct dmac_softc *sc = (void *)self;
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struct dmac_channel_stat *chan = xf->dx_channel;
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bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR,
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bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CCR,
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DMAC_CCR_INT | DMAC_CCR_HLT);
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bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
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bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
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xf->dx_nextoff = xf->dx_nextsize = -1;
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return 0;
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@ -571,7 +568,7 @@ dmac_dump_regs(void)
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if ((chan == 0) || (dmacdebug & 0xf0))
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return 0;
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sc = (void *)chan->ch_softc;
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sc = chan->ch_softc;
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printf("DMAC channel %d registers\n", chan->ch_channel);
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printf("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x, "
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