Bugfix: reset 16-bit pcmcia in chip initialisation sequence.
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@ -1,4 +1,4 @@
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/* $NetBSD: pccbb.c,v 1.45 2000/08/28 09:26:38 haya Exp $ */
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/* $NetBSD: pccbb.c,v 1.46 2000/10/25 09:15:58 haya Exp $ */
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/*
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* Copyright (c) 1998, 1999 and 2000
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@ -745,6 +745,7 @@ pccbb_chipinit(sc)
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reg = pci_conf_read(pc, tag, PCI_BCR_INTR);
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reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */
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reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */
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reg |= CB_BCR_RESET_ENABLE; /* assert reset */
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pci_conf_write(pc, tag, PCI_BCR_INTR, reg);
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switch (sc->sc_chipset) {
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@ -785,6 +786,15 @@ pccbb_chipinit(sc)
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pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0);
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pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff);
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pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0);
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/* reset 16-bit pcmcia bus */
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bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh,
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0x800 + PCIC_INTR,
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bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh,
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0x800 + PCIC_INTR) & ~PCIC_INTR_RESET);
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/* turn of power */
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pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
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}
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@ -829,7 +839,7 @@ pccbb_pcmcia_attach_setup(sc, paa)
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* needs that while in PCMCIA mode.
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* 4) Clear any pending CSC interrupt.
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*/
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Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET);
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Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE);
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if (sc->sc_chipset == CB_TI113X) {
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Pcic_write(ph, PCIC_CSC_INTR, 0);
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} else {
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