Fix performance bug in pmax MachFlushDCache(). Old code disabled icache
and wasn't unrolled. This code runs cached and unrolled, giving an order of magnitude improvement in some cases (e.g., DMA-capable network devices). In use at Stanford DSG since late January 1995.
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jonathan
parent
0cd2332f66
commit
b2c7420e5a
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.S,v 1.11 1995/04/28 03:10:41 jonathan Exp $ */
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/* $NetBSD: locore.S,v 1.12 1995/04/28 23:17:51 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -2967,23 +2967,32 @@ END(MachFlushICache)
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LEAF(MachFlushDCache)
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mfc0 t0, MACH_COP_0_STATUS_REG # Save SR
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mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts.
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la v1, 1f
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or v1, MACH_UNCACHED_MEMORY_ADDR # Run uncached.
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j v1
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nop
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1:
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bc0f 1b # make sure stores are complete
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# BUG: should drain write buffer.
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# The insn above does not work on some all DEC machines, or all variants
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# of the mips architecture.
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li v1, MACH_SR_ISOL_CACHES
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mtc0 v1, MACH_COP_0_STATUS_REG
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nop
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addu a1, a1, a0 # compute ending address
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addu t1, a1, a0 # compute ending address
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1:
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addu a0, a0, 4
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bne a0, a1, 1b
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sb zero, 0(a0)
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sb zero, 4(a0)
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sb zero, 8(a0)
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sb zero, 12(a0)
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sb zero, 16(a0)
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sb zero, 20(a0)
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sb zero, 24(a0)
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addu a0, 32
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bltu a0, t1, 1b
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sb zero, -4(a0)
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nop # drain pipeline
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nop
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mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts
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nop
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j ra # return and run cached
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nop
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END(MachFlushDCache)
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@ -1,4 +1,4 @@
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/* $NetBSD: locore_r2000.S,v 1.11 1995/04/28 03:10:41 jonathan Exp $ */
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/* $NetBSD: locore_r2000.S,v 1.12 1995/04/28 23:17:51 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -2967,23 +2967,32 @@ END(MachFlushICache)
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LEAF(MachFlushDCache)
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mfc0 t0, MACH_COP_0_STATUS_REG # Save SR
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mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts.
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la v1, 1f
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or v1, MACH_UNCACHED_MEMORY_ADDR # Run uncached.
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j v1
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nop
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1:
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bc0f 1b # make sure stores are complete
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# BUG: should drain write buffer.
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# The insn above does not work on some all DEC machines, or all variants
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# of the mips architecture.
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li v1, MACH_SR_ISOL_CACHES
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mtc0 v1, MACH_COP_0_STATUS_REG
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nop
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addu a1, a1, a0 # compute ending address
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addu t1, a1, a0 # compute ending address
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1:
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addu a0, a0, 4
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bne a0, a1, 1b
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sb zero, 0(a0)
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sb zero, 4(a0)
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sb zero, 8(a0)
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sb zero, 12(a0)
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sb zero, 16(a0)
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sb zero, 20(a0)
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sb zero, 24(a0)
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addu a0, 32
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bltu a0, t1, 1b
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sb zero, -4(a0)
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nop # drain pipeline
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nop
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mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts
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nop
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j ra # return and run cached
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nop
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END(MachFlushDCache)
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@ -1,4 +1,4 @@
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/* $NetBSD: locore_r4000.S,v 1.11 1995/04/28 03:10:41 jonathan Exp $ */
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/* $NetBSD: locore_r4000.S,v 1.12 1995/04/28 23:17:51 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -2967,23 +2967,32 @@ END(MachFlushICache)
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LEAF(MachFlushDCache)
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mfc0 t0, MACH_COP_0_STATUS_REG # Save SR
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mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts.
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la v1, 1f
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or v1, MACH_UNCACHED_MEMORY_ADDR # Run uncached.
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j v1
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nop
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1:
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bc0f 1b # make sure stores are complete
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# BUG: should drain write buffer.
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# The insn above does not work on some all DEC machines, or all variants
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# of the mips architecture.
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li v1, MACH_SR_ISOL_CACHES
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mtc0 v1, MACH_COP_0_STATUS_REG
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nop
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addu a1, a1, a0 # compute ending address
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addu t1, a1, a0 # compute ending address
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1:
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addu a0, a0, 4
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bne a0, a1, 1b
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sb zero, 0(a0)
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sb zero, 4(a0)
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sb zero, 8(a0)
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sb zero, 12(a0)
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sb zero, 16(a0)
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sb zero, 20(a0)
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sb zero, 24(a0)
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addu a0, 32
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bltu a0, t1, 1b
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sb zero, -4(a0)
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nop # drain pipeline
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nop
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mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts
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nop
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j ra # return and run cached
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nop
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END(MachFlushDCache)
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.S,v 1.11 1995/04/28 03:10:41 jonathan Exp $ */
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/* $NetBSD: locore.S,v 1.12 1995/04/28 23:17:51 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -2967,23 +2967,32 @@ END(MachFlushICache)
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LEAF(MachFlushDCache)
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mfc0 t0, MACH_COP_0_STATUS_REG # Save SR
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mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts.
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la v1, 1f
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or v1, MACH_UNCACHED_MEMORY_ADDR # Run uncached.
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j v1
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nop
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1:
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bc0f 1b # make sure stores are complete
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# BUG: should drain write buffer.
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# The insn above does not work on some all DEC machines, or all variants
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# of the mips architecture.
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li v1, MACH_SR_ISOL_CACHES
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mtc0 v1, MACH_COP_0_STATUS_REG
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nop
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addu a1, a1, a0 # compute ending address
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addu t1, a1, a0 # compute ending address
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1:
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addu a0, a0, 4
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bne a0, a1, 1b
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sb zero, 0(a0)
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sb zero, 4(a0)
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sb zero, 8(a0)
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sb zero, 12(a0)
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sb zero, 16(a0)
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sb zero, 20(a0)
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sb zero, 24(a0)
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addu a0, 32
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bltu a0, t1, 1b
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sb zero, -4(a0)
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nop # drain pipeline
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nop
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mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts
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nop
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j ra # return and run cached
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nop
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END(MachFlushDCache)
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