diff --git a/sys/dev/ic/adw.c b/sys/dev/ic/adw.c index dbc27122aaf1..ff8498e3c809 100644 --- a/sys/dev/ic/adw.c +++ b/sys/dev/ic/adw.c @@ -1,4 +1,4 @@ -/* $NetBSD: adw.c,v 1.1 1998/09/26 16:10:40 dante Exp $ */ +/* $NetBSD: adw.c,v 1.2 1998/09/26 19:54:22 dante Exp $ */ /* * Generic driver for the Advanced Systems Inc. SCSI controllers @@ -65,7 +65,7 @@ #ifndef DDB #define Debugger() panic("should call debugger here (adv.c)") -#endif /* ! DDB */ +#endif /* ! DDB */ /******************************************************************************/ @@ -84,7 +84,7 @@ static void adw_start_ccbs __P((ADW_SOFTC *)); static int adw_scsi_cmd __P((struct scsipi_xfer *)); static int adw_build_req __P((struct scsipi_xfer *, ADW_CCB *)); -static void adw_build_sglist __P(( ADW_CCB *, ADW_SCSI_REQ_Q *)); +static void adw_build_sglist __P((ADW_CCB *, ADW_SCSI_REQ_Q *)); static void adwminphys __P((struct buf *)); static void adw_wide_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); @@ -120,7 +120,7 @@ struct scsipi_device adw_dev = /******************************************************************************/ -/* scsipi_xfer queue routines */ +/* scsipi_xfer queue routines */ /******************************************************************************/ /* @@ -166,7 +166,7 @@ adw_dequeue(sc) /******************************************************************************/ -/* Control Blocks routines */ +/* Control Blocks routines */ /******************************************************************************/ @@ -380,7 +380,7 @@ adw_start_ccbs(sc) /******************************************************************************/ -/* SCSI layer interfacing routines */ +/* SCSI layer interfacing routines */ /******************************************************************************/ @@ -388,11 +388,11 @@ int adw_init(sc) ADW_SOFTC *sc; { - u_int16_t warn_code; + u_int16_t warn_code; sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) | - ADW_LIB_VERSION_MINOR; + ADW_LIB_VERSION_MINOR; sc->cfg.chip_version = ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type); @@ -401,20 +401,18 @@ adw_init(sc) */ if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) { panic("adw_init: adw_find_signature failed"); - } - else - { + } else { AdvResetChip(sc->sc_iot, sc->sc_ioh); warn_code = AdvInitFromEEP(sc); - if(warn_code & ASC_WARN_EEPROM_CHKSUM) + if (warn_code & ASC_WARN_EEPROM_CHKSUM) printf("%s: Bad checksum found. " - "Setting default values\n", - sc->sc_dev.dv_xname); - if(warn_code & ASC_WARN_EEPROM_TERMINATION) + "Setting default values\n", + sc->sc_dev.dv_xname); + if (warn_code & ASC_WARN_EEPROM_TERMINATION) printf("%s: Bad bus termination setting." - "Using automatic termination.\n", - sc->sc_dev.dv_xname); + "Using automatic termination.\n", + sc->sc_dev.dv_xname); /* * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus @@ -440,28 +438,27 @@ adw_attach(sc) /* * Initialize the ASC3550. */ - switch(AdvInitAsc3550Driver(sc)) - { - case ASC_IERR_MCODE_CHKSUM: - panic("%s: Microcode checksum error", - sc->sc_dev.dv_xname); - break; + switch (AdvInitAsc3550Driver(sc)) { + case ASC_IERR_MCODE_CHKSUM: + panic("%s: Microcode checksum error", + sc->sc_dev.dv_xname); + break; - case ASC_IERR_ILLEGAL_CONNECTION: - panic("%s: All three connectors are in use", - sc->sc_dev.dv_xname); - break; + case ASC_IERR_ILLEGAL_CONNECTION: + panic("%s: All three connectors are in use", + sc->sc_dev.dv_xname); + break; - case ASC_IERR_REVERSED_CABLE: - panic("%s: Cable is reversed", - sc->sc_dev.dv_xname); - break; + case ASC_IERR_REVERSED_CABLE: + panic("%s: Cable is reversed", + sc->sc_dev.dv_xname); + break; - case ASC_IERR_SINGLE_END_DEVICE: - panic("%s: single-ended device is attached to" - " one of the connectors", - sc->sc_dev.dv_xname); - break; + case ASC_IERR_SINGLE_END_DEVICE: + panic("%s: single-ended device is attached to" + " one of the connectors", + sc->sc_dev.dv_xname); + break; } @@ -500,10 +497,9 @@ adw_attach(sc) return; /* (ENOMEM) */ ; } else if (i != ADW_MAX_CCB) { printf("%s: WARNING: only %d of %d control blocks" - " created\n", - sc->sc_dev.dv_xname, i, ADW_MAX_CCB); + " created\n", + sc->sc_dev.dv_xname, i, ADW_MAX_CCB); } - config_found(&sc->sc_dev, &sc->sc_link, scsiprint); } @@ -520,8 +516,8 @@ adwminphys(bp) /* - * start a scsi operation given the command and the data address. Also needs - * the unit, target and lu. + * start a scsi operation given the command and the data address. + * Also needs the unit, target and lu. */ static int adw_scsi_cmd(xs) @@ -597,8 +593,7 @@ adw_scsi_cmd(xs) ccb->xs = xs; ccb->timeout = xs->timeout; - if(adw_build_req(xs, ccb)) - { + if (adw_build_req(xs, ccb)) { s = splbio(); adw_queue_ccb(sc, ccb); splx(s); @@ -618,8 +613,7 @@ adw_scsi_cmd(xs) adw_timeout(ccb); } } - - return (COMPLETE); + return (COMPLETE); } @@ -628,14 +622,14 @@ adw_scsi_cmd(xs) */ static int adw_build_req(xs, ccb) - struct scsipi_xfer *xs; - ADW_CCB *ccb; + struct scsipi_xfer *xs; + ADW_CCB *ccb; { - struct scsipi_link *sc_link = xs->sc_link; - ADW_SOFTC *sc = sc_link->adapter_softc; - bus_dma_tag_t dmat = sc->sc_dmat; - ADW_SCSI_REQ_Q *scsiqp; - int error; + struct scsipi_link *sc_link = xs->sc_link; + ADW_SOFTC *sc = sc_link->adapter_softc; + bus_dma_tag_t dmat = sc->sc_dmat; + ADW_SCSI_REQ_Q *scsiqp; + int error; scsiqp = &ccb->scsiq; bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q)); @@ -658,7 +652,7 @@ adw_build_req(xs, ccb) scsiqp->target_id = sc_link->scsipi_scsi.target; scsiqp->target_lun = sc_link->scsipi_scsi.lun; - scsiqp->vsense_addr = (ulong) &ccb->scsi_sense; + scsiqp->vsense_addr = (ulong) & ccb->scsi_sense; scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr + ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense); scsiqp->sense_len = sizeof(struct scsipi_sense_data); @@ -673,14 +667,16 @@ adw_build_req(xs, ccb) #ifdef TFS if (xs->flags & SCSI_DATA_UIO) { error = bus_dmamap_load_uio(dmat, - ccb->dmamap_xfer, (struct uio *) xs->data, - (xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK); + ccb->dmamap_xfer, (struct uio *) xs->data, + (xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : + BUS_DMA_WAITOK); } else #endif /* TFS */ { error = bus_dmamap_load(dmat, - ccb->dmamap_xfer, xs->data, xs->datalen, NULL, - (xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK); + ccb->dmamap_xfer, xs->data, xs->datalen, NULL, + (xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : + BUS_DMA_WAITOK); } if (error) { @@ -698,10 +694,9 @@ adw_build_req(xs, ccb) adw_free_ccb(sc, ccb); return (0); } - bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0, ccb->dmamap_xfer->dm_mapsize, - (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : + (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); /* @@ -711,7 +706,8 @@ adw_build_req(xs, ccb) scsiqp->vdata_addr = (ulong) xs->data; scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr; scsiqp->sg_list_ptr = &ccb->sg_block[0]; - bzero(scsiqp->sg_list_ptr, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK); + bzero(scsiqp->sg_list_ptr, + sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK); adw_build_sglist(ccb, scsiqp); } else { /* @@ -732,17 +728,17 @@ adw_build_req(xs, ccb) */ static void adw_build_sglist(ccb, scsiqp) - ADW_CCB *ccb; - ADW_SCSI_REQ_Q *scsiqp; + ADW_CCB *ccb; + ADW_SCSI_REQ_Q *scsiqp; { struct scsipi_xfer *xs = ccb->xs; - ADW_SOFTC *sc = xs->sc_link->adapter_softc; - ADW_SG_BLOCK *sg_block = scsiqp->sg_list_ptr; - ulong sg_block_next_addr; /* block and its next */ - ulong sg_block_physical_addr; - int sg_block_index, i; /* how many SG entries */ + ADW_SOFTC *sc = xs->sc_link->adapter_softc; + ADW_SG_BLOCK *sg_block = scsiqp->sg_list_ptr; + ulong sg_block_next_addr; /* block and its next */ + ulong sg_block_physical_addr; + int sg_block_index, i; /* how many SG entries */ bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0]; - int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs; + int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs; sg_block_next_addr = (ulong) sg_block; /* allow math operation */ @@ -756,20 +752,17 @@ adw_build_sglist(ccb, scsiqp) */ sg_block_index = 0; - do - { + do { sg_block->first_entry_no = sg_block_index; - for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) - { + for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { sg_block->sg_list[i].sg_addr = sg_list->ds_addr; sg_block->sg_list[i].sg_count = sg_list->ds_len; - if (--sg_elem_cnt == 0) - { + if (--sg_elem_cnt == 0) { /* last entry, get out */ scsiqp->sg_entry_cnt = sg_block_index + i + 1; sg_block->last_entry_no = sg_block_index + i; - sg_block->sg_ptr = NULL;/* next link = NULL */ + sg_block->sg_ptr = NULL; /* next link = NULL */ return; } sg_list++; @@ -780,7 +773,7 @@ adw_build_sglist(ccb, scsiqp) sg_block_index += NO_OF_SG_PER_BLOCK; sg_block->sg_ptr = (ADW_SG_BLOCK *) sg_block_physical_addr; sg_block->last_entry_no = sg_block_index - 1; - sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virtual addr */ + sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */ } while (1); } @@ -893,7 +886,7 @@ adw_watchdog(arg) /******************************************************************************/ -/* NARROW and WIDE boards Interrupt callbacks */ +/* NARROW and WIDE boards Interrupt callbacks */ /******************************************************************************/ @@ -907,11 +900,11 @@ adw_wide_isr_callback(sc, scsiq) ADW_SOFTC *sc; ADW_SCSI_REQ_Q *scsiq; { - bus_dma_tag_t dmat = sc->sc_dmat; - ADW_CCB *ccb = (ADW_CCB *) scsiq->ccb_ptr; - struct scsipi_xfer *xs = ccb->xs; + bus_dma_tag_t dmat = sc->sc_dmat; + ADW_CCB *ccb = (ADW_CCB *) scsiq->ccb_ptr; + struct scsipi_xfer *xs = ccb->xs; struct scsipi_sense_data *s1, *s2; -// int underrun = ASC_FALSE; + //int underrun = ASC_FALSE; untimeout(adw_timeout, ccb); @@ -927,23 +920,19 @@ adw_wide_isr_callback(sc, scsiq) BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(dmat, ccb->dmamap_xfer); } - if ((ccb->flags & CCB_ALLOC) == 0) { printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname); Debugger(); return; } - - /* * Check for an underrun condition. */ -/* if (xs->request_bufflen != 0 && scsiqp->data_cnt != 0) { - ASC_DBG1(1, "adw_isr_callback: underrun condition %lu bytes\n", - scsiqp->data_cnt); - underrun = ASC_TRUE; - } -*/ + /* + * if (xs->request_bufflen != 0 && scsiqp->data_cnt != 0) { + * ASC_DBG1(1, "adw_isr_callback: underrun condition %lu bytes\n", + * scsiqp->data_cnt); underrun = ASC_TRUE; } + */ /* * 'done_status' contains the command's ending status. */ @@ -966,10 +955,10 @@ adw_wide_isr_callback(sc, scsiq) * Note: There is no way yet to indicate the number * of underrun bytes. */ -/* if (xs->error == XS_NOERROR && underrun == ASC_TRUE) { - scp->result = HOST_BYTE(DID_UNDERRUN); - } -*/ break; + /* + * if (xs->error == XS_NOERROR && underrun == ASC_TRUE) { + * scp->result = HOST_BYTE(DID_UNDERRUN); } + */ break; case QD_WITH_ERROR: switch (scsiq->host_status) { diff --git a/sys/dev/ic/adwlib.c b/sys/dev/ic/adwlib.c index d5023a64419e..a0c71aa0e502 100644 --- a/sys/dev/ic/adwlib.c +++ b/sys/dev/ic/adwlib.c @@ -1,4 +1,4 @@ -/* $NetBSD: adwlib.c,v 1.1 1998/09/26 16:10:41 dante Exp $ */ +/* $NetBSD: adwlib.c,v 1.2 1998/09/26 19:54:22 dante Exp $ */ /* * Low level routines for the Advanced Systems Inc. SCSI controllers chips @@ -78,16 +78,17 @@ /* Static Functions */ static u_int16_t AdvGetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, - ADWEEP_CONFIG *)); -static u_int16_t AdvReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int)); + ADWEEP_CONFIG *)); +static u_int16_t AdvReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, + int)); static void AdvWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); static void AdvSetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, - ADWEEP_CONFIG *)); + ADWEEP_CONFIG *)); static int AdvSendScsiCmd __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); static void AdvInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); -static void DvcSleepMilliSecond __P((ulong)); -static void DvcDelayMicroSecond __P((ulong)); +static void DvcSleepMilliSecond __P((ulong)); +static void DvcDelayMicroSecond __P((ulong)); /* @@ -100,40 +101,40 @@ static void DvcDelayMicroSecond __P((ulong)); */ static ADWEEP_CONFIG Default_EEPROM_Config = { - ADW_EEPROM_BIOS_ENABLE, /* cfg_msw */ - 0x0000, /* cfg_lsw */ - 0xFFFF, /* disc_enable */ - 0xFFFF, /* wdtr_able */ - 0xFFFF, /* sdtr_able */ - 0xFFFF, /* start_motor */ - 0xFFFF, /* tagqng_able */ - 0xFFFF, /* bios_scan */ - 0, /* scam_tolerant */ - 7, /* adapter_scsi_id */ - 0, /* bios_boot_delay */ - 3, /* scsi_reset_delay */ - 0, /* bios_id_lun */ - 0, /* termination */ - 0, /* reserved1 */ - 0xFFEF, /* bios_ctrl */ - 0xFFFF, /* ultra_able */ - 0, /* reserved2 */ - ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ - ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ - 0, /* dvc_cntl */ - 0, /* bug_fix */ - 0, /* serial_number_word1 */ - 0, /* serial_number_word2 */ - 0, /* serial_number_word3 */ - 0, /* check_sum */ - { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* oem_name[16] */ - 0, /* dvc_err_code */ - 0, /* adv_err_code */ - 0, /* adv_err_addr */ - 0, /* saved_dvc_err_code */ - 0, /* saved_adv_err_code */ - 0, /* saved_adv_err_addr */ - 0 /* num_of_err */ + ADW_EEPROM_BIOS_ENABLE, /* cfg_msw */ + 0x0000, /* cfg_lsw */ + 0xFFFF, /* disc_enable */ + 0xFFFF, /* wdtr_able */ + 0xFFFF, /* sdtr_able */ + 0xFFFF, /* start_motor */ + 0xFFFF, /* tagqng_able */ + 0xFFFF, /* bios_scan */ + 0, /* scam_tolerant */ + 7, /* adapter_scsi_id */ + 0, /* bios_boot_delay */ + 3, /* scsi_reset_delay */ + 0, /* bios_id_lun */ + 0, /* termination */ + 0, /* reserved1 */ + 0xFFEF, /* bios_ctrl */ + 0xFFFF, /* ultra_able */ + 0, /* reserved2 */ + ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ + ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ + 0, /* dvc_cntl */ + 0, /* bug_fix */ + 0, /* serial_number_word1 */ + 0, /* serial_number_word2 */ + 0, /* serial_number_word3 */ + 0, /* check_sum */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* oem_name[16] */ + 0, /* dvc_err_code */ + 0, /* adv_err_code */ + 0, /* adv_err_addr */ + 0, /* saved_dvc_err_code */ + 0, /* saved_adv_err_code */ + 0, /* saved_adv_err_addr */ + 0 /* num_of_err */ }; /* @@ -146,20 +147,21 @@ Default_EEPROM_Config = { */ int AdvInitAsc3550Driver(sc) - ADW_SOFTC *sc; +ADW_SOFTC *sc; { - bus_space_tag_t iot = sc->sc_iot; - bus_space_handle_t ioh = sc->sc_ioh; - u_int16_t warn_code; - u_int32_t sum; - int begin_addr; - int end_addr; - int code_sum; - int word; - int rql_addr; /* RISC Queue List address */ - int i; - u_int16_t scsi_cfg1; - u_int8_t biosmem[ASC_MC_BIOSLEN]; /* BIOS RISC Memory 0x40-0x8F */ + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; + u_int16_t warn_code; + u_int32_t sum; + int begin_addr; + int end_addr; + int code_sum; + int word; + int rql_addr; /* RISC Queue List address */ + int i; + u_int16_t scsi_cfg1; + u_int8_t biosmem[ASC_MC_BIOSLEN]; /* BIOS RISC Memory + * 0x40-0x8F */ warn_code = 0; @@ -184,7 +186,7 @@ AdvInitAsc3550Driver(sc) ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); for (word = 0; word < adv_mcode_size; word += 2) { ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, - *((u_int16_t *) (&adv_mcode[word]))); + *((u_int16_t *) (&adv_mcode[word]))); } /* @@ -215,7 +217,7 @@ AdvInitAsc3550Driver(sc) /* * Calculate and write the microcode code checksum to the microcode - * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). + * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). */ ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); @@ -235,7 +237,7 @@ AdvInitAsc3550Driver(sc) * Initialize microcode operating variables */ ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_ADAPTER_SCSI_ID, - sc->chip_scsi_id); + sc->chip_scsi_id); /* * If the PCI Configuration Command Register "Parity Error Response @@ -248,7 +250,6 @@ AdvInitAsc3550Driver(sc) word |= CONTROL_FLAG_IGNORE_PERR; ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); } - /* * Set default microcode operating variables for WDTR, SDTR, and * command tag queuing based on the EEPROM configuration values. @@ -263,7 +264,7 @@ AdvInitAsc3550Driver(sc) * SDTR target mask overrides the ULTRA target mask in the * microcode so it is safe to set this value without determining * whether the device supports SDTR. - * + * * Note: There is no way to know whether a device supports ULTRA * speed without attempting a SDTR ULTRA speed negotiation with * the device. The device will reject the speed if it does not @@ -281,8 +282,8 @@ AdvInitAsc3550Driver(sc) * after it is started below. */ ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, - ADW_PARITY_EN | ADW_SEL_TMO_LONG | ADW_OUR_ID_EN | sc->chip_scsi_id); - + ADW_PARITY_EN | ADW_SEL_TMO_LONG | ADW_OUR_ID_EN | sc->chip_scsi_id); + /* * Determine SCSI_CFG1 Microcode Default Value. * @@ -297,17 +298,19 @@ AdvInitAsc3550Driver(sc) * If all three connectors are in use, return an error. */ if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || - (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { + (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { return ASC_IERR_ILLEGAL_CONNECTION; } - /* * If the internal narrow cable is reversed all of the SCSI_CTRL * register signals will be set. Check for and return an error if * this condition is found. */ - if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) + if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == + 0x3F07) { + return ASC_IERR_REVERSED_CABLE; + } /* * If this is a differential board and a single-ended device @@ -326,29 +329,40 @@ AdvInitAsc3550Driver(sc) */ if (sc->cfg.termination == 0) { /* - * The software always controls termination by setting ADW_TERM_CTL_SEL. - * If ADW_TERM_CTL_SEL were set to 0, the hardware would set termination. + * The software always controls termination by setting + * ADW_TERM_CTL_SEL. + * If ADW_TERM_CTL_SEL were set to 0, the hardware would + * set termination. */ sc->cfg.termination |= ADW_TERM_CTL_SEL; - switch(scsi_cfg1 & ADW_CABLE_DETECT) - { + switch (scsi_cfg1 & ADW_CABLE_DETECT) { /* ADW_TERM_CTL_H: on, ADW_TERM_CTL_L: on */ - case 0x3: case 0x7: case 0xB: case 0xD: case 0xE: case 0xF: - sc->cfg.termination |= (ADW_TERM_CTL_H | ADW_TERM_CTL_L); - break; + case 0x3: + case 0x7: + case 0xB: + case 0xD: + case 0xE: + case 0xF: + sc->cfg.termination |= (ADW_TERM_CTL_H | + ADW_TERM_CTL_L); + break; /* ADW_TERM_CTL_H: on, ADW_TERM_CTL_L: off */ - case 0x1: case 0x5: case 0x9: case 0xA: case 0xC: - sc->cfg.termination |= ADW_TERM_CTL_H; - break; + case 0x1: + case 0x5: + case 0x9: + case 0xA: + case 0xC: + sc->cfg.termination |= ADW_TERM_CTL_H; + break; /* ADW_TERM_CTL_H: off, ADW_TERM_CTL_L: off */ - case 0x2: case 0x6: - break; + case 0x2: + case 0x6: + break; } } - /* * Clear any set ADW_TERM_CTL_H and ADW_TERM_CTL_L bits. */ @@ -372,7 +386,7 @@ AdvInitAsc3550Driver(sc) * after it is started below. */ ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, - ADW_FLTR_11_TO_20NS | scsi_cfg1); + ADW_FLTR_11_TO_20NS | scsi_cfg1); /* * Set SEL_MASK Microcode Default Value @@ -381,7 +395,7 @@ AdvInitAsc3550Driver(sc) * after it is started below. */ ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, - ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); + ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); /* * Link all the RISC Queue Lists together in a doubly-linked @@ -389,15 +403,18 @@ AdvInitAsc3550Driver(sc) * * Skip the NULL (0) queue which is not used. */ - for (i = 1, rql_addr = ASC_MC_RISC_Q_LIST_BASE + ASC_MC_RISC_Q_LIST_SIZE; - i < ASC_MC_RISC_Q_TOTAL_CNT; - i++, rql_addr += ASC_MC_RISC_Q_LIST_SIZE) { + for (i = 1, rql_addr = ASC_MC_RISC_Q_LIST_BASE+ASC_MC_RISC_Q_LIST_SIZE; + i < ASC_MC_RISC_Q_TOTAL_CNT; + i++, rql_addr += ASC_MC_RISC_Q_LIST_SIZE) { /* - * Set the current RISC Queue List's RQL_FWD and RQL_BWD pointers - * in a one word write and set the state (RQL_STATE) to free. + * Set the current RISC Queue List's RQL_FWD and + * RQL_BWD pointers in a one word write and set + * the state (RQL_STATE) to free. */ - ADW_WRITE_WORD_LRAM(iot, ioh, rql_addr, ((i + 1) + ((i - 1) << 8))); - ADW_WRITE_BYTE_LRAM(iot, ioh, rql_addr + RQL_STATE, ASC_MC_QS_FREE); + ADW_WRITE_WORD_LRAM(iot, ioh, rql_addr, + ((i + 1) + ((i - 1) << 8))); + ADW_WRITE_BYTE_LRAM(iot, ioh, rql_addr + RQL_STATE, + ASC_MC_QS_FREE); } /* @@ -406,17 +423,22 @@ AdvInitAsc3550Driver(sc) * Both sets of pointers are initialized with the same values: * ASC_MC_RISC_Q_FIRST(0x01) and ASC_MC_RISC_Q_LAST (0xFF). */ - ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_READY, ASC_MC_RISC_Q_FIRST); - ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_DONE, ASC_MC_RISC_Q_LAST); + ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_READY, + ASC_MC_RISC_Q_FIRST); + ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_DONE, + ASC_MC_RISC_Q_LAST); - ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_RISC_NEXT_READY, ASC_MC_RISC_Q_FIRST); - ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_RISC_NEXT_DONE, ASC_MC_RISC_Q_LAST); + ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_RISC_NEXT_READY, + ASC_MC_RISC_Q_FIRST); + ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_RISC_NEXT_DONE, + ASC_MC_RISC_Q_LAST); /* * Finally, set up the last RISC Queue List (255) with * a NULL forward pointer. */ - ADW_WRITE_WORD_LRAM(iot, ioh, rql_addr, (ASC_MC_NULL_Q + ((i - 1) << 8))); + ADW_WRITE_WORD_LRAM(iot, ioh, rql_addr, + (ASC_MC_NULL_Q + ((i - 1) << 8))); ADW_WRITE_BYTE_LRAM(iot, ioh, rql_addr + RQL_STATE, ASC_MC_QS_FREE); ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, @@ -427,7 +449,7 @@ AdvInitAsc3550Driver(sc) /* finally, finally, gentlemen, start your engine */ ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); - + return warn_code; } @@ -445,13 +467,13 @@ AdvInitAsc3550Driver(sc) */ int AdvInitFromEEP(sc) - ADW_SOFTC *sc; + ADW_SOFTC *sc; { - bus_space_tag_t iot = sc->sc_iot; - bus_space_handle_t ioh = sc->sc_ioh; - u_int16_t warn_code; - ADWEEP_CONFIG eep_config; - int eep_chksum, i; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; + u_int16_t warn_code; + ADWEEP_CONFIG eep_config; + int eep_chksum, i; warn_code = 0; @@ -462,17 +484,16 @@ AdvInitFromEEP(sc) * Set default values if a bad checksum is found. */ eep_chksum = AdvGetEEPConfig(iot, ioh, &eep_config); - - if (eep_chksum != eep_config.check_sum) - { + + if (eep_chksum != eep_config.check_sum) { warn_code |= ASC_WARN_EEPROM_CHKSUM; /* * Set EEPROM default values. */ for (i = 0; i < sizeof(ADWEEP_CONFIG); i++) { - *((u_int8_t *) &eep_config + i) = - *((u_int8_t *) &Default_EEPROM_Config + i); + *((u_int8_t *) & eep_config + i) = + *((u_int8_t *) & Default_EEPROM_Config + i); } /* @@ -488,7 +509,6 @@ AdvInitFromEEP(sc) AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); AdvSetEEPConfig(iot, ioh, &eep_config); } - /* * Set ADW_DVC_VAR and ADW_DVC_CFG variables from the * EEPROM configuration that was read. @@ -526,31 +546,23 @@ AdvInitFromEEP(sc) eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; } } - - if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) - { + if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; - } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) - { + } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { /* If the value is zero, assume it is uninitialized. */ - if (eep_config.max_dvc_qng == 0) - { + if (eep_config.max_dvc_qng == 0) { eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; - } else - { + } else { eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; } } - /* * If 'max_dvc_qng' is greater than 'max_host_qng', then * set 'max_dvc_qng' to 'max_host_qng'. */ - if (eep_config.max_dvc_qng > eep_config.max_host_qng) - { + if (eep_config.max_dvc_qng > eep_config.max_host_qng) { eep_config.max_dvc_qng = eep_config.max_host_qng; } - /* * Set ADW_DVC_VAR 'max_host_qng' and ADW_DVC_CFG 'max_dvc_qng' * values based on possibly adjusted EEPROM values. @@ -567,30 +579,25 @@ AdvInitFromEEP(sc) * value check that a legal value is set and set the ADW_DVC_CFG * 'termination' field appropriately. */ - if (eep_config.termination == 0) - { + if (eep_config.termination == 0) { sc->cfg.termination = 0; /* auto termination */ - } else - { + } else { /* Enable manual control with low off / high off. */ - if (eep_config.termination == 1) - { + if (eep_config.termination == 1) { sc->cfg.termination = ADW_TERM_CTL_SEL; - /* Enable manual control with low off / high on. */ - } else if (eep_config.termination == 2) - { + /* Enable manual control with low off / high on. */ + } else if (eep_config.termination == 2) { sc->cfg.termination = ADW_TERM_CTL_SEL | ADW_TERM_CTL_H; - /* Enable manual control with low on / high on. */ - } else if (eep_config.termination == 3) - { - sc->cfg.termination = ADW_TERM_CTL_SEL | ADW_TERM_CTL_H | ADW_TERM_CTL_L; - } else - { + /* Enable manual control with low on / high on. */ + } else if (eep_config.termination == 3) { + sc->cfg.termination = ADW_TERM_CTL_SEL | + ADW_TERM_CTL_H | ADW_TERM_CTL_L; + } else { /* - * The EEPROM 'termination' field contains a bad value. Use - * automatic termination instead. + * The EEPROM 'termination' field contains a bad value. + * Use automatic termination instead. */ sc->cfg.termination = 0; warn_code |= ASC_WARN_EEPROM_TERMINATION; @@ -605,23 +612,22 @@ AdvInitFromEEP(sc) * * Return a checksum based on the EEPROM configuration read. */ -static u_int16_t +static u_int16_t AdvGetEEPConfig(iot, ioh, cfg_buf) - bus_space_tag_t iot; - bus_space_handle_t ioh; - ADWEEP_CONFIG *cfg_buf; + bus_space_tag_t iot; + bus_space_handle_t ioh; + ADWEEP_CONFIG *cfg_buf; { - u_int16_t wval, chksum; - u_int16_t *wbuf; - int eep_addr; + u_int16_t wval, chksum; + u_int16_t *wbuf; + int eep_addr; wbuf = (u_int16_t *) cfg_buf; chksum = 0; for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; - eep_addr < ASC_EEP_DVC_CFG_END; - eep_addr++, wbuf++) - { + eep_addr < ASC_EEP_DVC_CFG_END; + eep_addr++, wbuf++) { wval = AdvReadEEPWord(iot, ioh, eep_addr); chksum += wval; *wbuf = wval; @@ -629,9 +635,8 @@ AdvGetEEPConfig(iot, ioh, cfg_buf) *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); wbuf++; for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; - eep_addr < ASC_EEP_MAX_WORD_ADDR; - eep_addr++, wbuf++) - { + eep_addr < ASC_EEP_MAX_WORD_ADDR; + eep_addr++, wbuf++) { *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); } return chksum; @@ -640,16 +645,16 @@ AdvGetEEPConfig(iot, ioh, cfg_buf) /* * Read the EEPROM from specified location */ -static u_int16_t +static u_int16_t AdvReadEEPWord(iot, ioh, eep_word_addr) - bus_space_tag_t iot; - bus_space_handle_t ioh; - int eep_word_addr; + bus_space_tag_t iot; + bus_space_handle_t ioh; + int eep_word_addr; { - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, - ASC_EEP_CMD_READ | eep_word_addr); - AdvWaitEEPCmd(iot, iot); - return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); + ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, + ASC_EEP_CMD_READ | eep_word_addr); + AdvWaitEEPCmd(iot, iot); + return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); } /* @@ -657,18 +662,16 @@ AdvReadEEPWord(iot, ioh, eep_word_addr) */ static void AdvWaitEEPCmd(iot, ioh) - bus_space_tag_t iot; - bus_space_handle_t ioh; + bus_space_tag_t iot; + bus_space_handle_t ioh; { DvcSleepMilliSecond(1); - for(;;) - { + for (;;) { if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & - ASC_EEP_CMD_DONE) { + ASC_EEP_CMD_DONE) { break; } - DvcSleepMilliSecond(1); } @@ -680,12 +683,12 @@ AdvWaitEEPCmd(iot, ioh) */ static void AdvSetEEPConfig(iot, ioh, cfg_buf) - bus_space_tag_t iot; - bus_space_handle_t ioh; - ADWEEP_CONFIG *cfg_buf; + bus_space_tag_t iot; + bus_space_handle_t ioh; + ADWEEP_CONFIG *cfg_buf; { - u_int16_t *wbuf; - u_int16_t addr, chksum; + u_int16_t *wbuf; + u_int16_t addr, chksum; wbuf = (u_int16_t *) cfg_buf; chksum = 0; @@ -697,12 +700,11 @@ AdvSetEEPConfig(iot, ioh, cfg_buf) * Write EEPROM from word 0 to word 15 */ for (addr = ASC_EEP_DVC_CFG_BEGIN; - addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) - { + addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { chksum += *wbuf; ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); ADW_WRITE_WORD_REGISTER(iot, ioh, - IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); + IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); AdvWaitEEPCmd(iot, ioh); DvcSleepMilliSecond(ASC_EEP_DELAY_MS); } @@ -712,23 +714,22 @@ AdvSetEEPConfig(iot, ioh, cfg_buf) */ ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, - ASC_EEP_CMD_WRITE | addr); + ASC_EEP_CMD_WRITE | addr); AdvWaitEEPCmd(iot, ioh); - wbuf++; /* skip over check_sum */ + wbuf++; /* skip over check_sum */ /* - * Write EEPROM OEM name at words 19 to 26 + * Write EEPROM OEM name at words 19 to 26 */ for (addr = ASC_EEP_DVC_CTL_BEGIN; - addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) - { + addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); ADW_WRITE_WORD_REGISTER(iot, ioh, - IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); + IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); AdvWaitEEPCmd(iot, ioh); } ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, - ASC_EEP_CMD_WRITE_DISABLE); + ASC_EEP_CMD_WRITE_DISABLE); AdvWaitEEPCmd(iot, ioh); return; } @@ -749,26 +750,28 @@ AdvSetEEPConfig(iot, ioh, cfg_buf) */ void AdvResetChip(iot, ioh) - bus_space_tag_t iot; - bus_space_handle_t ioh; + bus_space_tag_t iot; + bus_space_handle_t ioh; { - u_int16_t word; - u_int8_t byte; + u_int16_t word; + u_int8_t byte; /* * Reset Chip. */ - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, ADW_CTRL_REG_CMD_RESET); + ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, + ADW_CTRL_REG_CMD_RESET); DvcSleepMilliSecond(100); - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG); + ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, + ADW_CTRL_REG_CMD_WR_IO_REG); /* * Initialize Chip registers. - * + * * Note: Don't remove the use of a temporary variable in the following - * code, otherwise the Microsoft C compiler will turn the following lines - * into a no-op. + * code, otherwise the Microsoft C compiler will turn the following + * lines into a no-op. */ byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_MEM_CFG); byte |= RAM_SZ_8KB; @@ -783,7 +786,7 @@ AdvResetChip(iot, ioh) * of 128 bytes. This register is only accessible to the host. */ ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, - START_CTL_EMFU | READ_CMD_MRM); + START_CTL_EMFU | READ_CMD_MRM); } /* @@ -802,10 +805,10 @@ AdvResetChip(iot, ioh) */ int AdvExeScsiQueue(sc, scsiq) - ADW_SOFTC *sc; - ADW_SCSI_REQ_Q *scsiq; + ADW_SOFTC *sc; + ADW_SCSI_REQ_Q *scsiq; { - return AdvSendScsiCmd(sc, scsiq); + return AdvSendScsiCmd(sc, scsiq); } /* @@ -818,9 +821,9 @@ AdvExeScsiQueue(sc, scsiq) */ int AdvResetCCB(sc) - ADW_SOFTC *sc; + ADW_SOFTC *sc; { - int status; + int status; status = AdvSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET, 0L, 0); @@ -834,18 +837,18 @@ AdvResetCCB(sc) */ void AdvResetSCSIBus(sc) - ADW_SOFTC *sc; + ADW_SOFTC *sc; { - bus_space_tag_t iot = sc->sc_iot; - bus_space_handle_t ioh = sc->sc_ioh; - u_int16_t scsi_ctrl; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; + u_int16_t scsi_ctrl; /* * The microcode currently sets the SCSI Bus Reset signal while * handling the AdvSendIdleCmd() IDLE_CMD_SCSI_RESET command above. - * But the SCSI Bus Reset Hold Time in the microcode is not deterministic + * But the SCSI Bus Reset Hold Time in the uCode is not deterministic * (it may in fact be for less than the SCSI Spec. minimum of 25 us). * Therefore on return the Adv Library sets the SCSI Bus Reset signal * for ASC_SCSI_RESET_HOLD_TIME_US, which is defined to be greater @@ -853,10 +856,10 @@ AdvResetSCSIBus(sc) */ scsi_ctrl = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL); ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL, - scsi_ctrl | ADW_SCSI_CTRL_RSTOUT); - DvcDelayMicroSecond( (u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); + scsi_ctrl | ADW_SCSI_CTRL_RSTOUT); + DvcDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL, - scsi_ctrl & ~ADW_SCSI_CTRL_RSTOUT); + scsi_ctrl & ~ADW_SCSI_CTRL_RSTOUT); DvcSleepMilliSecond((ulong) sc->scsi_reset_wait * 1000); } @@ -883,39 +886,34 @@ AdvResetSCSIBus(sc) */ int AdvISR(sc) - ADW_SOFTC *sc; + ADW_SOFTC *sc; { - bus_space_tag_t iot = sc->sc_iot; - bus_space_handle_t ioh = sc->sc_ioh; - u_int8_t int_stat; - u_int16_t next_done_loc, target_bit; - int completed_q; - ADW_SCSI_REQ_Q *scsiq; - ASC_REQ_SENSE *sense_data; - int ret; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; + u_int8_t int_stat; + u_int16_t next_done_loc, target_bit; + int completed_q; + ADW_SCSI_REQ_Q *scsiq; + ASC_REQ_SENSE *sense_data; + int ret; - ret = (ADW_IS_INT_PENDING(iot, ioh))? ADW_TRUE : ADW_FALSE; + ret = (ADW_IS_INT_PENDING(iot, ioh)) ? ADW_TRUE : ADW_FALSE; /* Reading the register clears the interrupt. */ int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); - if (int_stat & ADW_INTR_STATUS_INTRB) - { + if (int_stat & ADW_INTR_STATUS_INTRB) { sc->idle_cmd_done = ADW_TRUE; } - /* * Notify the driver of a hardware detected SCSI Bus Reset. */ - if (int_stat & ADW_INTR_STATUS_INTRC) - { - if (sc->sbreset_callback) - { - (*(ADW_SBRESET_CALLBACK) sc->sbreset_callback)(sc); + if (int_stat & ADW_INTR_STATUS_INTRC) { + if (sc->sbreset_callback) { + (*(ADW_SBRESET_CALLBACK) sc->sbreset_callback) (sc); } } - /* * ASC_MC_HOST_NEXT_DONE (0x129) is actually the last completed RISC * Queue List request. Its forward pointer (RQL_FWD) points to the @@ -928,13 +926,12 @@ AdvISR(sc) ADW_READ_BYTE_LRAM(iot, ioh, next_done_loc, completed_q); /* Loop until all completed Q's are processed. */ - while (completed_q != ASC_MC_NULL_Q) - { + while (completed_q != ASC_MC_NULL_Q) { ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_DONE, - completed_q); + completed_q); next_done_loc = ASC_MC_RISC_Q_LIST_BASE + - (completed_q * ASC_MC_RISC_Q_LIST_SIZE); + (completed_q * ASC_MC_RISC_Q_LIST_SIZE); /* * Read the ADW_SCSI_REQ_Q virtual address pointer from @@ -945,14 +942,14 @@ AdvISR(sc) * more information on the RISC list structure. */ { - ushort lsw, msw; + ushort lsw, msw; ADW_READ_WORD_LRAM(iot, ioh, - next_done_loc + RQL_PHYADDR, lsw); + next_done_loc + RQL_PHYADDR, lsw); ADW_READ_WORD_LRAM(iot, ioh, - next_done_loc + RQL_PHYADDR + 2, msw); + next_done_loc + RQL_PHYADDR + 2, msw); scsiq = (ADW_SCSI_REQ_Q *) - (((u_int32_t) msw << 16) | lsw); + (((u_int32_t) msw << 16) | lsw); } target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); @@ -966,10 +963,10 @@ AdvISR(sc) * Check Condition handling */ if ((scsiq->done_status == QD_WITH_ERROR) && - (scsiq->scsi_status == SS_CHK_CONDITION) && - (sense_data = (ASC_REQ_SENSE *) scsiq->vsense_addr) != 0 && - (scsiq->orig_sense_len - scsiq->sense_len) >= ASC_MIN_SENSE_LEN) - { + (scsiq->scsi_status == SS_CHK_CONDITION) && + (sense_data = (ASC_REQ_SENSE *) scsiq->vsense_addr) != 0 && + (scsiq->orig_sense_len - scsiq->sense_len) >= + ASC_MIN_SENSE_LEN) { /* * Command returned with a check condition and valid * sense data. @@ -981,20 +978,17 @@ AdvISR(sc) * command information for the device. */ else if (scsiq->done_status == QD_NO_ERROR && - scsiq->cdb[0] == INQUIRY && - scsiq->target_lun == 0) - { + scsiq->cdb[0] == INQUIRY && + scsiq->target_lun == 0) { AdvInquiryHandling(sc, scsiq); } - - /* Change the RISC Queue List state to free. */ ADW_WRITE_BYTE_LRAM(iot, ioh, - next_done_loc + RQL_STATE, ASC_MC_QS_FREE); + next_done_loc + RQL_STATE, ASC_MC_QS_FREE); /* Get the RISC Queue List forward pointer. */ ADW_READ_BYTE_LRAM(iot, ioh, - next_done_loc + RQL_FWD, completed_q); + next_done_loc + RQL_FWD, completed_q); /* * Notify the driver of the completed request by passing @@ -1002,7 +996,7 @@ AdvISR(sc) */ sc->cur_host_qng--; scsiq->a_flag |= ADW_SCSIQ_DONE; - (*(ADW_ISR_CALLBACK) sc->isr_callback)(sc, scsiq); + (*(ADW_ISR_CALLBACK) sc->isr_callback) (sc, scsiq); /* * Note: After the driver callback function is called, 'scsiq' * can no longer be referenced. @@ -1025,15 +1019,15 @@ AdvISR(sc) */ int AdvSendIdleCmd(sc, idle_cmd, idle_cmd_parameter, flags) - ADW_SOFTC *sc; - u_int16_t idle_cmd; - u_int32_t idle_cmd_parameter; - int flags; + ADW_SOFTC *sc; + u_int16_t idle_cmd; + u_int32_t idle_cmd_parameter; + int flags; { - bus_space_tag_t iot = sc->sc_iot; - bus_space_handle_t ioh = sc->sc_ioh; - u_int32_t i; - int ret; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; + u_int32_t i; + int ret; sc->idle_cmd_done = 0; @@ -1044,7 +1038,7 @@ AdvSendIdleCmd(sc, idle_cmd, idle_cmd_parameter, flags) * parameters have been written to LRAM. */ ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IDLE_PARA_STAT, - idle_cmd_parameter); + idle_cmd_parameter); ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD, idle_cmd); /* @@ -1054,8 +1048,7 @@ AdvSendIdleCmd(sc, idle_cmd, idle_cmd_parameter, flags) if (flags & ADW_NOWAIT) return ADW_TRUE; - for (i = 0; i < SCSI_WAIT_10_SEC * SCSI_MS_PER_SEC; i++) - { + for (i = 0; i < SCSI_WAIT_10_SEC * SCSI_MS_PER_SEC; i++) { /* * 'idle_cmd_done' is set by AdvISR(). */ @@ -1072,11 +1065,9 @@ AdvSendIdleCmd(sc, idle_cmd, idle_cmd_parameter, flags) (void) AdvISR(sc); } - if (sc->idle_cmd_done == ADW_FALSE) - { + if (sc->idle_cmd_done == ADW_FALSE) { return ADW_FALSE; - } else - { + } else { ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_IDLE_PARA_STAT, ret); return ret; } @@ -1100,23 +1091,21 @@ AdvSendIdleCmd(sc, idle_cmd, idle_cmd_parameter, flags) */ static int AdvSendScsiCmd(sc, scsiq) - ADW_SOFTC *sc; - ADW_SCSI_REQ_Q *scsiq; + ADW_SOFTC *sc; + ADW_SCSI_REQ_Q *scsiq; { - bus_space_tag_t iot = sc->sc_iot; - bus_space_handle_t ioh = sc->sc_ioh; - ADW_CCB *ccb = (ADW_CCB *)scsiq->ccb_ptr; - u_int16_t next_ready_loc; - u_int8_t next_ready_loc_fwd; - long req_size; - u_int32_t q_phy_addr; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; + ADW_CCB *ccb = (ADW_CCB *) scsiq->ccb_ptr; + u_int16_t next_ready_loc; + u_int8_t next_ready_loc_fwd; + long req_size; + u_int32_t q_phy_addr; - if (sc->cur_host_qng >= sc->max_host_qng) - { + if (sc->cur_host_qng >= sc->max_host_qng) { return ADW_BUSY; - } else - { + } else { sc->cur_host_qng++; } @@ -1156,12 +1145,15 @@ AdvSendScsiCmd(sc, scsiq) * to in microcode LRAM, has the format detailed in the comment * header for this function. * - * Write the ADW_SCSI_REQ_Q physical pointer to 'next_ready_loc' request. + * Write the ADW_SCSI_REQ_Q physical pointer to + * 'next_ready_loc' request. */ - ADW_WRITE_DWORD_LRAM(iot, ioh, next_ready_loc + RQL_PHYADDR, q_phy_addr); + ADW_WRITE_DWORD_LRAM(iot, ioh, next_ready_loc + RQL_PHYADDR, + q_phy_addr); /* Write target_id to 'next_ready_loc' request. */ - ADW_WRITE_BYTE_LRAM(iot, ioh, next_ready_loc + RQL_TID, scsiq->target_id); + ADW_WRITE_BYTE_LRAM(iot, ioh, next_ready_loc + RQL_TID, + scsiq->target_id); /* * Set the ASC_MC_HOST_NEXT_READY (0x128) microcode variable to @@ -1176,9 +1168,9 @@ AdvSendScsiCmd(sc, scsiq) * it were used as the 3rd argument to 'AdvWriteByteLram()'. */ ADW_READ_BYTE_LRAM(iot, ioh, next_ready_loc + RQL_FWD, - next_ready_loc_fwd); + next_ready_loc_fwd); ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_READY, - next_ready_loc_fwd); + next_ready_loc_fwd); /* * Change the state of 'next_ready_loc' request from QS_FREE to @@ -1189,7 +1181,7 @@ AdvSendScsiCmd(sc, scsiq) * state to QS_READY. The microcode now owns the request. */ ADW_WRITE_BYTE_LRAM(iot, ioh, next_ready_loc + RQL_STATE, - ASC_MC_QS_READY); + ASC_MC_QS_READY); return ADW_SUCCESS; } @@ -1198,20 +1190,20 @@ AdvSendScsiCmd(sc, scsiq) * Inquiry Information Byte 7 Handling * * Handle SCSI Inquiry Command information for a device by setting - * microcode operating variables that affect WDTR, SDTR, and Tag + * microcode operating variables that affect WDTR, SDTR, and Tag * Queuing. */ static void AdvInquiryHandling(sc, scsiq) - ADW_SOFTC *sc; - ADW_SCSI_REQ_Q *scsiq; + ADW_SOFTC *sc; + ADW_SCSI_REQ_Q *scsiq; { - bus_space_tag_t iot = sc->sc_iot; - bus_space_handle_t ioh = sc->sc_ioh; - ASC_SCSI_INQUIRY *inq; - u_int16_t cfg_word; - u_int16_t tidmask; - u_int8_t tid; + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; + ASC_SCSI_INQUIRY *inq; + u_int16_t cfg_word; + u_int16_t tidmask; + u_int8_t tid; /* * AdvInquiryHandling() requires up to INQUIRY information Byte 7 @@ -1222,23 +1214,18 @@ AdvInquiryHandling(sc, scsiq) * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the * microcode to the transfer residual count. */ - if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) - { + if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { return; } - tid = scsiq->target_id; inq = (ASC_SCSI_INQUIRY *) scsiq->vdata_addr; /* * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. */ - if (inq->byte3.rsp_data_fmt < 2 && inq->byte2.ansi_apr_ver < 2) - { + if (inq->byte3.rsp_data_fmt < 2 && inq->byte2.ansi_apr_ver < 2) { return; - } - else - { + } else { /* * INQUIRY Byte 7 Handling * @@ -1257,29 +1244,26 @@ AdvInquiryHandling(sc, scsiq) * device's 'wdtr_able' bit and write the new value to the * microcode. */ - if ((sc->wdtr_able & tidmask) && inq->byte7.WBus16) - { + if ((sc->wdtr_able & tidmask) && inq->byte7.WBus16) { ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, - cfg_word); - if ((cfg_word & tidmask) == 0) - { + cfg_word); + if ((cfg_word & tidmask) == 0) { cfg_word |= tidmask; ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, - cfg_word); + cfg_word); /* - * Clear the microcode "WDTR negotiation" done indicator - * for the target to cause it to negotiate with the new - * setting set above. + * Clear the microcode "WDTR negotiation" done + * indicator for the target to cause it + * to negotiate with the new setting set above. */ ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, - cfg_word); + cfg_word); cfg_word &= ~tidmask; ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, - cfg_word); + cfg_word); } } - /* * Synchronous Transfers * @@ -1287,29 +1271,26 @@ AdvInquiryHandling(sc, scsiq) * supports synchronous transfers, then turn on the device's * 'sdtr_able' bit. Write the new value to the microcode. */ - if ((sc->sdtr_able & tidmask) && inq->byte7.Sync) - { + if ((sc->sdtr_able & tidmask) && inq->byte7.Sync) { ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, - cfg_word); - if ((cfg_word & tidmask) == 0) - { + cfg_word); + if ((cfg_word & tidmask) == 0) { cfg_word |= tidmask; ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, - cfg_word); + cfg_word); /* - * Clear the microcode "SDTR negotiation" done indicator - * for the target to cause it to negotiate with the new - * setting set above. + * Clear the microcode "SDTR negotiation" done + * indicator for the target to cause it + * to negotiate with the new setting set above. */ ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, - cfg_word); + cfg_word); cfg_word &= ~tidmask; ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, - cfg_word); + cfg_word); } } - /* * If the EEPROM enabled Tag Queuing for device and the * device supports Tag Queuing, then turn on the device's @@ -1322,23 +1303,22 @@ AdvInquiryHandling(sc, scsiq) * disabling Tag Queuing in the BIOS devices with Tag Queuing * bugs will at least work with the BIOS. */ - if ((sc->tagqng_able & tidmask) && inq->byte7.CmdQue) - { + if ((sc->tagqng_able & tidmask) && inq->byte7.CmdQue) { ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, - cfg_word); + cfg_word); cfg_word |= tidmask; ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, - cfg_word); + cfg_word); ADW_WRITE_BYTE_LRAM(iot, ioh, - ASC_MC_NUMBER_OF_MAX_CMD + tid, - sc->max_dvc_qng); + ASC_MC_NUMBER_OF_MAX_CMD + tid, + sc->max_dvc_qng); } } } static void DvcSleepMilliSecond(n) - ulong n; + ulong n; { DELAY(n * 1000); @@ -1346,7 +1326,7 @@ DvcSleepMilliSecond(n) static void DvcDelayMicroSecond(n) - ulong n; + ulong n; { DELAY(n); diff --git a/sys/dev/pci/adw_pci.c b/sys/dev/pci/adw_pci.c index c8a7179cb36c..00a84452b14f 100644 --- a/sys/dev/pci/adw_pci.c +++ b/sys/dev/pci/adw_pci.c @@ -1,10 +1,10 @@ -/* $NetBSD: adw_pci.c,v 1.1 1998/09/26 16:09:32 dante Exp $ */ +/* $NetBSD: adw_pci.c,v 1.2 1998/09/26 19:53:34 dante Exp $ */ /* * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. - * + * * Author: Baldassare Dante Profeta - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -69,8 +69,8 @@ /******************************************************************************/ -int adw_pci_match __P((struct device *, struct cfdata *, void *)); -void adw_pci_attach __P((struct device *, struct device *, void *)); +int adw_pci_match __P((struct device *, struct cfdata *, void *)); +void adw_pci_attach __P((struct device *, struct device *, void *)); struct cfattach adw_pci_ca = { @@ -83,11 +83,11 @@ struct cfattach adw_pci_ca = * If we find one, note it's address (slot) and call * the actual probe routine to check it out. */ -int +int adw_pci_match(parent, match, aux) - struct device *parent; - struct cfdata *match; - void *aux; + struct device *parent; + struct cfdata *match; + void *aux; { struct pci_attach_args *pa = aux; @@ -101,10 +101,10 @@ adw_pci_match(parent, match, aux) } -void +void adw_pci_attach(parent, self, aux) - struct device *parent, *self; - void *aux; + struct device *parent, *self; + void *aux; { struct pci_attach_args *pa = aux; ADW_SOFTC *sc = (void *) self; @@ -142,7 +142,6 @@ adw_pci_attach(parent, self, aux) command | (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)); } - /* * Latency timer settings. */ @@ -152,27 +151,24 @@ adw_pci_attach(parent, self, aux) bhlcr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_WIDE) && - (PCI_LATTIMER(bhlcr) < 0x20)) { - bhlcr &= 0xFFFF00FFul; - bhlcr |= 0x00002000ul; + (PCI_LATTIMER(bhlcr) < 0x20)) { + bhlcr &= 0xFFFF00FFUL; + bhlcr |= 0x00002000UL; pci_conf_write(pa->pa_pc, pa->pa_tag, - PCI_BHLC_REG, bhlcr); + PCI_BHLC_REG, bhlcr); } } - if((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_WIDE) && - (command & PCI_COMMAND_PARITY_ENABLE) == 0) { + if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_WIDE) && + (command & PCI_COMMAND_PARITY_ENABLE) == 0) { sc->cfg.control_flag |= CONTROL_FLAG_IGNORE_PERR; } - - - /* * Map Device Registers for I/O */ if (pci_mapreg_map(pa, PCI_BASEADR_IO, PCI_MAPREG_TYPE_IO, 0, - &iot, &ioh, NULL, NULL)) { + &iot, &ioh, NULL, NULL)) { printf("%s: unable to map device registers\n", sc->sc_dev.dv_xname); return;