From b0cd3c8093cbeaaae3238b2d050a2582651ae03a Mon Sep 17 00:00:00 2001 From: tsutsui Date: Sun, 5 Oct 2003 15:38:08 +0000 Subject: [PATCH] Apply a bunch of patches written by Christopher SEKIYA (with several cosmetic changes by me) which fixes O2 (IP32) support. Now my R5000 O2 works fine in multiuser with on-board AIC7880 SCSIs and several PCI network cards (but only on serial console yet). L2 cache on R5000/Rm5200 is still disabled for now, but it will be fixed later, hopefully. See recent discussion on port-sgimips for details. --- sys/arch/sgimips/conf/GENERIC | 15 +- sys/arch/sgimips/conf/files.sgimips | 8 +- sys/arch/sgimips/dev/com_mace.c | 16 +- sys/arch/sgimips/dev/crime.c | 55 ++++-- sys/arch/sgimips/dev/crimereg.h | 104 +++++----- sys/arch/sgimips/dev/crimevar.h | 48 +++++ sys/arch/sgimips/dev/lpt_mace.c | 29 ++- sys/arch/sgimips/dev/mace.c | 255 +++++++++++++++++++------ sys/arch/sgimips/dev/macereg.h | 163 ++++++++-------- sys/arch/sgimips/dev/macevar.h | 13 +- sys/arch/sgimips/dev/mcclock_mace.c | 9 +- sys/arch/sgimips/dev/pckbc_mace.c | 73 +++++-- sys/arch/sgimips/include/bus.h | 24 +-- sys/arch/sgimips/include/pci_machdep.h | 5 +- sys/arch/sgimips/pci/macepci.c | 186 +++++++++++++----- sys/arch/sgimips/pci/pci_machdep.c | 13 +- sys/arch/sgimips/sgimips/autoconf.c | 22 +-- sys/arch/sgimips/sgimips/console.c | 16 +- sys/arch/sgimips/sgimips/cpu.c | 11 +- sys/arch/sgimips/sgimips/ip22.c | 58 +----- sys/arch/sgimips/sgimips/ip32.c | 88 ++++----- sys/arch/sgimips/sgimips/machdep.c | 123 +++++++----- 22 files changed, 821 insertions(+), 513 deletions(-) create mode 100644 sys/arch/sgimips/dev/crimevar.h diff --git a/sys/arch/sgimips/conf/GENERIC b/sys/arch/sgimips/conf/GENERIC index 3c72074ed4f2..c28280e9d64f 100644 --- a/sys/arch/sgimips/conf/GENERIC +++ b/sys/arch/sgimips/conf/GENERIC @@ -1,4 +1,4 @@ -# $NetBSD: GENERIC,v 1.23 2003/09/28 12:56:09 tsutsui Exp $ +# $NetBSD: GENERIC,v 1.24 2003/10/05 15:38:08 tsutsui Exp $ # # GENERIC machine description file # @@ -28,7 +28,7 @@ include "arch/sgimips/conf/std.sgimips" options INCLUDE_CONFIG_FILE # embed config file in kernel binary -#ident "GENERIC-$Revision: 1.23 $" +#ident "GENERIC-$Revision: 1.24 $" maxusers 32 @@ -38,7 +38,8 @@ options IP22 # Indy / Indigo2 options IP32 # O2 options MIPS3 # MIPS3 support -options MIPS3_L2CACHE_ABSENT +options MIPS3_L2CACHE_ABSENT # required if L2cache is disabled +#options ENABLE_MIPS4_CACHE_R10K # enable R10000 cache ops # Standard system options #options INSECURE # disable kernel security levels @@ -163,11 +164,11 @@ macepci0 at mace0 offset 0x080000 intr 7 pci0 at macepci0 bus 0 # MACE devices -mec0 at mace0 offset 0x280000 intr 3 +#mec0 at mace0 offset 0x280000 intr 3 pckbc0 at mace0 offset 0x320000 intr 5 -lpt0 at mace0 offset 0x380000 intr 4 -com0 at mace0 offset 0x390000 intr 4 -com1 at mace0 offset 0x398000 intr 4 +lpt0 at mace0 offset 0x380000 intr 4 intrmask 0x000f0000 +com0 at mace0 offset 0x390000 intr 4 intrmask 0x03f00000 +com1 at mace0 offset 0x398000 intr 4 intrmask 0xfc000000 mcclock0 at mace0 offset 0x3a0000 # PCI network devices diff --git a/sys/arch/sgimips/conf/files.sgimips b/sys/arch/sgimips/conf/files.sgimips index a47189b1b9e9..d07d2fa2d824 100644 --- a/sys/arch/sgimips/conf/files.sgimips +++ b/sys/arch/sgimips/conf/files.sgimips @@ -1,4 +1,4 @@ -# $NetBSD: files.sgimips,v 1.24 2003/09/15 06:39:20 simonb Exp $ +# $NetBSD: files.sgimips,v 1.25 2003/10/05 15:38:08 tsutsui Exp $ maxpartitions 16 @@ -24,14 +24,14 @@ device crime attach crime at mainbus file arch/sgimips/dev/crime.c crime -device mace {[offset = -1], [intr = -1]} +device mace {[offset = -1], [intr = -1], [intrmask = 0] } attach mace at mainbus file arch/sgimips/dev/mace.c mace attach com at mace with com_mace file arch/sgimips/dev/com_mace.c com_mace -device lpt # XXX +device lpt attach lpt at mace with lpt_mace file arch/sgimips/dev/lpt_mace.c lpt_mace file dev/ic/lpt.c lpt_mace @@ -39,7 +39,7 @@ file dev/ic/lpt.c lpt_mace attach pckbc at mace with pckbc_mace file arch/sgimips/dev/pckbc_mace.c pckbc_mace -device mcclock # XXX +device mcclock attach mcclock at mace with mcclock_mace file arch/sgimips/dev/mcclock_mace.c mcclock_mace diff --git a/sys/arch/sgimips/dev/com_mace.c b/sys/arch/sgimips/dev/com_mace.c index d3ea24f43912..b0b3cd121e14 100644 --- a/sys/arch/sgimips/dev/com_mace.c +++ b/sys/arch/sgimips/dev/com_mace.c @@ -1,4 +1,4 @@ -/* $NetBSD: com_mace.c,v 1.9 2003/07/15 03:35:51 lukem Exp $ */ +/* $NetBSD: com_mace.c,v 1.10 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -33,7 +33,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: com_mace.c,v 1.9 2003/07/15 03:35:51 lukem Exp $"); +__KERNEL_RCSID(0, "$NetBSD: com_mace.c,v 1.10 2003/10/05 15:38:08 tsutsui Exp $"); #include #include @@ -94,8 +94,13 @@ com_mace_attach(parent, self, aux) struct mace_attach_args *maa = aux; sc->sc_iot = maa->maa_st; - sc->sc_ioh = maa->maa_sh; - sc->sc_iobase = maa->maa_sh; + + /* + * XXX should check com_is_console() and + * XXX use bus_space_map(). + */ + sc->sc_ioh = maa->maa_sh + maa->maa_offset; + sc->sc_iobase = sc->sc_ioh; sc->sc_frequency = COM_FREQ; @@ -104,8 +109,7 @@ com_mace_attach(parent, self, aux) com_attach_subr(sc); delay(10000); - mace_intr_establish(4, IPL_TTY, comintr, sc); - /*mace_intr_establish(maa->maa_intr, IPL_TTY, comintr, sc);*/ + mace_intr_establish(maa->maa_intr, maa->maa_intrmask, comintr, sc); return; } diff --git a/sys/arch/sgimips/dev/crime.c b/sys/arch/sgimips/dev/crime.c index bc46ca58c80b..ca1a134e761f 100644 --- a/sys/arch/sgimips/dev/crime.c +++ b/sys/arch/sgimips/dev/crime.c @@ -1,4 +1,4 @@ -/* $NetBSD: crime.c,v 1.12 2003/07/15 03:35:51 lukem Exp $ */ +/* $NetBSD: crime.c,v 1.13 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -37,7 +37,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: crime.c,v 1.12 2003/07/15 03:35:51 lukem Exp $"); +__KERNEL_RCSID(0, "$NetBSD: crime.c,v 1.13 2003/10/05 15:38:08 tsutsui Exp $"); #include #include @@ -50,19 +50,17 @@ __KERNEL_RCSID(0, "$NetBSD: crime.c,v 1.12 2003/07/15 03:35:51 lukem Exp $"); #include #include -#include - -#include +#include #include #include "locators.h" static int crime_match(struct device *, struct cfdata *, void *); static void crime_attach(struct device *, struct device *, void *); -void * crime_intr_establish(int, int, int, int (*)(void *), void *); -void crime_intr(u_int); -CFATTACH_DECL(crime, sizeof(struct device), +struct crime_softc *crime_sc; /* only one per machine, okay to be global */ + +CFATTACH_DECL(crime, sizeof(struct crime_softc), crime_match, crime_attach, NULL, NULL); #define CRIME_NINTR 32 /* XXX */ @@ -94,10 +92,19 @@ crime_attach(parent, self, aux) struct device *self; void *aux; { + struct crime_softc *sc = (struct crime_softc *)self; struct mainbus_attach_args *ma = aux; u_int64_t crm_id; - crm_id = bus_space_read_8(ma->ma_iot, ma->ma_ioh, 0); + crime_sc = sc; + + sc->iot = SGIMIPS_BUS_SPACE_HPC; + + if (bus_space_map(sc->iot, ma->ma_addr, 0 /* XXX */, + BUS_SPACE_MAP_LINEAR, &sc->ioh)) + panic("crime_attach: can't map I/O space"); + + crm_id = bus_space_read_8(sc->iot, sc->ioh, CRIME_REV); aprint_naive(": system ASIC"); @@ -126,13 +133,18 @@ crime_attach(parent, self, aux) aprint_normal(" (CRIME_ID: %llx)\n", crm_id); - /* All interrupts off. Turned on as we register devices */ - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK) = 0; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTSTAT) = 0; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_SOFTINT) = 0; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_HARDINT) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_STATUS) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_MASK) = 0; + /* Turn on memory error and crime error interrupts. + All others turned on as devices are registered. */ + bus_space_write_8(sc->iot, sc->ioh, CRIME_INTMASK, + CRIME_INT_MEMERR | + CRIME_INT_CRMERR | + CRIME_INT_VICE | + CRIME_INT_VID_OUT | + CRIME_INT_VID_IN2 | + CRIME_INT_VID_IN1); + bus_space_write_8(sc->iot, sc->ioh, CRIME_INTSTAT, 0); + bus_space_write_8(sc->iot, sc->ioh, CRIME_SOFTINT, 0); + bus_space_write_8(sc->iot, sc->ioh, CRIME_HARDINT, 0); } /* @@ -153,6 +165,8 @@ crime_intr_establish(irq, type, level, func, arg) crime[irq].func = func; crime[irq].arg = arg; + crime_intr_mask(irq); + return (void *)&crime[irq]; } @@ -168,3 +182,12 @@ crime_intr(pendmask) } } +void +crime_intr_mask(unsigned int intr) +{ + u_int64_t mask; + + mask = bus_space_read_8(crime_sc->iot, crime_sc->ioh, CRIME_INTMASK); + mask |= (1 << intr); + bus_space_write_8(crime_sc->iot, crime_sc->ioh, CRIME_INTMASK, mask); +} diff --git a/sys/arch/sgimips/dev/crimereg.h b/sys/arch/sgimips/dev/crimereg.h index fc3a7df9a2ff..4532b3ae421b 100644 --- a/sys/arch/sgimips/dev/crimereg.h +++ b/sys/arch/sgimips/dev/crimereg.h @@ -1,4 +1,4 @@ -/* $NetBSD: crimereg.h,v 1.7 2003/10/04 09:19:23 tsutsui Exp $ */ +/* $NetBSD: crimereg.h,v 1.8 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -36,30 +36,30 @@ * O2 CRIME register definitions */ -#define CRIME_BASE 0x14000000 /* all registers 64-bit access */ +#define CRIME_BASE 0x14000000 /* all registers 64-bit access */ /* Offset 0x00 -- revision register */ -#define CRIME_REV (CRIME_BASE+0x000) -#define CRIME_ID_IDBITS 0xf0 -#define CRIME_ID_IDSHIFT 4 -#define CRIME_ID_REV 0x0f -#define CRIME_REV_PETTY 0x0 -#define CRIME_REV_11 0x11 -#define CRIME_REV_13 0x13 -#define CRIME_REV_14 0x14 +#define CRIME_REV 0x00 +#define CRIME_ID_IDBITS 0x000000f0 +#define CRIME_ID_IDSHIFT 4 +#define CRIME_ID_REV 0x0000000f +#define CRIME_REV_PETTY 0x00 +#define CRIME_REV_11 0x11 +#define CRIME_REV_13 0x13 +#define CRIME_REV_14 0x14 -/* offset 0x08 -- control register. Only lower 14 bits are valid*/ -#define CRIME_CONTROL (CRIME_BASE+0x008) -#define CRIME_CONTROL_TRITON_SYSADC 0x2000 -#define CRIME_CONTROL_CRIME_SYSADC 0x1000 -#define CRIME_CONTROL_HARD_RESET 0x0800 -#define CRIME_CONTROL_SOFT_RESET 0x0400 -#define CRIME_CONTROL_DOG_ENABLE 0x0200 -#define CRIME_CONTROL_ENDIANESS 0x0100 /* assert for BE */ -#define CRIME_CONTROL_CQUEUE_HWM 0x000f -#define CRIME_CONTROL_CQUEUE_SHFT 0 -#define CRIME_CONTROL_WBUF_HWM 0x00f0 -#define CRIME_CONTROL_WBUF_SHFT 8 +/* offset 0x08 -- control register. Only lower 14 bits are valid */ +#define CRIME_CONTROL 0x08 +#define CRIME_CONTROL_TRITON_SYSADC 0x2000 +#define CRIME_CONTROL_CRIME_SYSADC 0x1000 +#define CRIME_CONTROL_HARD_RESET 0x0800 +#define CRIME_CONTROL_SOFT_RESET 0x0400 +#define CRIME_CONTROL_DOG_ENABLE 0x0200 +#define CRIME_CONTROL_ENDIANESS 0x0100 /* assert for BE */ +#define CRIME_CONTROL_CQUEUE_HWM 0x000f +#define CRIME_CONTROL_CQUEUE_SHFT 0 +#define CRIME_CONTROL_WBUF_HWM 0x00f0 +#define CRIME_CONTROL_WBUF_SHFT 8 /* * macros to manipulate CRIME High Water Mark bits in @@ -83,7 +83,7 @@ /* Offset 0x010 -- interrupt status register. All 32 bits valid */ -#define CRIME_INTSTAT (CRIME_BASE+0x010) +#define CRIME_INTSTAT 0x10 #define CRIME_INT_VICE 0x80000000 #define CRIME_INT_SOFT2 0x40000000 /* Also CPU_SysCorErr */ #define CRIME_INT_SOFT1 0x20000000 @@ -117,40 +117,40 @@ #define CRIME_INT_VID_IN2 0x00000002 #define CRIME_INT_VID_IN1 0x00000001 -/* Masks, hard interrupts, soft interrupts. Don't know what to do with these */ -#define CRIME_INTMASK (CRIME_BASE+0x018) -#define CRIME_SOFTINT (CRIME_BASE+0x020) -#define CRIME_HARDINT (CRIME_BASE+0x028) +/* Masks, hard interrupts, soft interrupts. */ +#define CRIME_INTMASK 0x18 +#define CRIME_SOFTINT 0x20 +#define CRIME_HARDINT 0x28 /* - * Offset 0x030 -- watchdog register. 33 bits are valid - * Bit 32: power on reset - * Bit 31: warm reset + * Offset 0x030 -- watchdog register. 33 bits are valid + * Bit 32: power on reset + * Bit 31: warm reset * Write zero here to reset watchdog */ -#define CRIME_DOG (CRIME_BASE+0x030) +#define CRIME_DOG 0x30 #define CRIME_WATCHDOG CRIME_DOG -#define CRIME_TIME (CRIME_BASE+0x038) -#define CRIME_TIME_MASK 0x0000ffffffffffff -#define CRIME_CPU_ERROR_ADDR (CRIME_BASE+0x040) -#define CRIME_CPU_ERROR_STAT (CRIME_BASE+0x048) -#define CRIME_CPU_ERROR_ENA (CRIME_BASE+0x050) -#define CRIME_VICE_ERROR_ADDR (CRIME_BASE+0x058) -#define CRIME_MEM_CONTROL (CRIME_BASE+0x200) -#define CRIME_MEM_BANK_CTRL0 (CRIME_BASE+0x208) -#define CRIME_MEM_BANK_CTRL1 (CRIME_BASE+0x218) -#define CRIME_MEM_BANK_CTRL2 (CRIME_BASE+0x210) -#define CRIME_MEM_BANK_CTRL3 (CRIME_BASE+0x228) -#define CRIME_MEM_BANK_CTRL4 (CRIME_BASE+0x220) -#define CRIME_MEM_BANK_CTRL5 (CRIME_BASE+0x238) -#define CRIME_MEM_BANK_CTRL6 (CRIME_BASE+0x230) -#define CRIME_MEM_BANK_CTRL7 (CRIME_BASE+0x248) -#define CRIME_MEM_REFRESH_CNTR (CRIME_BASE+0x248) -#define CRIME_MEM_ERROR_STAT (CRIME_BASE+0x250) -#define CRIME_MEM_ERROR_ADDR (CRIME_BASE+0x258) -#define CRIME_MEM_ERROR_ECC_SYN (CRIME_BASE+0x260) -#define CRIME_MEM_ERROR_ECC_CHK (CRIME_BASE+0x268) -#define CRIME_MEM_ERROR_ECC_REPL (CRIME_BASE+0x270) +#define CRIME_TIME 0x38 +#define CRIME_TIME_MASK 0x0000ffffffffffffULL +#define CRIME_CPU_ERROR_ADDR 0x40 +#define CRIME_CPU_ERROR_STAT 0x48 +#define CRIME_CPU_ERROR_ENA 0x50 +#define CRIME_VICE_ERROR_ADDR 0x58 +#define CRIME_MEM_CONTROL 0x0200 +#define CRIME_MEM_BANK_CTRL0 0x0208 +#define CRIME_MEM_BANK_CTRL1 0x0218 +#define CRIME_MEM_BANK_CTRL2 0x0210 +#define CRIME_MEM_BANK_CTRL3 0x0228 +#define CRIME_MEM_BANK_CTRL4 0x0220 +#define CRIME_MEM_BANK_CTRL5 0x0238 +#define CRIME_MEM_BANK_CTRL6 0x0230 +#define CRIME_MEM_BANK_CTRL7 0x0248 +#define CRIME_MEM_REFRESH_CNTR 0x0248 +#define CRIME_MEM_ERROR_STAT 0x0250 +#define CRIME_MEM_ERROR_ADDR 0x0258 +#define CRIME_MEM_ERROR_ECC_SYN 0x0260 +#define CRIME_MEM_ERROR_ECC_CHK 0x0268 +#define CRIME_MEM_ERROR_ECC_REPL 0x0270 #define McGriff CRIME_DOG /* Baseball compatibility */ diff --git a/sys/arch/sgimips/dev/crimevar.h b/sys/arch/sgimips/dev/crimevar.h new file mode 100644 index 000000000000..4e6198d34cd0 --- /dev/null +++ b/sys/arch/sgimips/dev/crimevar.h @@ -0,0 +1,48 @@ +/* $NetBSD: crimevar.h,v 1.1 2003/10/05 15:38:08 tsutsui Exp $ */ + +/* + * Copyright (c) 2003 Christopher SEKIYA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the + * NetBSD Project. See http://www.netbsd.org/ for + * information about NetBSD. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +struct crime_softc { + struct device sc_dev; + + bus_space_tag_t iot; + bus_space_handle_t ioh; +}; + +extern struct crime_softc *crime_sc; + +void *crime_intr_establish(int, int, int, int (*)(void *), void *); +void crime_intr(u_int); +void crime_intr_mask(unsigned int); diff --git a/sys/arch/sgimips/dev/lpt_mace.c b/sys/arch/sgimips/dev/lpt_mace.c index 8a99dd37425d..149fba593c0d 100644 --- a/sys/arch/sgimips/dev/lpt_mace.c +++ b/sys/arch/sgimips/dev/lpt_mace.c @@ -1,6 +1,7 @@ -/* $NetBSD: lpt_mace.c,v 1.6 2003/07/15 03:35:52 lukem Exp $ */ +/* $NetBSD: lpt_mace.c,v 1.7 2003/10/05 15:38:08 tsutsui Exp $ */ /* + * Copyright (c) 2003 Christopher SEKIYA * Copyright (c) 2000 Soren S. Jorvang * All rights reserved. * @@ -33,7 +34,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: lpt_mace.c,v 1.6 2003/07/15 03:35:52 lukem Exp $"); +__KERNEL_RCSID(0, "$NetBSD: lpt_mace.c,v 1.7 2003/10/05 15:38:08 tsutsui Exp $"); #include #include @@ -53,6 +54,7 @@ __KERNEL_RCSID(0, "$NetBSD: lpt_mace.c,v 1.6 2003/07/15 03:35:52 lukem Exp $"); #include #include #include +#include #include @@ -77,7 +79,11 @@ lpt_mace_match(parent, match, aux) struct cfdata *match; void *aux; { - return 1; + + if (mach_type == MACH_SGI_IP32) + return (1); + + return (0); } static void @@ -86,13 +92,24 @@ lpt_mace_attach(parent, self, aux) struct device *self; void *aux; { -#if 0 struct lpt_mace_softc *msc = (void *)self; struct lpt_softc *sc = &msc->sc_lpt; struct mace_attach_args *maa = aux; -#endif - printf(": stub\n"); + sc->sc_iot = maa->maa_st; + + /* XXX should use bus_space_map() */ + if (bus_space_subregion(sc->sc_iot, maa->maa_sh, + maa->maa_offset, LPT_NPORTS, &sc->sc_ioh) != 0) { + printf(": can't map i/o space\n"); + return; + } + + printf("\n"); + + lpt_attach_subr(sc); + + mace_intr_establish(maa->maa_intr, maa->maa_intrmask, lptintr, sc); return; } diff --git a/sys/arch/sgimips/dev/mace.c b/sys/arch/sgimips/dev/mace.c index ec294da37a89..b4849e1dc78d 100644 --- a/sys/arch/sgimips/dev/mace.c +++ b/sys/arch/sgimips/dev/mace.c @@ -1,6 +1,8 @@ -/* $NetBSD: mace.c,v 1.12 2003/07/15 03:35:52 lukem Exp $ */ +/* $NetBSD: mace.c,v 1.13 2003/10/05 15:38:08 tsutsui Exp $ */ /* + * Copyright (c) 2003 Christopher Sekiya + * Copyright (c) 2002,2003 Rafal K. Boni * Copyright (c) 2000 Soren S. Jorvang * All rights reserved. * @@ -34,40 +36,80 @@ /* * O2 MACE + * + * The MACE is weird -- although it is a 32-bit device, writes only seem to + * work properly if they are 64-bit-at-once writes (at least, out in ISA + * space and probably MEC space -- the PCI stuff seems to be okay with _4). + * Therefore, the _8* routines are used even though the top 32 bits are + * thrown away. */ #include -__KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.12 2003/07/15 03:35:52 lukem Exp $"); +__KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.13 2003/10/05 15:38:08 tsutsui Exp $"); #include -#include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define _SGIMIPS_BUS_DMA_PRIVATE +#include #include #include #include -#include #include #include #include +#include #include #include "locators.h" +#define MACE_NINTR 32 /* actually only 8, but interrupts are shared */ + +struct { + unsigned int irq; + unsigned int intrmask; + int (*func)(void *); + void *arg; +} maceintrtab[MACE_NINTR]; + struct mace_softc { struct device sc_dev; + + bus_space_tag_t iot; + bus_space_handle_t ioh; + bus_dma_tag_t dmat; /* 32KB ring buffers, 4KB segments, for ISA */ + int nsegs; + bus_dma_segment_t seg; + bus_dmamap_t map; + + void *isa_ringbuffer; }; static int mace_match(struct device *, struct cfdata *, void *); static void mace_attach(struct device *, struct device *, void *); static int mace_print(void *, const char *); static int mace_search(struct device *, struct cfdata *, void *); -void mace_intr(int irqs); CFATTACH_DECL(mace, sizeof(struct mace_softc), mace_match, mace_attach, NULL, NULL); +#if defined(BLINK) +static struct callout mace_blink_ch = CALLOUT_INITIALIZER; +static void mace_blink(void *); +#endif + static int mace_match(parent, match, aux) struct device *parent; @@ -90,25 +132,90 @@ mace_attach(parent, self, aux) struct device *self; void *aux; { - u_int32_t id; + struct mace_softc *sc = (struct mace_softc *)self; + struct mainbus_attach_args *ma = aux; + u_int32_t scratch; - id = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_REV_INFO_R); - aprint_normal(": rev %x", id); - printf("\n"); + sc->iot = SGIMIPS_BUS_SPACE_MACE; + sc->dmat = &sgimips_default_bus_dma_tag; + + if (bus_space_map(sc->iot, ma->ma_addr, NULL, + BUS_SPACE_MAP_LINEAR, &sc->ioh)) + panic("mace_attach: could not allocate memory\n"); + +#if 0 + /* + * There's something deeply wrong with the alloc() routine -- it + * returns a pointer to memory that is used by the kernel i/o + * buffers. Disable for now. + */ + + if ((bus_dmamem_alloc(sc->dmat, 32768, PAGE_SIZE, 32768, + &sc->seg, 1, &sc->nsegs, BUS_DMA_NOWAIT)) != 0) { + printf(": unable to allocate DMA memory\n"); + return; + } + + if ((bus_dmamem_map(sc->dmat, &sc->seg, sc->nsegs, 32768, + (caddr_t *)&sc->isa_ringbuffer, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) + != 0) { + printf(": unable to map control data\n"); + return; + } + + if ((bus_dmamap_create(sc->dmat, 32768, 1, 32768, 0, + BUS_DMA_NOWAIT, &sc->map)) != 0) { + printf(": unable to create DMA map for control data\n"); + return; + } + + if ((scratch = bus_dmamap_load(sc->dmat, sc->map, sc->isa_ringbuffer, + 32768, NULL, BUS_DMA_NOWAIT)) != 0) { + printf(": unable to load DMA map for control data %i\n", + scratch); + } + + memset(sc->isa_ringbuffer, 0, 32768); + + bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_RINGBASE, + MIPS_KSEG1_TO_PHYS(sc->isa_ringbuffer) & 0xffff8000); + + aprint_normal(" isa ringbuffer 0x%x size 32k", + MIPS_KSEG1_TO_PHYS((unsigned long)sc->isa_ringbuffer)); +#endif + + aprint_normal("\n"); aprint_debug("%s: isa sts %llx\n", self->dv_xname, - *(volatile u_int64_t *)0xbf310010); + bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS)); aprint_debug("%s: isa msk %llx\n", self->dv_xname, - *(volatile u_int64_t *)0xbf310018); + bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK)); - /* - * Disable interrupts. These are enabled and unmasked during - * interrupt establishment + /* + * Turn on all ISA interrupts. These are actually masked and + * registered via the CRIME, as the MACE ISA interrupt mask is + * really whacky and nigh on impossible to map to a sane autoconfig + * scheme. */ - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_ADDR) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_FLAGS) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_CONTROL) = 0xff008500; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_MASK) = 0; + + bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK, 0xffffffff); + bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS, 0); + + /* set up LED for solid green or blink, if that's your fancy */ + scratch = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); + scratch |= MACE_ISA_LED_RED; + scratch &= ~(MACE_ISA_LED_GREEN); + bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, scratch); + +#if defined(BLINK) + mace_blink(sc); +#endif + + /* Initialize the maceintr elements to sane values */ + for (scratch = 0; scratch < MACE_NINTR; scratch++) { + maceintrtab[scratch].func = NULL; + maceintrtab[scratch].irq = 0; + } config_search(mace_search, self, NULL); } @@ -126,12 +233,10 @@ mace_print(aux, pnp) if (maa->maa_offset != MACECF_OFFSET_DEFAULT) aprint_normal(" offset 0x%lx", maa->maa_offset); -#if 0 if (maa->maa_intr != MACECF_INTR_DEFAULT) aprint_normal(" intr %d", maa->maa_intr); - if (maa->maa_offset != MACECF_STRIDE_DEFAULT) - aprint_normal(" stride 0x%lx", maa->maa_stride); -#endif + if (maa->maa_offset != MACECF_INTRMASK_DEFAULT) + aprint_normal(" intrmask 0x%x", maa->maa_intrmask); return UNCONF; } @@ -142,18 +247,18 @@ mace_search(parent, cf, aux) struct cfdata *cf; void *aux; { + struct mace_softc *sc = (struct mace_softc *)parent; struct mace_attach_args maa; int tryagain; do { maa.maa_offset = cf->cf_loc[MACECF_OFFSET]; -#if 0 maa.maa_intr = cf->cf_loc[MACECF_INTR]; - maa.maa_stride = cf->cf_loc[MACECF_STRIDE]; -#endif - maa.maa_st = 3; - /* XXX */ - maa.maa_sh = MIPS_PHYS_TO_KSEG1(maa.maa_offset + 0x1f000000); + maa.maa_intrmask = cf->cf_loc[MACECF_INTRMASK]; + maa.maa_st = SGIMIPS_BUS_SPACE_MACE; + maa.maa_sh = sc->ioh; /* XXX */ + maa.maa_dmat = &sgimips_default_bus_dma_tag; + maa.isa_ringbuffer = sc->isa_ringbuffer; tryagain = 0; if (config_match(parent, cf, &maa) > 0) { @@ -166,13 +271,6 @@ mace_search(parent, cf, aux) return 0; } -#define MACE_NINTR 8 /* XXX */ - -struct { - int (*func)(void *); - void *arg; -} maceintrtab[MACE_NINTR]; - void * mace_intr_establish(intr, level, func, arg) int intr; @@ -180,38 +278,81 @@ mace_intr_establish(intr, level, func, arg) int (*func)(void *); void *arg; { - u_int64_t mask; + int i; - if (intr < 0 || intr >= 8) - panic("invalid interrupt number"); + if (intr < 0 || intr >= 8) + panic("invalid interrupt number"); - if (maceintrtab[intr].func != NULL) - return NULL; /* panic("Cannot share MACE interrupts!"); */ + for (i = 0; i < MACE_NINTR; i++) + if (maceintrtab[intr].func == NULL) { + maceintrtab[intr].func = func; + maceintrtab[intr].arg = arg; + maceintrtab[intr].irq = (1 << intr); + maceintrtab[intr].intrmask = level; + break; + } - maceintrtab[intr].func = func; - maceintrtab[intr].arg = arg; - mask = *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK); - mask |= (1 << intr); - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK) = mask; - aprint_debug("mace: established interrupt %d (level %i)\n", intr, level); - aprint_debug("mace: CRM_MASK now %llx\n", *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK)); + crime_intr_mask(intr); + aprint_normal("mace: established interrupt %d (level %x)\n", + intr, level); return (void *)&maceintrtab[intr]; } -void +void mace_intr(int irqs) { + u_int64_t isa_irq, isa_mask; int i; - - /* printf("mace_intr: irqs %x\n", irqs); */ - - for (i = 0; i < MACE_NINTR; i++) { - if (irqs & (1 << i)) { - if (maceintrtab[i].func != NULL) + + /* irq 4 is the ISA cascade interrupt. Must handle with care. */ + if (irqs & (1 << 4)) { + isa_mask = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE + + MACE_ISA_INT_MASK)); + isa_irq = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE + + MACE_ISA_INT_STATUS)); + for (i = 0; i < MACE_NINTR; i++) { + if ((maceintrtab[i].irq == (1 << 4)) && + (isa_irq & maceintrtab[i].intrmask)) { + if (isa_irq & 0xfc000000) + printf("dispatching\n"); + (maceintrtab[i].func)(maceintrtab[i].arg); - else - printf("Unexpected mace interrupt %d\n", i); - } + } + } +#if 0 + mips3_sd((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE + + MACE_ISA_INT_STATUS), isa_mask); +#endif + irqs &= ~(1 << 4); } + + for (i = 0; i < MACE_NINTR; i++) + if ((irqs & maceintrtab[i].irq)) + (maceintrtab[i].func)(maceintrtab[i].arg); } +#if defined(BLINK) +static void +mace_blink(void *self) +{ + struct mace_softc *sc = (struct mace_softc *) self; + register int s; + int value; + + s = splhigh(); + value = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); + value ^= MACE_ISA_LED_GREEN; + bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, value); + splx(s); + /* + * Blink rate is: + * full cycle every second if completely idle (loadav = 0) + * full cycle every 2 seconds if loadav = 1 + * full cycle every 3 seconds if loadav = 2 + * etc. + */ + s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); + callout_reset(&mace_blink_ch, s, mace_blink, sc); + +} +#endif diff --git a/sys/arch/sgimips/dev/macereg.h b/sys/arch/sgimips/dev/macereg.h index e4549054bfc0..3debfff6a605 100644 --- a/sys/arch/sgimips/dev/macereg.h +++ b/sys/arch/sgimips/dev/macereg.h @@ -1,4 +1,4 @@ -/* $NetBSD: macereg.h,v 1.4 2003/10/04 09:19:23 tsutsui Exp $ */ +/* $NetBSD: macereg.h,v 1.5 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -32,95 +32,90 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#define MACE_BASE 0x1f000000 +#define MACE_BASE 0x1f000000 -#define MACE_PCI (MACE_BASE + 0x080000) -#define MACE_PCI_ERROR_ADDR (MACE_PCI+0x0) -#define MACE_PCI_ERROR_FLAGS (MACE_PCI+0x4) +/* PCI definitions (offset 0x080000) */ -#define MACE_PCI_CONTROL (MACE_PCI+0x8) -#define MACE_PCI_CONTROL_INT(x) BIT(x) -#define MACE_PCI_CONTROL_INT_MASK 0xff -#define MACE_PCI_CONTROL_SERR_ENA 0x0100 -#define MACE_PCI_CONTROL_ARB_N6 0x0200 -#define MACE_PCI_CONTROL_PARITY_ERR 0x0400 -#define MACE_PCI_CONTROL_MRMRA_ENA 0x0800 -#define MACE_PCI_CONTROL_ARB_N3 0x1000 -#define MACE_PCI_CONTROL_ARB_N4 0x2000 -#define MACE_PCI_CONTROL_ARB_N5 0x4000 -#define MACE_PCI_CONTROL_PARK_LIU 0x8000 +#define MACE_PCI_ERROR_ADDR 0x00 +#define MACE_PCI_ERROR_FLAGS 0x04 -/* #define MACE_PCI_CONTROL_INV_INT(x) BIT(16+x) -#define MACE_PCI_CONTROL_INV_INT_MASK 0x00ff0000 -#define MACE_PCI_CONTROL_OVERRUN_INT BIT(24) -#define MACE_PCI_CONTROL_PARITY_INT BIT(25) -#define MACE_PCI_CONTROL_SERR_INT BIT(26) -#define MACE_PCI_CONTROL_IT_INT BIT(27) -#define MACE_PCI_CONTROL_RE_INT BIT(28) -#define MACE_PCI_CONTROL_DPED_INT BIT(29) -#define MACE_PCI_CONTROL_TAR_INT BIT(30) -#define MACE_PCI_CONTROL_MAR_INT BIT(31) -*/ +#define MACE_PCI_CONTROL 0x08 +#define MACE_PCI_CONTROL_INT_MASK 0x000000ff +#define MACE_PCI_CONTROL_SERR_ENA 0x00000100 +#define MACE_PCI_CONTROL_ARB_N6 0x00000200 +#define MACE_PCI_CONTROL_PARITY_ERR 0x00000400 +#define MACE_PCI_CONTROL_MRMRA_ENA 0x00000800 +#define MACE_PCI_CONTROL_ARB_N3 0x00001000 +#define MACE_PCI_CONTROL_ARB_N4 0x00002000 +#define MACE_PCI_CONTROL_ARB_N5 0x00004000 +#define MACE_PCI_CONTROL_PARK_LIU 0x00008000 + +#define MACE_PCI_CONTROL_INV_INT_MASK 0x00ff0000 +#define MACE_PCI_CONTROL_OVERRUN_INT 0x01000000 +#define MACE_PCI_CONTROL_PARITY_INT 0x02000000 +#define MACE_PCI_CONTROL_SERR_INT 0x04000000 +#define MACE_PCI_CONTROL_IT_INT 0x08000000 +#define MACE_PCI_CONTROL_RE_INT 0x10000000 +#define MACE_PCI_CONTROL_DPED_INT 0x20000000 +#define MACE_PCI_CONTROL_TAR_INT 0x40000000 +#define MACE_PCI_CONTROL_MAR_INT 0x80000000 -#define MACE_PCI_REV_INFO_R (MACE_PCI+0xC) -#define MACE_PCI_FLUSH_W (MACE_PCI+0xC) -#define MACE_PCI_CONFIG_ADDR (MACE_PCI+0xCF4) -#define MACE_PCI_CONFIG_DATA (MACE_PCI+0xCF8) -#define MACE_PCI_LOW_MEMORY 0x1A000000 +#define MACE_PCI_REV_INFO_R 0x0c +#define MACE_PCI_FLUSH_W 0x0c +#define MACE_PCI_CONFIG_ADDR 0xcf8 +#define MACE_PCI_CONFIG_DATA 0xcfc +#define MACE_PCI_LOW_MEMORY 0x1a000000 #define MACE_PCI_LOW_IO 0x18000000 #define MACE_PCI_NATIVE_VIEW 0x40000000 #define MACE_PCI_IO 0x80000000 #define MACE_PCI_HI_MEMORY 0x280000000 #define MACE_PCI_HI_IO 0x100000000 +#define MACE_VIN1 0x100000 +#define MACE_VIN2 0x180000 +#define MACE_VOUT 0x200000 +#define MACE_PERIF 0x300000 +#define MACE_ISA_EXT 0x380000 - -#define MACE_VIN1 (MACE_BASE + 0x100000) -#define MACE_VIN2 (MACE_BASE + 0x180000) -#define MACE_VOUT (MACE_BASE + 0x200000) -#define MACE_ENET (MACE_BASE + 0x280000) -#define MACE_PERIF (MACE_BASE + 0x300000) -#define MACE_ISA_EXT (MACE_BASE + 0x380000) - -#define MACE_AUDIO (MACE_PERIF + 0x00000) -#define MACE_ISA (MACE_PERIF + 0x10000) -#define MACE_KBDMS (MACE_PERIF + 0x20000) -#define MACE_I2C (MACE_PERIF + 0x30000) -#define MACE_UST_MSC (MACE_PERIF + 0X40000) +#define MACE_AUDIO (MACE_PERIF + 0x00000) +#define MACE_ISA (MACE_PERIF + 0x10000) +#define MACE_KBDMS (MACE_PERIF + 0x20000) +#define MACE_I2C (MACE_PERIF + 0x30000) +#define MACE_UST_MSC (MACE_PERIF + 0x40000) /*********************** * PCI_ERROR_FLAGS Bits */ -#define MACE_PERR_MASTER_ABORT 0x80000000 -#define MACE_PERR_TARGET_ABORT 0x40000000 -#define MACE_PERR_DATA_PARITY_ERR 0x20000000 -#define MACE_PERR_RETRY_ERR 0x10000000 -#define MACE_PERR_ILLEGAL_CMD 0x08000000 -#define MACE_PERR_SYSTEM_ERR 0x04000000 -#define MACE_PERR_INTERRUPT_TEST 0x02000000 -#define MACE_PERR_PARITY_ERR 0x01000000 -#define MACE_PERR_OVERRUN 0x00800000 -#define MACE_PERR_RSVD 0x00400000 -#define MACE_PERR_MEMORY_ADDR 0x00200000 -#define MACE_PERR_CONFIG_ADDR 0x00100000 -#define MACE_PERR_MASTER_ABORT_ADDR_VALID 0x00080000 -#define MACE_PERR_TARGET_ABORT_ADDR_VALID 0x00040000 -#define MACE_PERR_DATA_PARITY_ADDR_VALID 0x00020000 -#define MACE_PERR_RETRY_ADDR_VALID 0x00010000 +#define MACE_PERR_MASTER_ABORT 0x80000000 +#define MACE_PERR_TARGET_ABORT 0x40000000 +#define MACE_PERR_DATA_PARITY_ERR 0x20000000 +#define MACE_PERR_RETRY_ERR 0x10000000 +#define MACE_PERR_ILLEGAL_CMD 0x08000000 +#define MACE_PERR_SYSTEM_ERR 0x04000000 +#define MACE_PERR_INTERRUPT_TEST 0x02000000 +#define MACE_PERR_PARITY_ERR 0x01000000 +#define MACE_PERR_OVERRUN 0x00800000 +#define MACE_PERR_RSVD 0x00400000 +#define MACE_PERR_MEMORY_ADDR 0x00200000 +#define MACE_PERR_CONFIG_ADDR 0x00100000 +#define MACE_PERR_MASTER_ABORT_ADDR_VALID 0x00080000 +#define MACE_PERR_TARGET_ABORT_ADDR_VALID 0x00040000 +#define MACE_PERR_DATA_PARITY_ADDR_VALID 0x00020000 +#define MACE_PERR_RETRY_ADDR_VALID 0x00010000 /******************************* * MACE ISA External Address Map */ -#define MACE_ISA_EPP_BASE (MACE_ISA_EXT+0x00000) -#define MACE_ISA_ECP_BASE (MACE_ISA_EXT+0x08000) -#define MACE_ISA_SER1_BASE (MACE_ISA_EXT+0x10000) -#define MACE_ISA_SER2_BASE (MACE_ISA_EXT+0x18000) -#define MACE_ISA_RTC_BASE (MACE_ISA_EXT+0x20000) -#define MACE_ISA_GAME_BASE (MACE_ISA_EXT_0x30000) +#define MACE_ISA_EPP_BASE (MACE_ISA_EXT + 0x00000) +#define MACE_ISA_ECP_BASE (MACE_ISA_EXT + 0x08000) +#define MACE_ISA_SER1_BASE (MACE_ISA_EXT + 0x10000) +#define MACE_ISA_SER2_BASE (MACE_ISA_EXT + 0x18000) +#define MACE_ISA_RTC_BASE (MACE_ISA_EXT + 0x20000) +#define MACE_ISA_GAME_BASE (MACE_ISA_EXT + 0x30000) /************************* @@ -129,26 +124,26 @@ /* ISA Ringbase Address and Reset Register */ -#define MACE_ISA_RINGBASE (MACE_ISA+0x0000) +#define MACE_ISA_RINGBASE (MACE_ISA + 0x0000) /* Flash-ROM/LED/DP-RAM/NIC Controller Register */ -#define MACE_ISA_FLASH_NIC_REG (MACE_ISA+0x0008) -#define MACE_ISA_FLASH_WE (0x01) /* 1=> Enable FLASH writes */ -#define MACE_ISA_PWD_CLEAR (0x02) /* 1=> PWD CLEAR jumper detected */ -#define MACE_ISA_NIC_DEASSERT (0x04) -#define MACE_ISA_NIC_DATA (0x08) -#define MACE_ISA_LED_RED (0x10) /* 1=> Illuminate RED LED */ -#define MACE_ISA_LED_GREEN (0x20) /* 1=> Illuminate GREEN LED */ -#define MACE_ISA_DP_RAM_ENABLE (0x40) +#define MACE_ISA_FLASH_NIC_REG (MACE_ISA + 0x0008) +#define MACE_ISA_FLASH_WE 0x01 /* 1=> Enable FLASH writes */ +#define MACE_ISA_PWD_CLEAR 0x02 /* 1=> PWD CLEAR jumper detected */ +#define MACE_ISA_NIC_DEASSERT 0x04 +#define MACE_ISA_NIC_DATA 0x08 +#define MACE_ISA_LED_RED 0x10 /* 1=> Illuminate RED LED */ +#define MACE_ISA_LED_GREEN 0x20 /* 1=> Illuminate GREEN LED */ +#define MACE_ISA_DP_RAM_ENABLE 0x40 /* Interrupt Status and Mask Registers (32 bits) */ -#define MACE_ISA_INT_STATUS (MACE_ISA+0x0010) -#define MACE_ISA_INT_MASK (MACE_ISA+0x0018) +#define MACE_ISA_INT_STATUS (MACE_ISA + 0x0010) +#define MACE_ISA_INT_MASK (MACE_ISA + 0x0018) /* bit definitions */ -#define MACE_ISA_INT_RTC_IRQ (0x00000100) +#define MACE_ISA_INT_RTC_IRQ 0x00000100 /******************************** @@ -156,11 +151,11 @@ * * Note: MSC_UST<31:0> is MSC, MSC_UST<63:32> is UST. */ -#define MACE_UST (MACE_UST_MSC + 0x00) /* Universial system time */ -#define MACE_COMPARE1 (MACE_UST_MSC + 0x08) /* Interrupt compare reg 1 */ -#define MACE_COMPARE2 (MACE_UST_MSC + 0x10) /* Interrupt compare reg 2 */ -#define MACE_COMPARE3 (MACE_UST_MSC + 0x18) /* Interrupt compare reg 3 */ -#define MACE_UST_PERIOD 960 /* UST Period in ns */ +#define MACE_UST (MACE_UST_MSC + 0x00) /* Universial system time */ +#define MACE_COMPARE1 (MACE_UST_MSC + 0x08) /* Interrupt compare reg 1 */ +#define MACE_COMPARE2 (MACE_UST_MSC + 0x10) /* Interrupt compare reg 2 */ +#define MACE_COMPARE3 (MACE_UST_MSC + 0x18) /* Interrupt compare reg 3 */ +#define MACE_UST_PERIOD 960 /* UST Period in ns */ #define MACE_AIN_MSC_UST (MACE_UST_MSC + 0x20) /* Audio in MSC/UST pair */ #define MACE_AOUT1_MSC_UST (MACE_UST_MSC + 0x28) /* Audio out 1 MSC/UST pair */ diff --git a/sys/arch/sgimips/dev/macevar.h b/sys/arch/sgimips/dev/macevar.h index f6a369395e33..4b681a75f511 100644 --- a/sys/arch/sgimips/dev/macevar.h +++ b/sys/arch/sgimips/dev/macevar.h @@ -1,4 +1,4 @@ -/* $NetBSD: macevar.h,v 1.3 2003/01/03 09:09:21 rafal Exp $ */ +/* $NetBSD: macevar.h,v 1.4 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -35,14 +35,13 @@ struct mace_attach_args { bus_space_tag_t maa_st; bus_space_handle_t maa_sh; + bus_dma_tag_t maa_dmat; + void *isa_ringbuffer; -/* ? */ long maa_offset; int maa_intr; -#if 0 - int maa_stride; -#endif + int maa_intrmask; }; -extern void * mace_intr_establish(int, int, int (*)(void *), void *); -extern void mace_intr(int); +void * mace_intr_establish(int, int, int (*)(void *), void *); +void mace_intr(int); diff --git a/sys/arch/sgimips/dev/mcclock_mace.c b/sys/arch/sgimips/dev/mcclock_mace.c index d5746ec738d9..ac967404cfde 100644 --- a/sys/arch/sgimips/dev/mcclock_mace.c +++ b/sys/arch/sgimips/dev/mcclock_mace.c @@ -1,4 +1,4 @@ -/* $NetBSD: mcclock_mace.c,v 1.10 2003/10/04 09:19:23 tsutsui Exp $ */ +/* $NetBSD: mcclock_mace.c,v 1.11 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2001 Antti Kantee. All Rights Reserved. @@ -69,7 +69,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: mcclock_mace.c,v 1.10 2003/10/04 09:19:23 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: mcclock_mace.c,v 1.11 2003/10/05 15:38:08 tsutsui Exp $"); #include #include @@ -124,7 +124,10 @@ mcclock_mace_attach(struct device *parent, struct device *self, void *aux) struct mace_attach_args *maa = aux; sc->sc_st = maa->maa_st; - sc->sc_sh = maa->maa_sh; + /* XXX should be bus_space_map() */ + if (bus_space_subregion(maa->maa_st, maa->maa_sh, + maa->maa_offset, NULL, &sc->sc_sh)) + panic("mcclock_mace_attach: couldn't map"); /* * We want a fixed format: 24-hour, BCD data, so just force the diff --git a/sys/arch/sgimips/dev/pckbc_mace.c b/sys/arch/sgimips/dev/pckbc_mace.c index 726e239f830d..1c577d530752 100644 --- a/sys/arch/sgimips/dev/pckbc_mace.c +++ b/sys/arch/sgimips/dev/pckbc_mace.c @@ -1,6 +1,7 @@ -/* $NetBSD: pckbc_mace.c,v 1.6 2003/07/15 03:35:52 lukem Exp $ */ +/* $NetBSD: pckbc_mace.c,v 1.7 2003/10/05 15:38:08 tsutsui Exp $ */ /* + * Copyright (c) 2003 Christopher SEKIYA * Copyright (c) 2000 Soren S. Jorvang * All rights reserved. * @@ -33,26 +34,21 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: pckbc_mace.c,v 1.6 2003/07/15 03:35:52 lukem Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pckbc_mace.c,v 1.7 2003/10/05 15:38:08 tsutsui Exp $"); #include #include -#include -#include -#include -#include -#include -#include -#include #include -#include -#include +#include #include +#include +#include +#include +#include -#include -#include #include #include +#include #include @@ -62,11 +58,12 @@ __KERNEL_RCSID(0, "$NetBSD: pckbc_mace.c,v 1.6 2003/07/15 03:35:52 lukem Exp $") struct pckbc_mace_softc { struct pckbc_softc sc_pckbc; - /* XXX intr cookie */ + int sc_irq[PCKBC_NSLOTS]; }; static int pckbc_mace_match(struct device *, struct cfdata *, void *); static void pckbc_mace_attach(struct device *, struct device *, void *); +void pckbc_mace_intr_establish(struct pckbc_softc *, pckbc_slot_t); CFATTACH_DECL(pckbc_mace, sizeof(struct pckbc_mace_softc), pckbc_mace_match, pckbc_mace_attach, NULL, NULL); @@ -77,7 +74,11 @@ pckbc_mace_match(parent, match, aux) struct cfdata *match; void *aux; { - return 1; + + if (mach_type == MACH_SGI_IP32) + return (1); + + return (0); } static void @@ -86,15 +87,39 @@ pckbc_mace_attach(parent, self, aux) struct device *self; void *aux; { -#if 0 struct pckbc_mace_softc *msc = (void *)self; struct pckbc_softc *sc = &msc->sc_pckbc; struct mace_attach_args *maa = aux; -#endif + struct pckbc_internal *t; + bus_space_handle_t ioh_d, ioh_c; - printf(": stub\n"); + msc->sc_irq[PCKBC_KBD_SLOT] = + msc->sc_irq[PCKBC_AUX_SLOT] = maa->maa_intr; - return; + sc->intr_establish = pckbc_mace_intr_establish; + + /* XXX should be bus_space_map() */ + if (bus_space_subregion(maa->maa_st, maa->maa_sh, + maa->maa_offset, 1, &ioh_d) || + bus_space_subregion(maa->maa_st, maa->maa_sh, + maa->maa_offset + 0x20, 1, &ioh_c)) + panic("pckbc_attach: couldn't map"); + + t = malloc(sizeof(struct pckbc_internal), M_DEVBUF, M_WAITOK|M_ZERO); + t->t_iot = maa->maa_st; + t->t_ioh_d = ioh_d; + t->t_ioh_c = ioh_c; + t->t_addr = maa->maa_sh; + t->t_cmdbyte = KC8_CPU; /* Enable ports */ + callout_init(&t->t_cleanup); + + t->t_sc = sc; + sc->id = t; + + printf("\n"); + + /* Finish off the attach. */ + pckbc_attach(sc); } /* XXX */ @@ -108,5 +133,15 @@ pckbc_machdep_cnattach(kbctag, kbcslot) pckbc_tag_t kbctag; pckbc_slot_t kbcslot; { + return (ENXIO); } + +void +pckbc_mace_intr_establish(sc, slot) + struct pckbc_softc *sc; + pckbc_slot_t slot; +{ + + mace_intr_establish(5, 0, pckbcintr, sc); +} diff --git a/sys/arch/sgimips/include/bus.h b/sys/arch/sgimips/include/bus.h index 5be9b3f43fdf..337f9d0d2000 100644 --- a/sys/arch/sgimips/include/bus.h +++ b/sys/arch/sgimips/include/bus.h @@ -1,4 +1,4 @@ -/* $NetBSD: bus.h,v 1.8 2003/06/15 23:09:05 fvdl Exp $ */ +/* $NetBSD: bus.h,v 1.9 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. @@ -60,6 +60,15 @@ typedef u_long bus_size_t; typedef int bus_space_tag_t; typedef u_long bus_space_handle_t; +/* + * Values for sgimips bus space tag, not to be used directly by MI code. + */ +#define SGIMIPS_BUS_SPACE_NORMAL 0 +#define SGIMIPS_BUS_SPACE_HPC 1 +#define SGIMIPS_BUS_SPACE_MEM 2 +#define SGIMIPS_BUS_SPACE_MACE 3 +#define SGIMIPS_BUS_SPACE_IO 4 + /* * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, * bus_size_t size, int flags, bus_space_handle_t *bshp); @@ -138,10 +147,7 @@ u_int16_t bus_space_read_2(bus_space_tag_t, bus_space_handle_t, bus_size_t); (wbflush(), /* XXX */ \ (void) t, (*(volatile u_int32_t *)((h) + (o)))) -/* XXX Make sure to use 64-bit loads. */ -#define bus_space_read_8(t, h, o) \ -(wbflush(), /* XXX */ \ - (void) t, (*(volatile u_int64_t *)((h) + (o)))) +#define bus_space_read_8(t, h, o) mips3_ld((u_int64_t *)((h) + (o))) /* * void bus_space_read_multi_N(bus_space_tag_t tag, @@ -241,13 +247,7 @@ do { \ wbflush(); /* XXX */ \ } while (0) -/* XXX Make sure to use 64-bit stores. */ -#define bus_space_write_8(t, h, o, v) \ -do { \ - (void) t; \ - *(volatile u_int64_t *)((h) + (o)) = (v); \ - wbflush(); /* XXX */ \ -} while (0) +#define bus_space_write_8(t, h, o, v) (mips3_sd((u_int64_t *)((h) + (o)), (v))) /* * void bus_space_write_multi_N(bus_space_tag_t tag, diff --git a/sys/arch/sgimips/include/pci_machdep.h b/sys/arch/sgimips/include/pci_machdep.h index 15ad9d611d9c..4b8fc3575f1a 100644 --- a/sys/arch/sgimips/include/pci_machdep.h +++ b/sys/arch/sgimips/include/pci_machdep.h @@ -1,4 +1,4 @@ -/* $NetBSD: pci_machdep.h,v 1.3 2002/05/15 19:23:56 thorpej Exp $ */ +/* $NetBSD: pci_machdep.h,v 1.4 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. @@ -55,7 +55,8 @@ struct sgimips_pci_chipset { pcireg_t (*pc_conf_read)(pci_chipset_tag_t, pcitag_t, int); void (*pc_conf_write)(pci_chipset_tag_t, pcitag_t, int, pcireg_t); -/* XXX */ + bus_space_tag_t iot; + bus_space_handle_t ioh; }; extern struct sgimips_bus_dma_tag pci_bus_dma_tag; diff --git a/sys/arch/sgimips/pci/macepci.c b/sys/arch/sgimips/pci/macepci.c index 83bc36857cfb..0633b4cc6355 100644 --- a/sys/arch/sgimips/pci/macepci.c +++ b/sys/arch/sgimips/pci/macepci.c @@ -1,7 +1,7 @@ -/* $NetBSD: macepci.c,v 1.13 2003/10/04 09:19:23 tsutsui Exp $ */ +/* $NetBSD: macepci.c,v 1.14 2003/10/05 15:38:08 tsutsui Exp $ */ /* - * Copyright (c) 2001 Christopher Sekiya + * Copyright (c) 2001,2003 Christopher Sekiya * Copyright (c) 2000 Soren S. Jorvang * All rights reserved. * @@ -34,7 +34,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: macepci.c,v 1.13 2003/10/04 09:19:23 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: macepci.c,v 1.14 2003/10/05 15:38:08 tsutsui Exp $"); #include #include @@ -45,6 +45,7 @@ __KERNEL_RCSID(0, "$NetBSD: macepci.c,v 1.13 2003/10/04 09:19:23 tsutsui Exp $") #include #include #include +#include #include #include @@ -92,7 +93,7 @@ bus_addr_t pciaddr_ioaddr(u_int32_t val); int pciaddr_do_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size); -unsigned int ioaddr_base = 0x3000; +unsigned int ioaddr_base = 0x1000; unsigned int memaddr_base = 0x80100000; CFATTACH_DECL(macepci, sizeof(struct macepci_softc), @@ -104,7 +105,11 @@ macepci_match(parent, match, aux) struct cfdata *match; void *aux; { - return 1; + + if (mach_type == MACH_SGI_IP32) + return (1); + + return (0); } static void @@ -121,25 +126,42 @@ macepci_attach(parent, self, aux) pcitag_t devtag; int device, rev; - rev = bus_space_read_4(maa->maa_st, maa->maa_sh, MACEPCI_REVISION); + if (bus_space_subregion(maa->maa_st, maa->maa_sh, + maa->maa_offset, NULL, &pc->ioh) ) + panic("macepci_attach: couldn't map"); + + pc->iot = maa->maa_st; + + rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION); printf(": rev %d\n", rev); pc->pc_conf_read = macepci_conf_read; pc->pc_conf_write = macepci_conf_write; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_ADDR) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_FLAGS) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_CONTROL) = 0xff008500; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_HARDINT) = 0; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_SOFTINT) = 0; + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0); + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0); - /* Only fix up the PCI slot, leave SCSI 0 & 1 as is */ - for (device = 3; device < 4; device++) { + /* Turn on PCI error interrupts */ + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL, + MACE_PCI_CONTROL_SERR_ENA | + MACE_PCI_CONTROL_PARITY_ERR | + MACE_PCI_CONTROL_PARK_LIU | + MACE_PCI_CONTROL_OVERRUN_INT | + MACE_PCI_CONTROL_PARITY_INT | + MACE_PCI_CONTROL_SERR_INT | + MACE_PCI_CONTROL_IT_INT | + MACE_PCI_CONTROL_RE_INT | + MACE_PCI_CONTROL_DPED_INT | + MACE_PCI_CONTROL_TAR_INT | + MACE_PCI_CONTROL_MAR_INT); + + /* Must fix up all PCI devices, ahc_pci expects proper i/o mapping */ + for (device = 1; device < 4; device++) { const struct pci_quirkdata *qd; int function, nfuncs; pcireg_t bhlcr, id; - devtag = pci_make_tag(0, 0, device, 0); + devtag = pci_make_tag(pc, 0, device, 0); id = pci_conf_read(pc, devtag, PCI_ID_REG); /* Invalid vendor ID value? */ @@ -160,7 +182,7 @@ macepci_attach(parent, self, aux) nfuncs = 1; for (function = 0; function < nfuncs; function++) { - devtag = pci_make_tag(0, 0, device, function); + devtag = pci_make_tag(pc, 0, device, function); id = pci_conf_read(pc, devtag, PCI_ID_REG); /* Invalid vendor ID value? */ @@ -170,7 +192,7 @@ macepci_attach(parent, self, aux) if (PCI_VENDOR(id) == 0) continue; - pciaddr_resource_manage(0, devtag, NULL, NULL); + pciaddr_resource_manage(pc, devtag, NULL, NULL); } } @@ -178,15 +200,15 @@ macepci_attach(parent, self, aux) * Enable all MACE PCI interrupts. They will be masked by * the CRIME code. */ - control = bus_space_read_4(maa->maa_st, maa->maa_sh, MACEPCI_CONTROL); + control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL); control |= CONTROL_INT_MASK; - bus_space_write_4(maa->maa_st, maa->maa_sh, MACEPCI_CONTROL, control); + bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control); #if NPCI > 0 memset(&pba, 0, sizeof pba); pba.pba_busname = "pci"; -/*XXX*/ pba.pba_iot = 4; -/*XXX*/ pba.pba_memt = 2; +/*XXX*/ pba.pba_iot = SGIMIPS_BUS_SPACE_IO; +/*XXX*/ pba.pba_memt = SGIMIPS_BUS_SPACE_MEM; pba.pba_dmat = &pci_bus_dma_tag; pba.pba_dmat64 = NULL; pba.pba_bus = 0; @@ -200,8 +222,7 @@ macepci_attach(parent, self, aux) pba.pba_flags &= ~PCI_FLAGS_IO_ENABLED; /* Buggy? */ #endif - mace_intr_establish(7, IPL_NONE, macepci_intr, sc); - /*mace_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc);*/ + mace_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc); config_found(self, &pba, macepci_print); #endif @@ -220,9 +241,6 @@ macepci_print(aux, pnp) else aprint_normal(" bus %d", pba->pba_bus); - /* Mega XXX */ - *(volatile u_int32_t *)0xb4000034 = 0; /* prime timer */ - return UNCONF; } @@ -234,19 +252,9 @@ macepci_conf_read(pc, tag, reg) { pcireg_t data; - /* This should be handled by a real interrupt handler */ - if ((*(volatile u_int32_t *)0xbf080004 & ~0x00100000) != 6) - panic("pcierr: %x %x", *(volatile u_int32_t *)0xbf080000, - *(volatile u_int32_t *)0xbf080004); - - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cf8) = tag | reg; - data = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cfc); - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cf8) = 0; - - if (*(volatile u_int32_t *)0xbf080004 & 0xf0000000) { - *(volatile u_int32_t *)0xbf080004 = 0; - return (pcireg_t)-1; - } + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); + data = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA); + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); return data; } @@ -262,9 +270,9 @@ macepci_conf_write(pc, tag, reg, data) if (tag == 0) return; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cf8) = tag | reg; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cfc) = data; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cf8) = 0; + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA, data); + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); } @@ -275,7 +283,88 @@ int macepci_intr(arg) void *arg; { - printf("macepci_intr!\n"); + struct macepci_softc *sc = (struct macepci_softc *)arg; + pci_chipset_tag_t pc = &sc->sc_pc; + u_int32_t error, address; + + error = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS); + address = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR); + while (error & 0xffc00000) { + if (error & MACE_PERR_MASTER_ABORT) { + /* + * this seems to be a more-or-less normal error + * condition (e.g., "pcictl pci0 list" generates + * a _lot_ of these errors, so no message for now + * while I figure out if I missed a trick somewhere. + */ + error &= ~MACE_PERR_MASTER_ABORT; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_TARGET_ABORT) { + printf("mace: target abort at %x\n", address); + error &= ~MACE_PERR_TARGET_ABORT; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_DATA_PARITY_ERR) { + printf("mace: parity error at %x\n", address); + error &= ~MACE_PERR_DATA_PARITY_ERR; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_RETRY_ERR) { + printf("mace: retry error at %x\n", address); + error &= ~MACE_PERR_RETRY_ERR; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_ILLEGAL_CMD) { + printf("mace: illegal command at %x\n", address); + error &= ~MACE_PERR_ILLEGAL_CMD; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_SYSTEM_ERR) { + printf("mace: system error at %x\n", address); + error &= ~MACE_PERR_SYSTEM_ERR; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_INTERRUPT_TEST) { + printf("mace: interrupt test at %x\n", address); + error &= ~MACE_PERR_INTERRUPT_TEST; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_PARITY_ERR) { + printf("mace: parity error at %x\n", address); + error &= ~MACE_PERR_PARITY_ERR; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_RSVD) { + printf("mace: reserved condition at %x\n", address); + error &= ~MACE_PERR_RSVD; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_OVERRUN) { + printf("mace: overrun at %x\n", address); + error &= ~MACE_PERR_OVERRUN; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + } return 0; } @@ -385,9 +474,11 @@ pciaddr_resource_manage(pc, tag, func, ctx) error += pciaddr_do_resource_allocate(pc, tag, mapreg, ctx, type, &addr, size); -/* PCIBIOS_PRINTV(("\n\t%02xh %s 0x%08x 0x%08x", +#if 0 + PCIBIOS_PRINTV(("\n\t%02xh %s 0x%08x 0x%08x", mapreg, type ? "port" : "mem ", - (unsigned int)addr, (unsigned int)size)); */ + (unsigned int)addr, (unsigned int)size)); +#endif } /* enable/disable PCI device */ @@ -409,7 +500,6 @@ pciaddr_resource_manage(pc, tag, func, ctx) if (error) pciaddr.nbogus++; - } bus_addr_t @@ -417,8 +507,8 @@ pciaddr_ioaddr(val) u_int32_t val; { - return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM) - ? PCI_MAPREG_MEM_ADDR(val) : PCI_MAPREG_IO_ADDR(val)); + return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM) ? + PCI_MAPREG_MEM_ADDR(val) : PCI_MAPREG_IO_ADDR(val)); } int @@ -444,7 +534,7 @@ pciaddr_do_resource_allocate(pc, tag, mapreg, ctx, type, addr, size) default: PCIBIOS_PRINTV(("attempt to remap unknown region (addr 0x%lx, " - "size 0x%lx, type %d)\n", *addr, size, type)); + "size 0x%lx, type %d)\n", *addr, size, type)); return 0; } diff --git a/sys/arch/sgimips/pci/pci_machdep.c b/sys/arch/sgimips/pci/pci_machdep.c index 6a29ab02ca31..5de6d4cf329e 100644 --- a/sys/arch/sgimips/pci/pci_machdep.c +++ b/sys/arch/sgimips/pci/pci_machdep.c @@ -1,4 +1,4 @@ -/* $NetBSD: pci_machdep.c,v 1.8 2003/10/04 09:19:23 tsutsui Exp $ */ +/* $NetBSD: pci_machdep.c,v 1.9 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -33,7 +33,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.8 2003/10/04 09:19:23 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.9 2003/10/05 15:38:08 tsutsui Exp $"); #include #include @@ -52,6 +52,8 @@ __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.8 2003/10/04 09:19:23 tsutsui Exp #include #include +#include + /* * PCI doesn't have any special needs; just use * the generic versions of these functions. @@ -88,7 +90,10 @@ pci_bus_maxdevs(pc, busno) int busno; { - return 5; /* 2 on-board SCSI chips, slots 0, 1 and 2 */ + if (busno == 0) + return 5; /* 2 on-board SCSI chips, slots 0, 1 and 2 */ + else + return 0; /* XXX */ } pcitag_t @@ -200,8 +205,6 @@ pci_intr_evcnt(pc, ih) return NULL; } -extern void * crime_intr_establish(int, int, int, int (*)(void *), void *); - void * pci_intr_establish(pc, ih, level, func, arg) pci_chipset_tag_t pc; diff --git a/sys/arch/sgimips/sgimips/autoconf.c b/sys/arch/sgimips/sgimips/autoconf.c index 2fb425c11d0a..279284c09fd6 100644 --- a/sys/arch/sgimips/sgimips/autoconf.c +++ b/sys/arch/sgimips/sgimips/autoconf.c @@ -1,4 +1,4 @@ -/* $NetBSD: autoconf.c,v 1.16 2003/07/15 03:35:54 lukem Exp $ */ +/* $NetBSD: autoconf.c,v 1.17 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -33,7 +33,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.16 2003/07/15 03:35:54 lukem Exp $"); +__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.17 2003/10/05 15:38:08 tsutsui Exp $"); #include "opt_ddb.h" #include "opt_machtypes.h" @@ -83,24 +83,6 @@ cpu_configure() printf("biomask %02x netmask %02x ttymask %02x clockmask %02x\n", biomask >> 8, netmask >> 8, ttymask >> 8, clockmask >> 8); - /* XXXrkb: hack until we get interrupt setup code right */ - if (mach_type == MACH_SGI_IP32) { - u_int64_t mask; - - mask = *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_MASK); - aprint_debug("MACE_ISA_MASK was %llx\n", mask); - mask |= ((1UL << 20) | (1UL << 26)); - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_MASK) = mask; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_FLUSH_W) = 0xffffffff; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK) = 0x30ff10ULL; - - aprint_debug("CRM_MASK: %llx, MACEISA_MASK (%x) %llx\n", - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK), - MACE_ISA_INT_MASK, - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_MASK)); - - } - _splnone(); } diff --git a/sys/arch/sgimips/sgimips/console.c b/sys/arch/sgimips/sgimips/console.c index c828d2f0f436..ca786811084a 100644 --- a/sys/arch/sgimips/sgimips/console.c +++ b/sys/arch/sgimips/sgimips/console.c @@ -1,4 +1,4 @@ -/* $NetBSD: console.c,v 1.10 2003/07/15 03:35:54 lukem Exp $ */ +/* $NetBSD: console.c,v 1.11 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. @@ -28,7 +28,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: console.c,v 1.10 2003/07/15 03:35:54 lukem Exp $"); +__KERNEL_RCSID(0, "$NetBSD: console.c,v 1.11 2003/10/05 15:38:08 tsutsui Exp $"); #include "opt_kgdb.h" #include "opt_machtypes.h" @@ -98,15 +98,15 @@ consinit() strncmp(consdev, "serial", 6) == 0 && (consdev[7] == '0' || consdev[7] == '1')) { /* XXX: hardcoded MACE iotag */ - if (comcnattach(3, ((consdev[7] == '0') ? - MIPS_PHYS_TO_KSEG1(MACE_ISA_SER1_BASE) : - MIPS_PHYS_TO_KSEG1(MACE_ISA_SER2_BASE)), - speed, COM_FREQ, COM_TYPE_NORMAL, - comcnmode) == 0) + if (comcnattach(3, MIPS_PHYS_TO_KSEG1(MACE_BASE + + ((consdev[7] == '0') ? + MACE_ISA_SER1_BASE : MACE_ISA_SER2_BASE)), + speed, COM_FREQ, COM_TYPE_NORMAL, comcnmode) == 0) return; - printf("can't init serial hardware console!\n"); + panic("can't init serial hardware console!"); } + panic("ip32 supports serial console only. sorry."); } #endif /* IP32 && (NCOM > 0) */ diff --git a/sys/arch/sgimips/sgimips/cpu.c b/sys/arch/sgimips/sgimips/cpu.c index f605b957df56..faade6fed8ef 100644 --- a/sys/arch/sgimips/sgimips/cpu.c +++ b/sys/arch/sgimips/sgimips/cpu.c @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.c,v 1.14 2003/07/15 03:35:54 lukem Exp $ */ +/* $NetBSD: cpu.c,v 1.15 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -34,7 +34,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.14 2003/07/15 03:35:54 lukem Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.15 2003/10/05 15:38:08 tsutsui Exp $"); #include "opt_machtypes.h" @@ -73,11 +73,4 @@ cpu_attach(parent, self, aux) { printf(": "); cpu_identify(); - -#ifdef IP22 - if (mach_type == MACH_SGI_IP22) { /* XXX Indy */ - extern void ip22_cache_init(struct device *); - ip22_cache_init(self); - } -#endif } diff --git a/sys/arch/sgimips/sgimips/ip22.c b/sys/arch/sgimips/sgimips/ip22.c index 5acf8f404629..b3716750b710 100644 --- a/sys/arch/sgimips/sgimips/ip22.c +++ b/sys/arch/sgimips/sgimips/ip22.c @@ -1,4 +1,4 @@ -/* $NetBSD: ip22.c,v 1.17 2003/10/04 09:41:27 tsutsui Exp $ */ +/* $NetBSD: ip22.c,v 1.18 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2001, 2002 Rafal K. Boni @@ -28,7 +28,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: ip22.c,v 1.17 2003/10/04 09:41:27 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: ip22.c,v 1.18 2003/10/05 15:38:08 tsutsui Exp $"); #include "opt_cputype.h" #include "opt_machtypes.h" @@ -50,6 +50,7 @@ __KERNEL_RCSID(0, "$NetBSD: ip22.c,v 1.17 2003/10/04 09:41:27 tsutsui Exp $"); u_int32_t next_clk_intr; u_int32_t missed_clk_intrs; static unsigned long last_clk_intr; +u_int32_t int23addr; static struct evcnt mips_int5_evcnt = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "mips", "int 5 (clock)"); @@ -81,7 +82,6 @@ ip22_init(void) { u_int i; u_int32_t sysid; - u_int32_t int23addr; unsigned long cps; unsigned long ctrdiff[3]; @@ -277,14 +277,8 @@ ip22_mappable_intr(void* arg) int intnum; u_int32_t mstat; u_int32_t mmask; - u_int32_t int23addr; int which = (int)arg; - if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) - int23addr = 0x1fbd9000; - else - int23addr = 0x1fbd9880; - ret = 0; mstat = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x10); mmask = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x14 + @@ -314,12 +308,6 @@ ip22_local0_intr() int ret; u_int32_t l0stat; u_int32_t l0mask; - u_int32_t int23addr; - - if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) - int23addr = 0x1fbd9000; - else - int23addr = 0x1fbd9880; ret = 0; l0stat = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x00); @@ -346,12 +334,6 @@ ip22_local1_intr() int ret; u_int32_t l1stat; u_int32_t l1mask; - u_int32_t int23addr; - - if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) - int23addr = 0x1fbd9000; - else - int23addr = 0x1fbd9880; l1stat = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x08); l1mask = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x0c); @@ -381,7 +363,6 @@ ip22_intr_establish(level, ipl, handler, arg) void *arg; { u_int32_t mask; - u_int32_t int23addr; if (level < 0 || level >= NINTR) panic("invalid interrupt level"); @@ -392,11 +373,6 @@ ip22_intr_establish(level, ipl, handler, arg) intrtab[level].ih_fun = handler; intrtab[level].ih_arg = arg; - if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) - int23addr = 0x1fbd9000; - else - int23addr = 0x1fbd9880; - if (level < 8) { mask = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x4); mask |= (1 << level); @@ -479,32 +455,4 @@ ip22_cal_timer(u_int32_t tctrl, u_int32_t tcount) return (endctr - startctr) / roundtime * roundtime; } -void ip22_cache_init(struct device *); - -void -ip22_cache_init(struct device *self) -{ - - /* - * If we don't have an R4000-style cache, then initialize the - * IP22 SysAD L2 cache. - * - * XXX: For now we disable the SysAD cache on R4600/R5k systems, - * as there's no code to drive it; also make sure to clear the - * flags used by the generic MIPS code so it doesn't attempt to - * use the L2. - */ - switch (MIPS_PRID_IMPL(cpu_id)) { - case MIPS_R4600: -#ifndef ENABLE_MIPS_R3NKK - case MIPS_R5000: -#endif - mips_sdcache_size = 0; - mips_sdcache_line_size = 0; - printf("%s: disabling IP22 SysAD L2 cache\n", self->dv_xname); - ip22_sdcache_disable(); - break; - } -} - #endif /* IP22 */ diff --git a/sys/arch/sgimips/sgimips/ip32.c b/sys/arch/sgimips/sgimips/ip32.c index 64fdaf0a55ea..cbc6a203225a 100644 --- a/sys/arch/sgimips/sgimips/ip32.c +++ b/sys/arch/sgimips/sgimips/ip32.c @@ -1,9 +1,9 @@ -/* $NetBSD: ip32.c,v 1.19 2003/10/04 09:41:27 tsutsui Exp $ */ +/* $NetBSD: ip32.c,v 1.20 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang * Copyright (c) 2001, 2002 Rafal K. Boni - * Copyright (c) 2002 Christopher Sekiya + * Copyright (c) 2002, 2003 Christopher Sekiya * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -35,7 +35,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: ip32.c,v 1.19 2003/10/04 09:41:27 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: ip32.c,v 1.20 2003/10/05 15:38:08 tsutsui Exp $"); #include "opt_machtypes.h" @@ -53,7 +53,8 @@ __KERNEL_RCSID(0, "$NetBSD: ip32.c,v 1.19 2003/10/04 09:41:27 tsutsui Exp $"); #include #include -#include +#include +#include void ip32_init(void); void ip32_bus_reset(void); @@ -61,10 +62,6 @@ void ip32_intr(u_int, u_int, u_int, u_int); void ip32_intr_establish(int, int, int (*)(void *), void *); unsigned long ip32_clkread(void); -void crime_intr(u_int); -void *crime_intr_establish(int, int, int, int (*)(void *), void *); -void mace_intr(u_int); - u_int32_t next_clk_intr; u_int32_t missed_clk_intrs; static unsigned long last_clk_intr; @@ -84,6 +81,9 @@ ip32_init(void) u_int64_t baseline; u_int32_t cps; + /* XXX nasty hack */ + bus_space_handle_t ioh = MIPS_PHYS_TO_KSEG1(CRIME_BASE); + /* * NB: don't enable watchdog here as we do on IP22, since the * fixed -- and overly short -- duration of the IP32 watchdog @@ -95,16 +95,15 @@ ip32_init(void) */ /* Reset CRIME CPU & memory error registers */ - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_CPU_ERROR_STAT) = 0; - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_MEM_ERROR_STAT) = 0; + bus_space_write_8(iot, ioh, CRIME_CPU_ERROR_STAT, 0); + bus_space_write_8(iot, ioh, CRIME_MEM_ERROR_STAT, 0); #define WAIT_MS 50 - baseline = *(volatile u_int64_t *) - MIPS_PHYS_TO_KSEG1(CRIME_TIME) & CRIME_TIME_MASK; + baseline = bus_space_read_8(iot, ioh, CRIME_TIME) & CRIME_TIME_MASK; cps = mips3_cp0_count_read(); - while (((*(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_TIME) - & CRIME_TIME_MASK) - baseline) < WAIT_MS * 1000000 / 15) + while (((bus_space_read_8(iot, ioh, CRIME_TIME) & CRIME_TIME_MASK) + - baseline) < WAIT_MS * 1000000 / 15) continue; cps = mips3_cp0_count_read() - cps; cps = cps / 5; @@ -138,8 +137,11 @@ ip32_init(void) void ip32_bus_reset(void) { - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_CPU_ERROR_STAT) = 0; - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_MEM_ERROR_STAT) = 0; + + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_CPU_ERROR_STAT, 0); + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_MEM_ERROR_STAT, 0); } /* @@ -158,29 +160,9 @@ ip32_intr(status, cause, pc, ipending) u_int64_t crime_intstat, crime_intmask, crime_ipending; /* enable watchdog timer, clear it */ - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_CONTROL) |= - CRIME_CONTROL_DOG_ENABLE; - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_WATCHDOG) = 0; - -#if 1 - /* - * XXXrkb: Even if this code makes sense (which I'm not sure of; - * the magic number of "6" seems to correspond to capability bits - * of the card/slot in question -- not 66 Mhz capable, fast B2B - * capable and a medium DEVSEL timing -- and also seem to corres- - * pond to on-reset values of this register), these errors should - * be dealt with in the MACE PCI interrupt, not here! - * - * The 0x00100000 is MACE_PERR_CONFIG_ADDR, so this code should - * panic on any other PCI errors except simple address errors on - * config. space accesses. This also seems wrong, but I lack the - * PCI clue to figure out how to deal with other error ATM... - */ - if ((*(volatile u_int32_t *) MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_FLAGS) & ~0x00100000) != 6) - panic("pcierr: %x %x", - *(volatile u_int32_t *) MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_ADDR), - *(volatile u_int32_t *) MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_FLAGS)); -#endif + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL, CRIME_CONTROL_DOG_ENABLE); + bus_space_write_8(crime_sc->iot, crime_sc->ioh, CRIME_WATCHDOG, 0); if (ipending & MIPS_INT_MASK_5) { last_clk_intr = mips3_cp0_count_read(); @@ -209,8 +191,10 @@ ip32_intr(status, cause, pc, ipending) } if (ipending & MIPS_INT_MASK_0) { - crime_intmask = *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_INTMASK); - crime_intstat = *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_INTSTAT); + crime_intmask = bus_space_read_8(crime_sc->iot, crime_sc->ioh, + CRIME_INTMASK); + crime_intstat = bus_space_read_8(crime_sc->iot, crime_sc->ioh, + CRIME_INTSTAT); crime_ipending = (crime_intstat & crime_intmask); @@ -222,18 +206,28 @@ ip32_intr(status, cause, pc, ipending) if (crime_ipending & 0xffff0000) { /* - * CRIME interrupts for CPU and memory errors + * CRIME interrupts for CPU and memory errors */ if (crime_ipending & CRIME_INT_MEMERR) { - u_int64_t address = *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_MEM_ERROR_ADDR); - u_int64_t status = *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_MEM_ERROR_STAT); - printf("crime: memory error address %llx status %llx\n", address << 2, status); + u_int64_t address = + bus_space_read_8(crime_sc->iot, + crime_sc->ioh, CRIME_MEM_ERROR_ADDR); + u_int64_t status = + bus_space_read_8(crime_sc->iot, + crime_sc->ioh, CRIME_MEM_ERROR_STAT); + printf("crime: memory error address %llx" + " status %llx\n", address << 2, status); ip32_bus_reset(); } if (crime_ipending & CRIME_INT_CRMERR) { - u_int64_t stat = *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_CPU_ERROR_STAT); - printf("crime: cpu error %llx\n", stat); + u_int64_t stat = + bus_space_read_8(crime_sc->iot, + crime_sc->ioh, CRIME_CPU_ERROR_STAT); + printf("crime: cpu error %llx at" + " address %llx\n", stat, + bus_space_read_8(crime_sc->iot, + crime_sc->ioh, CRIME_CPU_ERROR_ADDR)); ip32_bus_reset(); } } diff --git a/sys/arch/sgimips/sgimips/machdep.c b/sys/arch/sgimips/sgimips/machdep.c index cc86e38298c8..2d63222b0c79 100644 --- a/sys/arch/sgimips/sgimips/machdep.c +++ b/sys/arch/sgimips/sgimips/machdep.c @@ -1,4 +1,4 @@ -/* $NetBSD: machdep.c,v 1.58 2003/10/04 09:19:23 tsutsui Exp $ */ +/* $NetBSD: machdep.c,v 1.59 2003/10/05 15:38:08 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -34,13 +34,14 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.58 2003/10/04 09:19:23 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.59 2003/10/05 15:38:08 tsutsui Exp $"); #include "opt_ddb.h" #include "opt_kgdb.h" #include "opt_execfmt.h" #include "opt_cputype.h" #include "opt_machtypes.h" +#include "opt_mips_cache.h" #include #include @@ -77,14 +78,18 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.58 2003/10/04 09:19:23 tsutsui Exp $") #include #include -#if 0 #include +#ifdef ENABLE_MIPS4_CACHE_R10K +#include #endif #include #include +#if defined(IP32) #include +#include +#endif #include "ksyms.h" @@ -144,6 +149,8 @@ void ip20_init(void); #ifdef IP22 void ip22_init(void); +extern void ip22_sdcache_disable(void); +extern void ip22_sdcache_enable(void); #endif #ifdef IP32 @@ -218,11 +225,6 @@ mach_init(argc, argv, magic, btinfo) int kernstartpfn, kernendpfn; int i, rv, nsym; -#if 0 - /* Clear the BSS segment. XXX Is this really necessary? */ - memset(_edata, 0, _end - _edata); -#endif - /* * Initialize ARCS. This will set up the bootstrap console. */ @@ -693,6 +695,9 @@ cpu_reboot(howto, bootstr) int howto; char *bootstr; { +#if defined(IP32) + u_int64_t scratch; +#endif /* Take a snapshot before clobbering any registers. */ if (curlwp) savectx((struct user *)curpcb); @@ -718,7 +723,6 @@ cpu_reboot(howto, bootstr) resettodr(); } -#if 1 /* Clear and disable watchdog timer. */ switch (mach_type) { case MACH_SGI_IP22: @@ -726,13 +730,17 @@ cpu_reboot(howto, bootstr) *(volatile u_int32_t *)0xbfa00004 &= ~0x100; break; +#if defined(IP32) case MACH_SGI_IP32: - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(CRIME_WATCHDOG) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(CRIME_CONTROL) - &= ~CRIME_CONTROL_DOG_ENABLE; + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_WATCHDOG, 0); + scratch = bus_space_read_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL) & ~CRIME_CONTROL_DOG_ENABLE; + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL, scratch); break; - } #endif + } splhigh(); @@ -917,6 +925,9 @@ lookup_bootinfo(int type) void ddb_trap_hook(int where) { +#if defined(IP32) + u_int64_t scratch; +#endif switch (where) { case 1: /* Entry to DDB, turn watchdog off */ switch (mach_type) { @@ -924,14 +935,16 @@ void ddb_trap_hook(int where) *(volatile u_int32_t *)0xbfa00014 = 0; *(volatile u_int32_t *)0xbfa00004 &= ~0x100; break; - +#if defined(IP32) case MACH_SGI_IP32: - *(volatile u_int32_t *) - MIPS_PHYS_TO_KSEG1(CRIME_WATCHDOG)= 0; - *(volatile u_int32_t *) - MIPS_PHYS_TO_KSEG1(CRIME_CONTROL) \ - &= ~CRIME_CONTROL_DOG_ENABLE; + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_WATCHDOG, 0); + scratch = bus_space_read_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL) & ~CRIME_CONTROL_DOG_ENABLE; + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL, scratch); break; +#endif } break; @@ -941,14 +954,16 @@ void ddb_trap_hook(int where) *(volatile u_int32_t *)0xbfa00004 |= 0x100; *(volatile u_int32_t *)0xbfa00014 = 0; break; - +#if defined(IP32) case MACH_SGI_IP32: - *(volatile u_int32_t *) - MIPS_PHYS_TO_KSEG1(CRIME_CONTROL) \ - |= CRIME_CONTROL_DOG_ENABLE; - *(volatile u_int32_t *) - MIPS_PHYS_TO_KSEG1(CRIME_WATCHDOG) = 0; + scratch = bus_space_read_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL) | CRIME_CONTROL_DOG_ENABLE; + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL, scratch); + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_WATCHDOG, 0); break; +#endif } break; } @@ -960,33 +975,49 @@ void mips_machdep_cache_config(void) { volatile u_int32_t cpu_config; - if (mach_type == MACH_SGI_IP32) - { -#if 1 - /* L2 cache does not work on IP32 (yet) */ + arcbios_tree_walk(mips_machdep_find_l2cache, NULL); + + switch (MIPS_PRID_IMPL(cpu_id)) { +#if defined(IP22) + case MIPS_R4600: + /* + * R4600 is on Indy-class machines only. Disable and + * flush pcache. + */ mips_sdcache_size = 0; mips_sdcache_line_size = 0; - + ip22_sdcache_disable(); + break; +#endif +#ifndef ENABLE_MIPS_R3NKK + case MIPS_R5000: +#endif + case MIPS_RM5200: cpu_config = mips3_cp0_config_read(); +#ifdef notyet /* disable r5ksc for now */ + if ((cpu_config & MIPS3_CONFIG_SC) == 0) + r5k_enable_sdcache(); + else +#else cpu_config &= ~MIPS3_CONFIG_SE; mips3_cp0_config_write(cpu_config); -#else - arcbios_tree_walk(mips_machdep_find_l2cache, NULL); - - cpu_config = mips3_cp0_config_read(); - printf("\nbefore mips_machdep_cache_config: SE = %x\n", - cpu_config & MIPS3_CONFIG_SE); - - r5k_enable_sdcache(); - - cpu_config = mips3_cp0_config_read(); - printf("after mips_machdep_cache_config: SE = %x\n", - cpu_config & MIPS3_CONFIG_SE); #endif - } - else /* IP22 works, maybe */ - { - arcbios_tree_walk(mips_machdep_find_l2cache, NULL); + { + mips_sdcache_size = 0; + mips_sdcache_line_size = 0; + } + break; +#ifdef ENABLE_MIPS4_CACHE_R10K + case MIPS_R10000: + cpu_config = mips3_cp0_config_read(); +#ifdef DEBUG + printf("\nr10k cpu config is %x\n", cpu_config); +#endif + break; +#endif /* ENABLE_MIPS4_CACHE_R10K */ + default: + printf("Don't know how to configure SC on this platform.\n"); + break; } }