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Update sc_mptargets atomically, as PEs will be started up in parallel w/o locking here

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This commit is contained in:
jmcneill 2018-09-10 09:48:57 +00:00
parent 36f4d88790
commit b07d637e10
1 changed files with 4 additions and 3 deletions
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7
sys/arch/arm/cortex/gic.c
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@ -1,4 +1,4 @@
/* $NetBSD: gic.c,v 1.35 2018/07/15 16:04:07 jmcneill Exp $ */
/* $NetBSD: gic.c,v 1.36 2018/09/10 09:48:57 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.35 2018/07/15 16:04:07 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.36 2018/09/10 09:48:57 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -43,6 +43,7 @@ __KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.35 2018/07/15 16:04:07 jmcneill Exp $");
#include <sys/evcnt.h>
#include <sys/intr.h>
#include <sys/proc.h>
#include <sys/atomic.h>
#include <arm/armreg.h>
#include <arm/atomic.h>
@ -514,7 +515,7 @@ armgic_cpu_init(struct pic_softc *pic, struct cpu_info *ci)
{
struct armgic_softc * const sc = PICTOSOFTC(pic);
sc->sc_target[cpu_index(ci)] = gicd_find_targets(sc);
sc->sc_mptargets |= sc->sc_target[cpu_index(ci)];
atomic_or_32(&sc->sc_mptargets, sc->sc_target[cpu_index(ci)]);
KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl);
armgic_cpu_init_priorities(sc);
if (!CPU_IS_PRIMARY(ci)) {