PR/49584: Leonardo Taccari: alc(4): add support for AR816x/AR817x chipsets
This commit is contained in:
christos
parent
1eb711493e
commit
afcbf6727b
@ -1,4 +1,4 @@
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.\" $NetBSD: alc.4,v 1.3 2011/12/14 13:24:14 njoly Exp $
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.\" $NetBSD: alc.4,v 1.4 2015/01/18 15:30:03 christos Exp $
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.\"
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.\" Copyright (c) 2009 Kevin Lo <kevlo@openbsd.org>
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.\"
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@ -14,12 +14,12 @@
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.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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.\"
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.Dd February 22, 2011
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.Dd January 18, 2015
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.Dt ALC 4
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.Os
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.Sh NAME
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.Nm alc
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.Nd Atheros AR813x/AR815x Ethernet device
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.Nd Atheros AR813x/AR815x/AR816x/AR817x Ethernet device
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.Sh SYNOPSIS
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.Cd "alc* at pci?"
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.Cd "atphy* at mii?"
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@ -27,7 +27,7 @@
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The
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.Nm
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driver provides support for Ethernet interfaces based on the
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Atheros AR8131/AR8132/AR8151/AR8152 Ethernet chipsets.
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Atheros AR813x/AR815x/AR816x/AR817x Gigabit/Fast Ethernet chipsets.
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.Pp
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The following
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.Ar media
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@ -41,7 +41,7 @@ Set 10Mbps operation.
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.It Cm 100baseTX
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Set 100Mbps (Fast Ethernet) operation.
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.It Cm 1000baseT
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Set 1000Mbps (Gigabit Ethernet) operation (AR8131/AR8151 only).
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Set 1000Mbps (Gigabit Ethernet) operation.
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.El
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.Pp
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For more information on configuring this device, see
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@ -57,5 +57,19 @@ For more information on configuring this device, see
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.Sh HISTORY
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The
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.Nm
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device driver first appeared in
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.Nx 6.0 .
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device driver was written by
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.An Pyun YongHyeon
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and first appeared in
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.Fx 8.0 . It was ported to
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.Ox 4.7
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by
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.An Kevin Lo
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and then ported to
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.Nx 6.0
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by
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.An Fire Crow .
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.An Leonardo Taccari
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ported the AR816x/AR817x support for
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.Nm
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from
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.Fx 11.0 .
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@ -1,4 +1,4 @@
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.\" $NetBSD: atphy.4,v 1.2 2009/01/16 23:26:31 wiz Exp $
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.\" $NetBSD: atphy.4,v 1.3 2015/01/18 15:30:03 christos Exp $
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.\" $OpenBSD: atphy.4,v 1.1 2008/09/26 21:39:34 brad Exp $
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.\"
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.\" Copyright (c) 2008 Brad Smith <brad@comstyle.com>
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@ -15,7 +15,7 @@
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.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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.\"
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.Dd January 16, 2009
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.Dd January 18, 2015
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.Dt ATPHY 4
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.Os
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.Sh NAME
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@ -29,7 +29,9 @@ The
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driver supports the Attansic Technology F1 10/100/1000 Ethernet PHY.
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.Sh SEE ALSO
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.Xr age 4 ,
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.Xr alc 4 ,
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.Xr ifmedia 4 ,
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.Xr intro 4 ,
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.Xr lii 4 ,
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.Xr mii 4 ,
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.Xr ifconfig 8
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@ -1,4 +1,4 @@
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.\" $NetBSD: lii.4,v 1.2 2008/04/30 13:10:54 martin Exp $
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.\" $NetBSD: lii.4,v 1.3 2015/01/18 15:30:03 christos Exp $
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.\"
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.\" Copyright (c) 2008 The NetBSD Foundation, Inc.
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.\" All rights reserved.
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@ -27,7 +27,7 @@
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.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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.\" POSSIBILITY OF SUCH DAMAGE.
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.\"
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.Dd March 29, 2008
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.Dd January 18, 2015
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.Dt LII 4
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.Os
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.Sh NAME
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@ -42,8 +42,8 @@ provides support for the Attansic/Atheros Fast-Ethernet card.
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This card is found in a variety of low-end Asus hardware, notably the
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Asus EeePC.
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.Sh SEE ALSO
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.Xr mii 4 ,
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.Xr ukphy 4
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.Xr atphy 4 ,
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.Xr mii 4
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.Sh HISTORY
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The
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.Nm
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File diff suppressed because it is too large
Load Diff
@ -36,6 +36,17 @@
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#define ATHEROS_AR8152_B_V10 0xC0
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#define ATHEROS_AR8152_B_V11 0xC1
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/*
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* Atheros AR816x/AR817x revisions
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*/
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#define AR816X_REV_A0 0
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#define AR816X_REV_A1 1
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#define AR816X_REV_B0 2
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#define AR816X_REV_C0 3
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#define AR816X_REV_SHIFT 3
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#define AR816X_REV(x) ((x) >> AR816X_REV_SHIFT)
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/* 0x0000 - 0x02FF : PCIe configuration space */
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#define ALC_PEX_UNC_ERR_SEV 0x10C
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@ -51,11 +62,34 @@
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#define PEX_UNC_ERR_SEV_ECRC 0x00080000
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#define PEX_UNC_ERR_SEV_UR 0x00100000
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#define ALC_EEPROM_LD 0x204 /* AR816x */
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#define EEPROM_LD_START 0x00000001
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#define EEPROM_LD_IDLE 0x00000010
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#define EEPROM_LD_DONE 0x00000000
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#define EEPROM_LD_PROGRESS 0x00000020
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#define EEPROM_LD_EXIST 0x00000100
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#define EEPROM_LD_EEPROM_EXIST 0x00000200
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#define EEPROM_LD_FLASH_EXIST 0x00000400
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#define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000
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#define EEPROM_LD_FLASH_END_ADDR_SHIFT 16
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#define ALC_TWSI_CFG 0x218
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#define TWSI_CFG_SW_LD_START 0x00000800
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#define TWSI_CFG_HW_LD_START 0x00001000
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#define TWSI_CFG_LD_EXIST 0x00400000
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#define ALC_SLD 0x218 /* AR816x */
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#define SLD_START 0x00000800
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#define SLD_PROGRESS 0x00001000
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#define SLD_IDLE 0x00002000
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#define SLD_SLVADDR_MASK 0x007F0000
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#define SLD_EXIST 0x00800000
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#define SLD_FREQ_MASK 0x03000000
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#define SLD_FREQ_100K 0x00000000
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#define SLD_FREQ_200K 0x01000000
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#define SLD_FREQ_300K 0x02000000
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#define SLD_FREQ_400K 0x03000000
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#define ALC_PCIE_PHYMISC 0x1000
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#define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
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@ -68,6 +102,9 @@
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#define ALC_TWSI_DEBUG 0x1108
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#define TWSI_DEBUG_DEV_EXIST 0x20000000
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#define ALC_PDLL_TRNS1 0x1104
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#define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800
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#define ALC_EEPROM_CFG 0x12C0
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#define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF
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#define EEPROM_CFG_ADDR_MASK 0x03FF0000
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@ -91,11 +128,14 @@
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#define PM_CFG_SERDES_PD_EX_L1 0x00000040
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#define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080
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#define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00
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#define PM_CFG_RX_L1_AFTER_L0S 0x00000800
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#define PM_CFG_ASPM_L0S_ENB 0x00001000
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#define PM_CFG_CLK_SWH_L1 0x00002000
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#define PM_CFG_CLK_PWM_VER1_1 0x00004000
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#define PM_CFG_PCIE_RECV 0x00008000
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#define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
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#define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000
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#define PM_CFG_TX_L1_AFTER_L0S 0x00080000
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#define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
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#define PM_CFG_LCKDET_TIMER_MASK 0x0F000000
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#define PM_CFG_EN_BUFS_RX_L0S 0x10000000
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@ -109,8 +149,10 @@
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#define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6
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#define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1
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#define PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT 4
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#define PM_CFG_LCKDET_TIMER_DEFAULT 12
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#define PM_CFG_PM_REQ_TIMER_DEFAULT 12
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#define PM_CFG_PM_REQ_TIMER_816X_DEFAULT 15
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#define ALC_LTSSM_ID_CFG 0x12FC
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#define LTSSM_ID_WRO_ENB 0x00001000
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@ -119,6 +161,7 @@
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#define MASTER_RESET 0x00000001
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#define MASTER_TEST_MODE_MASK 0x0000000C
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#define MASTER_BERT_START 0x00000010
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#define MASTER_WAKEN_25M 0x00000020
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#define MASTER_OOB_DIS_OFF 0x00000040
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#define MASTER_SA_TIMER_ENB 0x00000080
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#define MASTER_MTIMER_ENB 0x00000100
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@ -159,7 +202,7 @@
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*/
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#define ALC_IM_TX_TIMER_DEFAULT 50000 /* 50ms */
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#define ALC_GPHY_CFG 0x140C /* 16bits */
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#define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */
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#define GPHY_CFG_EXT_RESET 0x0001
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#define GPHY_CFG_RTL_MODE 0x0002
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#define GPHY_CFG_LED_MODE 0x0004
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@ -176,6 +219,7 @@
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#define GPHY_CFG_PHY_PLL_ON 0x2000
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#define GPHY_CFG_PWDOWN_HW 0x4000
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#define GPHY_CFG_PHY_PLL_BYPASS 0x8000
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#define GPHY_CFG_100AB_ENB 0x00020000
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#define ALC_IDLE_STATUS 0x1410
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#define IDLE_STATUS_RXMAC 0x00000001
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@ -200,9 +244,10 @@
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#define MDIO_CLK_25_10 0x04000000
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#define MDIO_CLK_25_14 0x05000000
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#define MDIO_CLK_25_20 0x06000000
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#define MDIO_CLK_25_28 0x07000000
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#define MDIO_CLK_25_128 0x07000000
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#define MDIO_OP_BUSY 0x08000000
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#define MDIO_AP_ENB 0x10000000
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#define MDIO_MODE_EXT 0x40000000
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#define MDIO_DATA_SHIFT 0
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#define MDIO_REG_ADDR_SHIFT 16
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@ -236,6 +281,23 @@
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#define SERDES_MAC_CLK_SLOWDOWN 0x00020000
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#define SERDES_PHY_CLK_SLOWDOWN 0x00040000
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#define ALC_LPI_CTL 0x1440
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#define LPI_CTL_ENB 0x00000001
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#define ALC_EXT_MDIO 0x1448
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#define EXT_MDIO_REG_MASK 0x0000FFFF
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#define EXT_MDIO_DEVADDR_MASK 0x001F0000
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#define EXT_MDIO_REG_SHIFT 0
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#define EXT_MDIO_DEVADDR_SHIFT 16
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#define EXT_MDIO_REG(x) \
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(((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK)
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#define EXT_MDIO_DEVADDR(x) \
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(((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK)
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#define ALC_IDLE_DECISN_TIMER 0x1474
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#define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400
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#define ALC_MAC_CFG 0x1480
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#define MAC_CFG_TX_ENB 0x00000001
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#define MAC_CFG_RX_ENB 0x00000002
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@ -266,6 +328,7 @@
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#define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000
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#define MAC_CFG_HASH_ALG_CRC32 0x20000000
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#define MAC_CFG_SPEED_MODE_SW 0x40000000
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#define MAC_CFG_FAST_PAUSE 0x80000000
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#define MAC_CFG_PREAMBLE_SHIFT 10
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#define MAC_CFG_PREAMBLE_DEFAULT 7
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@ -366,8 +429,12 @@
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#define ALC_RSS_IDT_TABLE0 0x14E0
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#define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */
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#define ALC_RSS_IDT_TABLE1 0x14E4
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#define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */
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#define ALC_RSS_IDT_TABLE2 0x14E8
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#define ALC_RSS_IDT_TABLE3 0x14EC
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@ -410,6 +477,8 @@
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#define ALC_SRAM_RX_FIFO_ADDR 0x1520
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#define ALC_SRAM_RX_FIFO_LEN 0x1524
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#define SRAM_RX_FIFO_LEN_MASK 0x00000FFF
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#define SRAM_RX_FIFO_LEN_SHIFT 0
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#define ALC_SRAM_TX_FIFO_ADDR 0x1528
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@ -466,8 +535,12 @@
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#define ALC_TDH_HEAD_ADDR_LO 0x157C
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#define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */
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#define ALC_TDL_HEAD_ADDR_LO 0x1580
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#define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */
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#define ALC_TD_RING_CNT 0x1584
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#define TD_RING_CNT_MASK 0x0000FFFF
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#define TD_RING_CNT_SHIFT 0
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@ -487,6 +560,7 @@
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#define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */
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#define TSO_OFFLOAD_THRESH_MASK 0x000007FF
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#define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800
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#define TSO_OFFLOAD_THRESH_SHIFT 0
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#define TSO_OFFLOAD_THRESH_UNIT 8
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#define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3
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@ -534,6 +608,17 @@
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(RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \
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RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB)
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/* AR816x specific bits */
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#define RXQ_CFG_816X_RSS_HASH_IPV4 0x00000004
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#define RXQ_CFG_816X_RSS_HASH_IPV4_TCP 0x00000008
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#define RXQ_CFG_816X_RSS_HASH_IPV6 0x00000010
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#define RXQ_CFG_816X_RSS_HASH_IPV6_TCP 0x00000020
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#define RXQ_CFG_816X_RSS_HASH_MASK 0x0000003C
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#define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080
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#define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00
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#define RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT 8
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#define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100
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#define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */
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#define RX_RD_FREE_THRESH_HI_MASK 0x0000003F
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#define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0
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@ -547,6 +632,12 @@
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#define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000
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#define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0
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#define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16
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/*
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* Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
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* rx-packet(1522) + delay-of-link(64)
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* = 3212.
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*/
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#define RX_FIFO_PAUSE_816X_RSVD 3212
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#define ALC_RD_DMA_CFG 0x15AC
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#define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */
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@ -570,6 +661,7 @@
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#define DMA_CFG_OUT_ORDER 0x00000004
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#define DMA_CFG_RCB_64 0x00000000
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#define DMA_CFG_RCB_128 0x00000008
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#define DMA_CFG_PEND_AUTO_RST 0x00000008
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#define DMA_CFG_RD_BURST_128 0x00000000
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#define DMA_CFG_RD_BURST_256 0x00000010
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#define DMA_CFG_RD_BURST_512 0x00000020
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@ -589,6 +681,14 @@
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#define DMA_CFG_SMB_ENB 0x00200000
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#define DMA_CFG_CMB_NOW 0x00400000
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#define DMA_CFG_SMB_DIS 0x01000000
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#define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000
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#define DMA_CFG_RD_CHNL_SEL_1 0x00000000
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#define DMA_CFG_RD_CHNL_SEL_2 0x04000000
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#define DMA_CFG_RD_CHNL_SEL_3 0x08000000
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#define DMA_CFG_RD_CHNL_SEL_4 0x0C000000
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#define DMA_CFG_WSRAM_RDCTL 0x10000000
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#define DMA_CFG_RD_PEND_CLR 0x20000000
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#define DMA_CFG_WR_PEND_CLR 0x40000000
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#define DMA_CFG_SMB_NOW 0x80000000
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#define DMA_CFG_RD_BURST_MASK 0x07
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#define DMA_CFG_RD_BURST_SHIFT 4
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@ -611,6 +711,12 @@
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#define CMB_TX_TIMER_MASK 0x0000FFFF
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#define CMB_TX_TIMER_SHIFT 0
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#define ALC_MSI_MAP_TBL1 0x15D0
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#define ALC_MSI_ID_MAP 0x15D4
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#define ALC_MSI_MAP_TBL2 0x15D8
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#define ALC_MBOX_RD0_PROD_IDX 0x15E0
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#define ALC_MBOX_RD1_PROD_IDX 0x15E4
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@ -628,12 +734,20 @@
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#define MBOX_TD_PROD_HI_IDX_SHIFT 0
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#define MBOX_TD_PROD_LO_IDX_SHIFT 16
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#define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */
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#define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */
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#define ALC_MBOX_TD_CONS_IDX 0x15F4
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#define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF
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#define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000
|
||||
#define MBOX_TD_CONS_HI_IDX_SHIFT 0
|
||||
#define MBOX_TD_CONS_LO_IDX_SHIFT 16
|
||||
|
||||
#define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */
|
||||
|
||||
#define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */
|
||||
|
||||
#define ALC_MBOX_RD01_CONS_IDX 0x15F8
|
||||
#define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF
|
||||
#define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000
|
||||
@ -662,7 +776,7 @@
|
||||
#define INTR_GPHY 0x00001000
|
||||
#define INTR_GPHY_LOW_PW 0x00002000
|
||||
#define INTR_TXQ_TO_RST 0x00004000
|
||||
#define INTR_TX_PKT 0x00008000
|
||||
#define INTR_TX_PKT0 0x00008000
|
||||
#define INTR_RX_PKT0 0x00010000
|
||||
#define INTR_RX_PKT1 0x00020000
|
||||
#define INTR_RX_PKT2 0x00040000
|
||||
@ -676,6 +790,15 @@
|
||||
#define INTR_PHY_LINK_DOWN 0x04000000
|
||||
#define INTR_DIS_INT 0x80000000
|
||||
|
||||
/* INTR status for AR816x/AR817x 4 TX queues, 8 RX queues */
|
||||
#define INTR_TX_PKT1 0x00000020
|
||||
#define INTR_TX_PKT2 0x00000040
|
||||
#define INTR_TX_PKT3 0x00000080
|
||||
#define INTR_RX_PKT4 0x08000000
|
||||
#define INTR_RX_PKT5 0x10000000
|
||||
#define INTR_RX_PKT6 0x20000000
|
||||
#define INTR_RX_PKT7 0x40000000
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
#define ALC_INTR_MASK 0x1604
|
||||
|
||||
@ -687,6 +810,7 @@
|
||||
(INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \
|
||||
INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN)
|
||||
#else
|
||||
#define INTR_TX_PKT INTR_TX_PKT0
|
||||
#define INTR_RX_PKT INTR_RX_PKT0
|
||||
#define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN
|
||||
#endif
|
||||
@ -708,11 +832,54 @@
|
||||
#define HDS_CFG_BACKFILLSIZE_SHIFT 8
|
||||
#define HDS_CFG_MAX_HDRSIZE_SHIFT 20
|
||||
|
||||
#define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */
|
||||
|
||||
#define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */
|
||||
|
||||
#define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */
|
||||
|
||||
#define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */
|
||||
|
||||
/* AR813x/AR815x registers for MAC statistics */
|
||||
#define ALC_RX_MIB_BASE 0x1700
|
||||
|
||||
#define ALC_TX_MIB_BASE 0x1760
|
||||
|
||||
#define ALC_DRV 0x1804 /* AR816x */
|
||||
#define DRV_ASPM_SPD10LMT_1M 0x00000000
|
||||
#define DRV_ASPM_SPD10LMT_10M 0x00000001
|
||||
#define DRV_ASPM_SPD10LMT_100M 0x00000002
|
||||
#define DRV_ASPM_SPD10LMT_NO 0x00000003
|
||||
#define DRV_ASPM_SPD10LMT_MASK 0x00000003
|
||||
#define DRV_ASPM_SPD100LMT_1M 0x00000000
|
||||
#define DRV_ASPM_SPD100LMT_10M 0x00000004
|
||||
#define DRV_ASPM_SPD100LMT_100M 0x00000008
|
||||
#define DRV_ASPM_SPD100LMT_NO 0x0000000C
|
||||
#define DRV_ASPM_SPD100LMT_MASK 0x0000000C
|
||||
#define DRV_ASPM_SPD1000LMT_100M 0x00000000
|
||||
#define DRV_ASPM_SPD1000LMT_NO 0x00000010
|
||||
#define DRV_ASPM_SPD1000LMT_1M 0x00000020
|
||||
#define DRV_ASPM_SPD1000LMT_10M 0x00000030
|
||||
#define DRV_ASPM_SPD1000LMT_MASK 0x00000000
|
||||
#define DRV_WOLCAP_BIOS_EN 0x00000100
|
||||
#define DRV_WOLMAGIC_EN 0x00000200
|
||||
#define DRV_WOLLINKUP_EN 0x00000400
|
||||
#define DRV_WOLPATTERN_EN 0x00000800
|
||||
#define DRV_AZ_EN 0x00001000
|
||||
#define DRV_WOLS5_BIOS_EN 0x00010000
|
||||
#define DRV_WOLS5_EN 0x00020000
|
||||
#define DRV_DISABLE 0x00040000
|
||||
#define DRV_PHY_MASK 0x1FE00000
|
||||
#define DRV_PHY_EEE 0x00200000
|
||||
#define DRV_PHY_APAUSE 0x00400000
|
||||
#define DRV_PHY_PAUSE 0x00800000
|
||||
#define DRV_PHY_DUPLEX 0x01000000
|
||||
#define DRV_PHY_10 0x02000000
|
||||
#define DRV_PHY_100 0x04000000
|
||||
#define DRV_PHY_1000 0x08000000
|
||||
#define DRV_PHY_AUTO 0x10000000
|
||||
#define DRV_PHY_SHIFT 21
|
||||
|
||||
#define ALC_CLK_GATING_CFG 0x1814
|
||||
#define CLK_GATING_DMAW_ENB 0x0001
|
||||
#define CLK_GATING_DMAR_ENB 0x0002
|
||||
@ -725,6 +892,52 @@
|
||||
|
||||
#define ALC_DEBUG_DATA1 0x1904
|
||||
|
||||
#define ALC_MSI_RETRANS_TIMER 0x1920
|
||||
#define MSI_RETRANS_TIMER_MASK 0x0000FFFF
|
||||
#define MSI_RETRANS_MASK_SEL_STD 0x00000000
|
||||
#define MSI_RETRANS_MASK_SEL_LINE 0x00010000
|
||||
#define MSI_RETRANS_TIMER_SHIFT 0
|
||||
|
||||
#define ALC_WRR 0x1938
|
||||
#define WRR_PRI0_MASK 0x0000001F
|
||||
#define WRR_PRI1_MASK 0x00001F00
|
||||
#define WRR_PRI2_MASK 0x001F0000
|
||||
#define WRR_PRI3_MASK 0x1F000000
|
||||
#define WRR_PRI_RESTRICT_MASK 0x60000000
|
||||
#define WRR_PRI_RESTRICT_ALL 0x00000000
|
||||
#define WRR_PRI_RESTRICT_HI 0x20000000
|
||||
#define WRR_PRI_RESTRICT_HI2 0x40000000
|
||||
#define WRR_PRI_RESTRICT_NONE 0x60000000
|
||||
#define WRR_PRI0_SHIFT 0
|
||||
#define WRR_PRI1_SHIFT 8
|
||||
#define WRR_PRI2_SHIFT 16
|
||||
#define WRR_PRI3_SHIFT 24
|
||||
#define WRR_PRI_DEFAULT 4
|
||||
#define WRR_PRI_RESTRICT_SHIFT 29
|
||||
|
||||
#define ALC_HQTD_CFG 0x193C
|
||||
#define HQTD_CFG_Q1_BURST_MASK 0x0000000F
|
||||
#define HQTD_CFG_Q2_BURST_MASK 0x000000F0
|
||||
#define HQTD_CFG_Q3_BURST_MASK 0x00000F00
|
||||
#define HQTD_CFG_BURST_ENB 0x80000000
|
||||
#define HQTD_CFG_Q1_BURST_SHIFT 0
|
||||
#define HQTD_CFG_Q2_BURST_SHIFT 4
|
||||
#define HQTD_CFG_Q3_BURST_SHIFT 8
|
||||
|
||||
#define ALC_MISC 0x19C0
|
||||
#define MISC_INTNLOSC_OPEN 0x00000008
|
||||
#define MISC_ISO_ENB 0x00001000
|
||||
#define MISC_PSW_OCP_MASK 0x00E00000
|
||||
#define MISC_PSW_OCP_SHIFT 21
|
||||
#define MISC_PSW_OCP_DEFAULT 7
|
||||
|
||||
#define ALC_MISC2 0x19C8
|
||||
#define MISC2_CALB_START 0x00000001
|
||||
|
||||
#define ALC_MISC3 0x19CC
|
||||
#define MISC3_25M_NOTO_INTNL 0x00000001
|
||||
#define MISC3_25M_BY_SW 0x00000002
|
||||
|
||||
#define ALC_MII_DBG_ADDR 0x1D
|
||||
#define ALC_MII_DBG_DATA 0x1E
|
||||
|
||||
@ -744,6 +957,9 @@
|
||||
#define ANA_SEL_CLK125M_DSP 0x8000
|
||||
#define ANA_MANUL_SWICH_ON_SHIFT 1
|
||||
|
||||
#define MII_DBG_ANACTL 0x00
|
||||
#define DBG_ANACTL_DEFAULT 0x02EF
|
||||
|
||||
#define MII_ANA_CFG4 0x04
|
||||
#define ANA_IECHO_ADJ_MASK 0x0F
|
||||
#define ANA_IECHO_ADJ_3_MASK 0x000F
|
||||
@ -755,6 +971,9 @@
|
||||
#define ANA_IECHO_ADJ_1_SHIFT 8
|
||||
#define ANA_IECHO_ADJ_0_SHIFT 12
|
||||
|
||||
#define MII_DBG_SYSMODCTL 0x04
|
||||
#define DBG_SYSMODCTL_DEFAULT 0xBB8B
|
||||
|
||||
#define MII_ANA_CFG5 0x05
|
||||
#define ANA_SERDES_CDR_BW_MASK 0x0003
|
||||
#define ANA_MS_PAD_DBG 0x0004
|
||||
@ -771,9 +990,17 @@
|
||||
#define ANA_SERDES_CDR_BW_SHIFT 0
|
||||
#define ANA_SERDES_TH_LOS_SHIFT 4
|
||||
|
||||
#define MII_DBG_SRDSYSMOD 0x05
|
||||
#define DBG_SRDSYSMOD_DEFAULT 0x2C46
|
||||
|
||||
#define MII_ANA_CFG11 0x0B
|
||||
#define ANA_PS_HIB_EN 0x8000
|
||||
|
||||
#define MII_DBG_HIBNEG 0x0B
|
||||
#define DBG_HIBNEG_HIB_PULSE 0x1000
|
||||
#define DBG_HIBNEG_PSHIB_EN 0x8000
|
||||
#define DBG_HIBNEG_DEFAULT 0xBC40
|
||||
|
||||
#define MII_ANA_CFG18 0x12
|
||||
#define ANA_TEST_MODE_10BT_01MASK 0x0003
|
||||
#define ANA_LOOP_SEL_10BT 0x0004
|
||||
@ -788,9 +1015,36 @@
|
||||
#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
|
||||
#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
|
||||
|
||||
#define MII_DBG_TST10BTCFG 0x12
|
||||
#define DBG_TST10BTCFG_DEFAULT 0x4C04
|
||||
|
||||
#define MII_DBG_AZ_ANADECT 0x15
|
||||
#define DBG_AZ_ANADECT_DEFAULT 0x3220
|
||||
#define DBG_AZ_ANADECT_LONG 0x3210
|
||||
|
||||
#define MII_DBG_MSE16DB 0x18
|
||||
#define DBG_MSE16DB_UP 0x05EA
|
||||
#define DBG_MSE16DB_DOWN 0x02EA
|
||||
|
||||
#define MII_DBG_MSE20DB 0x1C
|
||||
#define DBG_MSE20DB_TH_MASK 0x01FC
|
||||
#define DBG_MSE20DB_TH_DEFAULT 0x2E
|
||||
#define DBG_MSE20DB_TH_HI 0x54
|
||||
#define DBG_MSE20DB_TH_SHIFT 2
|
||||
|
||||
#define MII_DBG_AGC 0x23
|
||||
#define DBG_AGC_2_VGA_MASK 0x3F00
|
||||
#define DBG_AGC_2_VGA_SHIFT 8
|
||||
#define DBG_AGC_LONG1G_LIMT 40
|
||||
#define DBG_AGC_LONG100M_LIMT 44
|
||||
|
||||
#define MII_ANA_CFG41 0x29
|
||||
#define ANA_TOP_PS_EN 0x8000
|
||||
|
||||
#define MII_DBG_LEGCYPS 0x29
|
||||
#define DBG_LEGCYPS_ENB 0x8000
|
||||
#define DBG_LEGCYPS_DEFAULT 0x129D
|
||||
|
||||
#define MII_ANA_CFG54 0x36
|
||||
#define ANA_LONG_CABLE_TH_100_MASK 0x003F
|
||||
#define ANA_DESERVED 0x0040
|
||||
@ -801,6 +1055,51 @@
|
||||
#define ANA_LONG_CABLE_TH_100_SHIFT 0
|
||||
#define ANA_SHORT_CABLE_TH_100_SHIFT 8
|
||||
|
||||
#define MII_DBG_TST100BTCFG 0x36
|
||||
#define DBG_TST100BTCFG_DEFAULT 0xE12C
|
||||
|
||||
#define MII_DBG_GREENCFG 0x3B
|
||||
#define DBG_GREENCFG_DEFAULT 0x7078
|
||||
|
||||
#define MII_DBG_GREENCFG2 0x3D
|
||||
#define DBG_GREENCFG2_GATE_DFSE_EN 0x0080
|
||||
#define DBG_GREENCFG2_BP_GREEN 0x8000
|
||||
|
||||
/* Device addr 3 */
|
||||
#define MII_EXT_PCS 3
|
||||
|
||||
#define MII_EXT_CLDCTL3 0x8003
|
||||
#define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000
|
||||
|
||||
#define MII_EXT_CLDCTL5 0x8005
|
||||
#define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000
|
||||
|
||||
#define MII_EXT_CLDCTL6 0x8006
|
||||
#define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF
|
||||
#define EXT_CLDCTL6_CAB_LEN_SHIFT 0
|
||||
#define EXT_CLDCTL6_CAB_LEN_SHORT1G 116
|
||||
#define EXT_CLDCTL6_CAB_LEN_SHORT100M 152
|
||||
|
||||
#define MII_EXT_VDRVBIAS 0x8062
|
||||
#define EXT_VDRVBIAS_DEFAULT 3
|
||||
|
||||
/* Device addr 7 */
|
||||
#define MII_EXT_ANEG 7
|
||||
|
||||
#define MII_EXT_ANEG_LOCAL_EEEADV 0x3C
|
||||
#define ANEG_LOCA_EEEADV_100BT 0x0002
|
||||
#define ANEG_LOCA_EEEADV_1000BT 0x0004
|
||||
|
||||
#define MII_EXT_ANEG_AFE 0x801A
|
||||
#define ANEG_AFEE_10BT_100M_TH 0x0040
|
||||
|
||||
#define MII_EXT_ANEG_S3DIG10 0x8023
|
||||
#define ANEG_S3DIG10_SL 0x0001
|
||||
#define ANEG_S3DIG10_DEFAULT 0
|
||||
|
||||
#define MII_EXT_ANEG_NLP78 0x8027
|
||||
#define ANEG_NLP78_120M_DEFAULT 0x8A05
|
||||
|
||||
/* Statistics counters collected by the MAC. */
|
||||
struct smb {
|
||||
/* Rx stats. */
|
||||
@ -991,6 +1290,10 @@ struct tx_desc {
|
||||
/* Water mark to kick reclaiming Tx buffers. */
|
||||
#define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10)
|
||||
|
||||
/*
|
||||
* AR816x controllers support up to 16 messages but this driver
|
||||
* uses single message.
|
||||
*/
|
||||
#define ALC_MSI_MESSAGES 1
|
||||
#define ALC_MSIX_MESSAGES 1
|
||||
|
||||
@ -1166,12 +1469,13 @@ struct alc_softc {
|
||||
#define ALC_FLAG_MSIX 0x0008
|
||||
#define ALC_FLAG_FASTETHER 0x0020
|
||||
#define ALC_FLAG_JUMBO 0x0040
|
||||
#define ALC_FLAG_ASPM_MON 0x0080
|
||||
#define ALC_FLAG_CMB_BUG 0x0100
|
||||
#define ALC_FLAG_SMB_BUG 0x0200
|
||||
#define ALC_FLAG_L0S 0x0400
|
||||
#define ALC_FLAG_L1S 0x0800
|
||||
#define ALC_FLAG_APS 0x1000
|
||||
#define ALC_FLAG_AR816X_FAMILY 0x2000
|
||||
#define ALC_FLAG_LINK_WAR 0x4000
|
||||
#define ALC_FLAG_LINK 0x8000
|
||||
|
||||
callout_t sc_tick_ch;
|
||||
@ -1208,4 +1512,7 @@ do { \
|
||||
#define ALC_TIMEOUT 1000
|
||||
#define ALC_PHY_TIMEOUT 1000
|
||||
|
||||
/* For compatibility with FreeBSD */
|
||||
#define IFM_UNKNOWN 31
|
||||
|
||||
#endif /* _IF_ALCREG_H */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
$NetBSD: pcidevs,v 1.1212 2015/01/16 09:56:53 msaitoh Exp $
|
||||
$NetBSD: pcidevs,v 1.1213 2015/01/18 15:30:03 christos Exp $
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995, 1996 Christopher G. Demetriou
|
||||
@ -1182,6 +1182,7 @@ product ATTANSIC AR8171 0x10a1 AR8171
|
||||
product ATTANSIC ETHERNET_100 0x2048 L2 100 Mbit Ethernet Adapter
|
||||
product ATTANSIC AR8152_B 0x2060 AR8152 v1.1 Fast Ethernet Adapter
|
||||
product ATTANSIC AR8152_B2 0x2062 AR8152 v2.0 Fast Ethernet Adapter
|
||||
product ATTANSIC E2200 0xe091 E2200
|
||||
|
||||
/* ATI products */
|
||||
/* See http://www.x.org/wiki/Radeon%20ASICs */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user