From af63f8979cc52eb53e8136b2dbc4c5ef53afe9e4 Mon Sep 17 00:00:00 2001 From: thorpej Date: Mon, 28 May 2001 18:19:27 +0000 Subject: [PATCH] D'oh, clear the soft interrupt bits in CAUSE *before* servicing soft interrupts, rather than after, so that soft interrupts scheduled by other soft interrupts don't get lost. --- sys/arch/algor/algor/interrupt.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/sys/arch/algor/algor/interrupt.c b/sys/arch/algor/algor/interrupt.c index d7e8e2c1d79b..7047dda52321 100644 --- a/sys/arch/algor/algor/interrupt.c +++ b/sys/arch/algor/algor/interrupt.c @@ -1,4 +1,4 @@ -/* $NetBSD: interrupt.c,v 1.1 2001/05/28 16:22:15 thorpej Exp $ */ +/* $NetBSD: interrupt.c,v 1.2 2001/05/28 18:19:27 thorpej Exp $ */ /*- * Copyright (c) 2001 The NetBSD Foundation, Inc. @@ -124,9 +124,12 @@ cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) (*algor_iointr)(status, cause, pc, ipending); } - if ((ipending & (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)) == 0) + ipending &= (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0); + if (ipending == 0) return; + _clrsoftintr(ipending); + for (i = _IPL_NSOFT - 1; i >= 0; i--) { if ((ipending & ipl_si_to_sr[i]) == 0) continue; @@ -154,7 +157,6 @@ cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) (*sih->sih_fn)(sih->sih_arg); } } - _clrsoftintr(MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0); } /*