From aef222ecba09595e69c9eeb5f4e3dbccdf1c9907 Mon Sep 17 00:00:00 2001 From: mlelstv Date: Fri, 25 Sep 2009 13:51:27 +0000 Subject: [PATCH] The FPU Tag word is a 16bit register, in FPU (387) mode it defines 2-bit tags for each FPU data register, in MMX mode it defines 1-bit tags for each data register. The single bit tags are stored in the lower 8 bits and thus in the first byte of the save frame. See amd64/include/fpu.h and the IA-32 Software Developer's manual Vol 2A. --- sys/arch/i386/include/npx.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/arch/i386/include/npx.h b/sys/arch/i386/include/npx.h index 5af5e0a5f931..2de34d86536f 100644 --- a/sys/arch/i386/include/npx.h +++ b/sys/arch/i386/include/npx.h @@ -1,4 +1,4 @@ -/* $NetBSD: npx.h,v 1.22 2006/05/02 19:03:24 drochner Exp $ */ +/* $NetBSD: npx.h,v 1.23 2009/09/25 13:51:27 mlelstv Exp $ */ /*- * Copyright (c) 1990 The Regents of the University of California. @@ -81,8 +81,8 @@ struct save87 { struct envxmm { /*0*/ uint16_t en_cw; /* FPU Control Word */ uint16_t en_sw; /* FPU Status Word */ - uint8_t en_rsvd0; uint8_t en_tw; /* FPU Tag Word (abridged) */ + uint8_t en_rsvd0; uint16_t en_opcode; /* FPU Opcode */ uint32_t en_fip; /* FPU Instruction Pointer */ uint16_t en_fcs; /* FPU IP selector */