Add "options ARM32_DISABLE_ALIGNMENT_FAULTS" to forcibly disable

alignment fault checking if necessary.

This option gets the acorn32 port working again.

XXX: Richard Earnshaw suggested enabling alignment faults for
XXX: userland only on acorn32. Need to investigate this.
This commit is contained in:
scw 2003-11-05 12:53:15 +00:00
parent 754f153b0d
commit aee833c0ee
3 changed files with 54 additions and 18 deletions

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@ -1,4 +1,4 @@
# $NetBSD: std.acorn32,v 1.1 2001/10/05 22:27:47 reinoud Exp $
# $NetBSD: std.acorn32,v 1.2 2003/11/05 12:53:15 scw Exp $
#
# standard NetBSD/arm32 options
@ -10,3 +10,7 @@ options EXEC_SCRIPT
# To support easy transit to ../arch/arm/arm32
options ARM32
# Since the hardware is not capable of half-word loads/stores,
# Acorn machines and alignment faults do not play nice together.
options ARM32_DISABLE_ALIGNMENT_FAULTS

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@ -1,4 +1,4 @@
/* $NetBSD: cpufunc.c,v 1.64 2003/10/25 19:44:42 scw Exp $ */
/* $NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@ -46,7 +46,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.64 2003/10/25 19:44:42 scw Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@ -1614,8 +1614,7 @@ arm6_setup(args)
/* Set up default control registers bits */
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
| CPU_CONTROL_AFLT_ENABLE;
| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE;
cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
@ -1626,6 +1625,10 @@ arm6_setup(args)
cpuctrl |= CPU_CONTROL_LABT_ENABLE;
#endif /* ARM6_LATE_ABORT */
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl);
cpuctrl = parse_cpu_options(args, arm6_options, cpuctrl);
@ -1663,8 +1666,7 @@ arm7_setup(args)
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
| CPU_CONTROL_AFLT_ENABLE;
| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE;
cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
@ -1672,6 +1674,10 @@ arm7_setup(args)
| CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BEND_ENABLE
| CPU_CONTROL_AFLT_ENABLE;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl);
cpuctrl = parse_cpu_options(args, arm7_options, cpuctrl);
@ -1752,14 +1758,17 @@ arm8_setup(args)
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
| CPU_CONTROL_AFLT_ENABLE;
| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE;
cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
| CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_ROM_ENABLE
| CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl);
cpuctrl = parse_cpu_options(args, arm8_options, cpuctrl);
@ -1833,7 +1842,7 @@ arm9_setup(args)
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_AFLT_ENABLE;
| CPU_CONTROL_WBUF_ENABLE;
cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
@ -1842,6 +1851,10 @@ arm9_setup(args)
| CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
| CPU_CONTROL_CPCLK;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
cpuctrl = parse_cpu_options(args, arm9_options, cpuctrl);
#ifdef __ARMEB__
@ -1879,8 +1892,7 @@ arm10_setup(args)
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BPRD_ENABLE
| CPU_CONTROL_AFLT_ENABLE;
| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BPRD_ENABLE;
cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
@ -1888,6 +1900,10 @@ arm10_setup(args)
| CPU_CONTROL_BPRD_ENABLE
| CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
cpuctrl = parse_cpu_options(args, arm10_options, cpuctrl);
#ifdef __ARMEB__
@ -1935,7 +1951,7 @@ sa110_setup(args)
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_AFLT_ENABLE;
| CPU_CONTROL_WBUF_ENABLE;
cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
@ -1944,6 +1960,10 @@ sa110_setup(args)
| CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
| CPU_CONTROL_CPCLK;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
cpuctrl = parse_cpu_options(args, sa110_options, cpuctrl);
#ifdef __ARMEB__
@ -1992,8 +2012,7 @@ sa11x0_setup(args)
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE
| CPU_CONTROL_AFLT_ENABLE;
| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE;
cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
@ -2002,6 +2021,10 @@ sa11x0_setup(args)
| CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
| CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
cpuctrl = parse_cpu_options(args, sa11x0_options, cpuctrl);
#ifdef __ARMEB__
@ -2041,7 +2064,7 @@ ixp12x0_setup(args)
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE
| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_AFLT_ENABLE;
| CPU_CONTROL_IC_ENABLE;
cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_AFLT_ENABLE
| CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE
@ -2049,6 +2072,10 @@ ixp12x0_setup(args)
| CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_IC_ENABLE
| CPU_CONTROL_VECRELOC;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
cpuctrl = parse_cpu_options(args, ixp12x0_options, cpuctrl);
#ifdef __ARMEB__
@ -2102,7 +2129,7 @@ xscale_setup(args)
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE
| CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_AFLT_ENABLE;
| CPU_CONTROL_BPRD_ENABLE;
cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
@ -2111,6 +2138,10 @@ xscale_setup(args)
| CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
| CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
cpuctrl = parse_cpu_options(args, xscale_options, cpuctrl);
#ifdef __ARMEB__

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@ -1,4 +1,4 @@
# $NetBSD: files.arm,v 1.75 2003/10/23 15:03:24 scw Exp $
# $NetBSD: files.arm,v 1.76 2003/11/05 12:53:15 scw Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defflag ARM32
@ -16,6 +16,7 @@ defflag opt_cpuoptions.h XSCALE_CACHE_WRITE_THROUGH
defflag opt_cpuoptions.h XSCALE_CACHE_WRITE_BACK
defflag opt_cpuoptions.h XSCALE_NO_COALESCE_WRITES
defflag opt_cpuoptions.h XSCALE_CACHE_READ_WRITE_ALLOCATE
defflag opt_cpuoptions.h ARM32_DISABLE_ALIGNMENT_FAULTS
# Interrupt implementation header definition.
defparam opt_arm_intr_impl.h ARM_INTR_IMPL