Partial A80 GMAC support. Needs help from PMU to power it up still.
This commit is contained in:
jmcneill
parent
b003a9006c
commit
ae22139e51
@ -31,7 +31,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.19 2014/11/23 23:05:19 jmcneill Exp $");
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__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.20 2014/12/05 18:41:41 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -69,6 +69,9 @@ static const struct awin_gpio_pinset awin_gige_gpio_pinset_a31 = {
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'A', AWIN_A31_PIO_PA_GMAC_FUNC, AWIN_A31_PIO_PA_GMAC_PINS, 0, 3
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};
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static const struct awin_gpio_pinset awin_gige_gpio_pinset_a80 = {
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'A', AWIN_A80_PIO_PA_GMAC_FUNC, AWIN_A80_PIO_PA_GMAC_PINS, 0, 3
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};
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CFATTACH_DECL_NEW(awin_gige, sizeof(struct awin_gige_softc),
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awin_gige_match, awin_gige_attach, NULL, NULL);
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@ -102,12 +105,26 @@ awin_gige_attach(device_t parent, device_t self, void *aux)
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struct awin_gige_softc * const sc = device_private(self);
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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struct awin_gpio_pinset pinset =
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awin_chip_id() == AWIN_CHIP_ID_A31 ?
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awin_gige_gpio_pinset_a31 : awin_gige_gpio_pinset;
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struct awin_gpio_pinset pinset;
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prop_dictionary_t cfg = device_properties(self);
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uint32_t clkreg;
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const char *phy_type, *pin_name;
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bus_space_handle_t bsh;
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switch (awin_chip_id()) {
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case AWIN_CHIP_ID_A80:
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bsh = aio->aio_a80_core2_bsh;
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pinset = awin_gige_gpio_pinset_a80;
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break;
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case AWIN_CHIP_ID_A31:
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bsh = aio->aio_core_bsh;
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pinset = awin_gige_gpio_pinset_a31;
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break;
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default:
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bsh = aio->aio_core_bsh;
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pinset = awin_gige_gpio_pinset;
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break;
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}
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sc->sc_core.sc_dev = self;
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@ -116,7 +133,7 @@ awin_gige_attach(device_t parent, device_t self, void *aux)
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sc->sc_core.sc_bst = aio->aio_core_bst;
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sc->sc_core.sc_dmat = aio->aio_dmat;
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bus_space_subregion(sc->sc_core.sc_bst, aio->aio_core_bsh,
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bus_space_subregion(sc->sc_core.sc_bst, bsh,
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loc->loc_offset, loc->loc_size, &sc->sc_core.sc_bsh);
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aprint_naive("\n");
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@ -147,10 +164,14 @@ awin_gige_attach(device_t parent, device_t self, void *aux)
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/*
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* Enable GMAC clock
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*/
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if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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if (awin_chip_id() == AWIN_CHIP_ID_A80) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_REG,
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AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_GMAC, 0);
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} else if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_AHB_GATING0_REG, AWIN_A31_AHB_GATING0_GMAC, 0);
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} else {
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} else if (awin_chip_id() == AWIN_CHIP_ID_A20) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_AHB_GATING1_REG, AWIN_AHB_GATING1_GMAC, 0);
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}
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@ -158,9 +179,14 @@ awin_gige_attach(device_t parent, device_t self, void *aux)
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/*
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* Soft reset
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*/
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if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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if (awin_chip_id() == AWIN_CHIP_ID_A80) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A31_AHB_RESET0_REG, AWIN_A31_AHB_RESET0_GMAC_RST, 0);
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AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_REG,
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AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_GMAC, 0);
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} else if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A31_AHB_RESET0_REG,
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AWIN_A31_AHB_RESET0_GMAC_RST, 0);
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}
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/*
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@ -184,7 +210,11 @@ awin_gige_attach(device_t parent, device_t self, void *aux)
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} else {
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panic("unknown phy type '%s'", phy_type);
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}
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if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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if (awin_chip_id() == AWIN_CHIP_ID_A80) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_a80_core2_bsh,
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AWIN_A80_SYS_CTRL_OFFSET + AWIN_A80_SYS_CTRL_EMAC_CLK_REG,
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clkreg, AWIN_GMAC_CLK_PIT|AWIN_GMAC_CLK_TCS);
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} else if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A31_GMAC_CLK_REG, clkreg,
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AWIN_GMAC_CLK_PIT|AWIN_GMAC_CLK_TCS);
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@ -31,7 +31,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.34 2014/12/05 17:32:08 jmcneill Exp $");
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__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.35 2014/12/05 18:41:41 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -56,6 +56,7 @@ static struct awinio_softc {
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bus_space_handle_t sc_bsh;
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bus_space_handle_t sc_ccm_bsh;
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bus_space_handle_t sc_a80_usb_bsh;
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bus_space_handle_t sc_a80_core2_bsh;
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bus_dma_tag_t sc_dmat;
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bus_dma_tag_t sc_coherent_dmat;
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} awinio_sc;
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@ -168,6 +169,7 @@ static const struct awin_locators awin_locators[] = {
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{ "awe", OFFANDSIZE(EMAC), NOPORT, AWIN_IRQ_EMAC, A10|A20 },
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{ "awge", OFFANDSIZE(GMAC), NOPORT, AWIN_IRQ_GMAC, A20 },
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{ "awge", OFFANDSIZE(A31_GMAC), NOPORT, AWIN_A31_IRQ_GMAC, A31 },
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{ "awge", OFFANDSIZE(A80_GMAC), NOPORT, AWIN_A80_IRQ_EMAC, A80 },
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{ "awincrypto", OFFANDSIZE(SS), NOPORT, AWIN_IRQ_SS, AANY },
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{ "awinac", OFFANDSIZE(AC), NOPORT, AWIN_IRQ_AC, A10|A20 },
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{ "awinac", OFFANDSIZE(AC), NOPORT, AWIN_A31_IRQ_AC, A31 },
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@ -219,6 +221,8 @@ awinio_attach(device_t parent, device_t self, void *aux)
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AWIN_A80_CCU_SCLK_OFFSET, 0x1000, &sc->sc_ccm_bsh);
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bus_space_map(sc->sc_bst, AWIN_A80_USB_PBASE,
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AWIN_A80_USB_SIZE, 0, &sc->sc_a80_usb_bsh);
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bus_space_map(sc->sc_bst, AWIN_A80_CORE2_PBASE,
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AWIN_A80_CORE2_SIZE, 0, &sc->sc_a80_core2_bsh);
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break;
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default:
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bus_space_subregion(sc->sc_bst, sc->sc_bsh, AWIN_CCM_OFFSET,
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@ -266,6 +270,7 @@ awinio_attach(device_t parent, device_t self, void *aux)
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.aio_core_bsh = sc->sc_bsh,
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.aio_ccm_bsh = sc->sc_ccm_bsh,
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.aio_a80_usb_bsh = sc->sc_a80_usb_bsh,
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.aio_a80_core2_bsh = sc->sc_a80_core2_bsh,
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.aio_dmat = sc->sc_dmat,
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.aio_coherent_dmat = sc->sc_coherent_dmat,
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};
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@ -2695,6 +2695,12 @@ struct awin_a31_dma_desc {
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#define AWIN_A80_USB2_OFFSET 0x00002000
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#define AWIN_A80_USBPHY_OFFSET 0x00008000
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/*
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* These offsets are relative to AWIN_A80_CORE2_PBASE
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*/
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#define AWIN_A80_SYS_CTRL_OFFSET 0x00000000
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#define AWIN_A80_GMAC_OFFSET 0x00030000
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#define AWIN_A80_SDMMC_COMM_SDC_RESET_SW __BIT(18)
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#define AWIN_A80_SDMMC_COMM_SDC_CLOCK_SW __BIT(16)
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@ -2742,6 +2748,7 @@ struct awin_a31_dma_desc {
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#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING0_SD __BIT(8)
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#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_GMAC __BIT(17)
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#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_USB_HOST __BIT(1)
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#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI4 __BIT(4)
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@ -2752,6 +2759,7 @@ struct awin_a31_dma_desc {
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#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST0_SD __BIT(8)
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#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_GMAC __BIT(17)
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#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_USB_HOST __BIT(1)
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#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI4 __BIT(4)
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@ -2790,7 +2798,13 @@ struct awin_a31_dma_desc {
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#define AWIN_A80_USBPHY_HCI_PCR_480M_GATING_HCI1_HSIC __BIT(2)
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#define AWIN_A80_USBPHY_HCI_PCR_SCLK_GATING_HCI0_PHY __BIT(1)
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#define AWIN_A80_SYS_CTRL_VER_REG 0x0024
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#define AWIN_A80_SYS_CTRL_EMAC_CLK_REG 0x0030
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#define AWIN_A80_SYS_CTRL_DISP_MUX_CTRL_REG 0x0038
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#define AWIN_A80_PIO_PA_PINS 18
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#define AWIN_A80_PIO_PA_GMAC_FUNC 2
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#define AWIN_A80_PIO_PA_GMAC_PINS 0x0003f7bf /* PA pins 17-12,10-7,5-0 */
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#define AWIN_A80_PIO_PB_PINS 20
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#define AWIN_A80_PIO_PB_TWI4_FUNC 4
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@ -1,4 +1,4 @@
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/* $NetBSD: awin_var.h,v 1.30 2014/12/05 17:32:08 jmcneill Exp $ */
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/* $NetBSD: awin_var.h,v 1.31 2014/12/05 18:41:41 jmcneill Exp $ */
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/*-
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -60,6 +60,7 @@ struct awinio_attach_args {
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bus_space_handle_t aio_core_bsh;
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bus_space_handle_t aio_ccm_bsh;
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bus_space_handle_t aio_a80_usb_bsh;
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bus_space_handle_t aio_a80_core2_bsh;
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bus_dma_tag_t aio_dmat;
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bus_dma_tag_t aio_coherent_dmat;
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};
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