- add brdsetup.c left uncomitted over half month.
- fixes on tlp.c; more cautious about TCH/TER/RCH/RER usage and avoid self-pointing TER. - stylize structs and #define order to highlight similarities and differences.
This commit is contained in:
nisimura
parent
f26920b377
commit
ad5b6b45cd
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/* $NetBSD: brdsetup.c,v 1.1 2008/05/30 14:54:16 nisimura Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Tohru Nishimura.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <lib/libsa/stand.h>
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#include <lib/libkern/libkern.h>
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#include "globals.h"
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const unsigned dcache_line_size = 32; /* 32B linesize */
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const unsigned dcache_range_size = 4 * 1024; /* 16KB / 4-way */
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unsigned mpc107memsize(void);
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void setup_82C686B(void);
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void setup_83C553F(void);
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unsigned uartbase;
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#define THR 0
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#define DLB 0
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#define DMB 1
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#define IER 1
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#define FCR 2
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#define LCR 3
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#define MCR 4
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#define LSR 5
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#define DCR 11
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#define LSR_THRE 0x20
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#define UART_READ(r) *(volatile char *)(uartbase + (r))
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#define UART_WRITE(r, v) *(volatile char *)(uartbase + (r)) = (v)
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extern int brdtype;
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void
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brdsetup()
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{
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unsigned pchb, pcib, div;
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/* BAT to arrange address space */
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/* EUMBBAR */
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pchb = pcimaketag(0, 0, 0);
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pcicfgwrite(pchb, 0x78, 0xfc000000);
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brdtype = BRD_UNKNOWN;
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if (pcifinddev(0x10ad, 0x0565, &pcib) == 0) {
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brdtype = BRD_SANDPOINTX3;
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setup_83C553F();
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}
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else if (pcifinddev(0x1106, 0x0686, &pcib) == 0) {
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brdtype = BRD_ENCOREPP1;
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setup_82C686B();
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}
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/* now prepare serial console */
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if (strcmp(CONSNAME, "eumb") != 0)
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uartbase = 0xfe000000 + CONSPORT; /* 0x3f8, 0x2f8 */
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else {
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uartbase = 0xfc000000 + CONSPORT; /* 0x4500, 0x4600 */
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div = (TICKS_PER_SEC * 4) / CONSSPEED / 16;
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UART_WRITE(DCR, 0x01); /* 2 independent UART */
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UART_WRITE(LCR, 0x80); /* turn on DLAB bit */
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UART_WRITE(FCR, 0x00);
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UART_WRITE(DMB, div >> 8);
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UART_WRITE(DLB, div & 0xff); /* 0x36 when 115200bps@100MHz */
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UART_WRITE(LCR, 0x03); /* 8 N 1 */
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UART_WRITE(MCR, 0x03); /* RTS DTR */
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UART_WRITE(FCR, 0x07); /* FIFO_EN | RXSR | TXSR */
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UART_WRITE(IER, 0x00); /* make sure INT disabled */
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}
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}
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void
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putchar(c)
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int c;
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{
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unsigned timo, lsr;
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if (c == '\n')
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putchar('\r');
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timo = 0x00100000;
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do {
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lsr = UART_READ(LSR);
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} while (timo-- > 0 && (lsr & LSR_THRE) == 0);
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if (timo > 0)
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UART_WRITE(THR, c);
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}
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void
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_rtt()
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{
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run(0, 0, 0, 0, (void *)0xFFF00100); /* reset entry */
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/* NOTREACHED */
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}
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static inline u_quad_t
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mftb()
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{
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u_long scratch;
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u_quad_t tb;
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asm ("1: mftbu %0; mftb %0+1; mftbu %1; cmpw %0,%1; bne 1b"
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: "=r"(tb), "=r"(scratch));
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return (tb);
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}
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time_t
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getsecs()
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{
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u_quad_t tb = mftb();
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return (tb / TICKS_PER_SEC);
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}
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/*
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* Wait for about n microseconds (at least!).
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*/
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void
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delay(n)
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u_int n;
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{
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u_quad_t tb;
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u_long tbh, tbl, scratch;
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tb = mftb();
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tb += (n * 1000 + NS_PER_TICK - 1) / NS_PER_TICK;
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tbh = tb >> 32;
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tbl = tb;
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asm volatile ("1: mftbu %0; cmpw %0,%1; blt 1b; bgt 2f; mftb %0; cmpw 0, %0,%2; blt 1b; 2:" : "=&r"(scratch) : "r"(tbh), "r"(tbl));
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}
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void
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_wb(adr, siz)
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uint32_t adr, siz;
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{
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uint32_t bnd;
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asm volatile("eieio");
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for (bnd = adr + siz; adr < bnd; adr += dcache_line_size)
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asm volatile ("dcbst 0,%0" :: "r"(adr));
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asm volatile ("sync");
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}
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void
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_wbinv(adr, siz)
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uint32_t adr, siz;
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{
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uint32_t bnd;
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asm volatile("eieio");
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for (bnd = adr + siz; adr < bnd; adr += dcache_line_size)
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asm volatile ("dcbf 0,%0" :: "r"(adr));
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asm volatile ("sync");
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}
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void
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_inv(adr, siz)
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uint32_t adr, siz;
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{
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uint32_t off, bnd;
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off = adr & (dcache_line_size - 1);
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adr -= off;
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siz += off;
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asm volatile ("eieio");
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if (off != 0) {
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/* wbinv() leading unaligned dcache line */
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asm volatile ("dcbf 0,%0" :: "r"(adr));
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if (siz < dcache_line_size)
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goto done;
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adr += dcache_line_size;
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siz -= dcache_line_size;
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}
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bnd = adr + siz;
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off = bnd & (dcache_line_size - 1);
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if (off != 0) {
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/* wbinv() trailing unaligned dcache line */
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asm volatile ("dcbf 0,%0" :: "r"(bnd)); /* it's OK */
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if (siz < dcache_line_size)
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goto done;
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siz -= off;
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}
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for (bnd = adr + siz; adr < bnd; adr += dcache_line_size) {
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/* inv() intermediate dcache lines if ever */
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asm volatile ("dcbi 0,%0" :: "r"(adr));
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}
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done:
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asm volatile ("sync");
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}
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unsigned
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mpc107memsize()
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{
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unsigned tag, val, n, bankn, end;
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tag = pcimaketag(0, 0, 0);
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if (brdtype == BRD_ENCOREPP1) {
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/* the brd's PPCBOOT looks to have erroneous values */
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unsigned tbl[] = {
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#define MPC106_MEMSTARTADDR1 0x80
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#define MPC106_EXTMEMSTARTADDR1 0x88
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#define MPC106_MEMENDADDR1 0x90
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#define MPC106_EXTMEMENDADDR1 0x98
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#define MPC106_MEMEN 0xa0
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#define BK0_S 0x00000000
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#define BK0_E (128 << 20) - 1
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#define BK1_S 0x3ff00000
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#define BK1_E 0x3fffffff
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#define BK2_S 0x3ff00000
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#define BK2_E 0x3fffffff
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#define BK3_S 0x3ff00000
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#define BK3_E 0x3fffffff
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#define AR(v, s) ((((v) & SAR_MASK) >> SAR_SHIFT) << (s))
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#define XR(v, s) ((((v) & EAR_MASK) >> EAR_SHIFT) << (s))
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#define SAR_MASK 0x0ff00000
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#define SAR_SHIFT 20
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#define EAR_MASK 0x30000000
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#define EAR_SHIFT 28
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AR(BK0_S, 0) | AR(BK1_S, 8) | AR(BK2_S, 16) | AR(BK3_S, 24),
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XR(BK0_S, 0) | XR(BK1_S, 8) | XR(BK2_S, 16) | XR(BK3_S, 24),
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AR(BK0_E, 0) | AR(BK1_E, 8) | AR(BK2_E, 16) | AR(BK3_E, 24),
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XR(BK0_E, 0) | XR(BK1_E, 8) | XR(BK2_E, 16) | XR(BK3_E, 24),
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};
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tag = pcimaketag(0, 0, 0);
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pcicfgwrite(tag, MPC106_MEMSTARTADDR1, tbl[0]);
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pcicfgwrite(tag, MPC106_EXTMEMSTARTADDR1, tbl[1]);
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pcicfgwrite(tag, MPC106_MEMENDADDR1, tbl[2]);
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pcicfgwrite(tag, MPC106_EXTMEMENDADDR1, tbl[3]);
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pcicfgwrite(tag, MPC106_MEMEN, 1);
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}
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bankn = 0;
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val = pcicfgread(tag, MPC106_MEMEN);
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for (n = 0; n < 4; n++) {
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if ((val & (1U << n)) == 0)
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break;
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bankn = n;
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}
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bankn = bankn * 8;
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val = pcicfgread(tag, MPC106_EXTMEMENDADDR1);
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end = ((val >> bankn) & 0x03) << 28;
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val = pcicfgread(tag, MPC106_MEMENDADDR1);
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end |= ((val >> bankn) & 0xff) << 20;
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end |= 0xfffff;
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return (end + 1); /* size of bankN SDRAM */
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}
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/*
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* VIA82C686B Southbridge
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* 0.22.0 1106.0686 PCI-ISA bridge
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* 0.22.1 1106.0571 IDE (viaide)
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* 0.22.2 1106.3038 USB 0/1 (uhci)
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* 0.22.3 1106.3038 USB 2/3 (uhci)
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* 0.22.4 1106.3057 power management
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* 0.22.5 1106.3058 AC97 (auvia)
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*/
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void
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setup_82C686B()
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{
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unsigned pcib, ide, usb12, usb34, ac97, pmgt, val;
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pcib = pcimaketag(0, 22, 0);
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ide = pcimaketag(0, 22, 1);
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usb12 = pcimaketag(0, 22, 2);
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usb34 = pcimaketag(0, 22, 3);
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pmgt = pcimaketag(0, 22, 4);
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ac97 = pcimaketag(0, 22, 5);
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#define CFG(i,v) do { \
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*(volatile unsigned char *)(0xfe000000 + 0x3f0) = (i); \
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*(volatile unsigned char *)(0xfe000000 + 0x3f1) = (v); \
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} while (0)
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val = pcicfgread(pcib, 0x84);
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val |= (02 << 8);
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pcicfgwrite(pcib, 0x84, val);
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CFG(0xe2, 0x0f); /* use COM1/2, don't use FDC/LPT */
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val = pcicfgread(pcib, 0x84);
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val &= ~(02 << 8);
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pcicfgwrite(pcib, 0x84, val);
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/* route pin C to i8259 IRQ 5, pin D to 11 */
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val = pcicfgread(pcib, 0x54);
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val = (val & 0xff) | 0xb0500000; /* Dx CB Ax xS */
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pcicfgwrite(pcib, 0x54, val);
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/* enable EISA ELCR1 (0x4d0) and ELCR2 (0x4d1) */
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val = pcicfgread(pcib, 0x44);
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val = val | 0x20000000;
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pcicfgwrite(pcib, 0x44, val);
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/* select level trigger for IRQ 5/11 at ELCR1/2 */
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*(volatile uint8_t *)0xfe0004d0 = 0x20; /* bit 5 */
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*(volatile uint8_t *)0xfe0004d1 = 0x08; /* bit 11 */
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/* USB and AC97 are hardwired with pin D and C */
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val = pcicfgread(usb12, 0x3c) &~ 0xff;
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val |= 11;
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pcicfgwrite(usb12, 0x3c, val);
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val = pcicfgread(usb34, 0x3c) &~ 0xff;
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val |= 11;
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pcicfgwrite(usb34, 0x3c, val);
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val = pcicfgread(ac97, 0x3c) &~ 0xff;
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val |= 5;
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pcicfgwrite(ac97, 0x3c, val);
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}
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/*
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* WinBond/Symphony Lab 83C553 with PC87308 "SuperIO"
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*
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* 0.11.0 10ad.0565 PCI-ISA bridge
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* 0.11.1 10ad.0105 IDE (slide)
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*/
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void
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setup_83C553F()
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{
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#if 0
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unsigned pcib, ide, val;
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pcib = pcimaketag(0, 11, 0);
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ide = pcimaketag(0, 11, 1);
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#endif
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}
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void
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pcifixup()
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{
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unsigned pcib, ide, nic, val, steer, irq;
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int line;
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switch (brdtype) {
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case BRD_SANDPOINTX3:
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pcib = pcimaketag(0, 11, 0);
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ide = pcimaketag(0, 11, 1);
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nic = pcimaketag(0, 15, 0);
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/*
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* //// WinBond PIRQ ////
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* 0x40 - bit 5 (0x20) indicates PIRQ presense
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* 0x60 - PIRQ interrupt routing steer
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*/
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if (pcicfgread(pcib, 0x40) & 0x20) {
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steer = pcicfgread(pcib, 0x60);
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if ((steer & 0x80808080) == 0x80808080)
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printf("PIRQ[0-3] disabled\n");
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else {
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unsigned i, v = steer;
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for (i = 0; i < 4; i++, v >>= 8) {
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if ((v & 0x80) != 0 || (v & 0xf) == 0)
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continue;
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printf("PIRQ[%d]=%d\n", i, v & 0xf);
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}
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}
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}
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#if 1
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/*
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* //// IDE fixup -- case A ////
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* - "native PCI mode" (ide 0x09)
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* - don't use ISA IRQ14/15 (pcib 0x43)
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* - native IDE for both channels (ide 0x40)
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* - LEGIRQ bit 11 steers interrupt to pin C (ide 0x40)
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* - sign as PCI pin C line 11 (ide 0x3d/3c)
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*/
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/* ide: 0x09 - programming interface; 1000'SsPp */
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val = pcicfgread(ide, 0x08);
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val &= 0xffff00ff;
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pcicfgwrite(ide, 0x08, val | (0x8f << 8));
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/* pcib: 0x43 - IDE interrupt routing */
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val = pcicfgread(pcib, 0x40) & 0x00ffffff;
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pcicfgwrite(pcib, 0x40, val);
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/* pcib: 0x45/44 - PCI interrupt routing */
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val = pcicfgread(pcib, 0x44) & 0xffff0000;
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pcicfgwrite(pcib, 0x44, val);
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/* ide: 0x41/40 - IDE channel */
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val = pcicfgread(ide, 0x40) & 0xffff0000;
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val |= (1 << 11) | 0x33; /* LEGIRQ turns on PCI interrupt */
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pcicfgwrite(ide, 0x40, val);
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/* ide: 0x3d/3c - use PCI pin C/line 11 */
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val = pcicfgread(ide, 0x3c) & 0xffffff00;
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val |= 11; /* pin designation is hardwired to pin A */
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pcicfgwrite(ide, 0x3c, val);
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#else
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/*
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* //// IDE fixup -- case B ////
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* - "compatiblity mode" (ide 0x09)
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* - IDE primary/secondary interrupt routing (pcib 0x43)
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* - PCI interrupt routing (pcib 0x45/44)
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* - no PCI pin/line assignment (ide 0x3d/3c)
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*/
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/* ide: 0x09 - programming interface; 1000'SsPp */
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val = pcicfgread(ide, 0x08);
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val &= 0xffff00ff;
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pcicfgwrite(ide, 0x08, val | (0x8a << 8));
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/* pcib: 0x43 - IDE interrupt routing */
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val = pcicfgread(pcib, 0x40) & 0x00ffffff;
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pcicfgwrite(pcib, 0x40, val | (0xee << 24));
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/* ide: 0x45/44 - PCI interrupt routing */
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val = pcicfgread(ide, 0x44) & 0xffff0000;
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pcicfgwrite(ide, 0x44, val);
|
||||
|
||||
/* ide: 0x3d/3c - turn off PCI pin/line */
|
||||
val = pcicfgread(ide, 0x3c) & 0xffff0000;
|
||||
pcicfgwrite(ide, 0x3c, val);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* //// fxp fixup ////
|
||||
* - use PCI pin A line 15 (fxp 0x3d/3c)
|
||||
*/
|
||||
val = pcicfgread(nic, 0x3c) & 0xffff0000;
|
||||
pcidecomposetag(nic, NULL, &line, NULL);
|
||||
val |= (('A' - '@') << 8) | line;
|
||||
pcicfgwrite(nic, 0x3c, val);
|
||||
break;
|
||||
|
||||
case BRD_ENCOREPP1:
|
||||
#define STEER(v, b) (((v) & (b)) ? "edge" : "level")
|
||||
|
||||
pcib = pcimaketag(0, 22, 0);
|
||||
ide = pcimaketag(0, 22, 1);
|
||||
nic = pcimaketag(0, 25, 0);
|
||||
|
||||
/*
|
||||
* //// VIA PIRQ ////
|
||||
* 0x57/56/55/54 - Dx CB Ax xS
|
||||
*/
|
||||
val = pcicfgread(pcib, 0x54); /* Dx CB Ax xs */
|
||||
steer = val & 0xf;
|
||||
irq = (val >> 12) & 0xf; /* 15:12 */
|
||||
if (irq) {
|
||||
printf("pin A -> irq %d, %s\n",
|
||||
irq, STEER(steer, 0x1));
|
||||
}
|
||||
irq = (val >> 16) & 0xf; /* 19:16 */
|
||||
if (irq) {
|
||||
printf("pin B -> irq %d, %s\n",
|
||||
irq, STEER(steer, 0x2));
|
||||
}
|
||||
irq = (val >> 20) & 0xf; /* 23:20 */
|
||||
if (irq) {
|
||||
printf("pin C -> irq %d, %s\n",
|
||||
irq, STEER(steer, 0x4));
|
||||
}
|
||||
irq = (val >> 28); /* 31:28 */
|
||||
if (irq) {
|
||||
printf("pin D -> irq %d, %s\n",
|
||||
irq, STEER(steer, 0x8));
|
||||
}
|
||||
#if 0
|
||||
/*
|
||||
* //// IDE fixup ////
|
||||
* - "native mode" (ide 0x09)
|
||||
* - use primary only (ide 0x40)
|
||||
*/
|
||||
/* ide: 0x09 - programming interface; 1000'SsPp */
|
||||
val = pcicfgread(ide, 0x08) & 0xffff00ff;
|
||||
pcicfgwrite(ide, 0x08, val | (0x8f << 8));
|
||||
|
||||
/* ide: 0x10-20 - leave them PCI memory space assigned */
|
||||
|
||||
/* ide: 0x40 - use primary only */
|
||||
val = pcicfgread(ide, 0x40) &~ 03;
|
||||
val |= 02;
|
||||
pcicfgwrite(ide, 0x40, val);
|
||||
#else
|
||||
/*
|
||||
* //// IDE fixup ////
|
||||
* - "compatiblity mode" (ide 0x09)
|
||||
* - use primary only (ide 0x40)
|
||||
* - remove PCI pin assignment (ide 0x3d)
|
||||
*/
|
||||
/* ide: 0x09 - programming interface; 1000'SsPp */
|
||||
val = pcicfgread(ide, 0x08) & 0xffff00ff;
|
||||
val |= (0x8a << 8);
|
||||
pcicfgwrite(ide, 0x08, val);
|
||||
|
||||
/* ide: 0x10-20 */
|
||||
/*
|
||||
experiment shows writing ide: 0x09 changes these
|
||||
register behaviour. The pcicfgwrite() above writes
|
||||
0x8a at ide: 0x09 to make sure legacy IDE. Then
|
||||
reading BAR0-3 is to return value 0s even though
|
||||
pcisetup() has written range assignments. Value
|
||||
overwrite makes no effect. Having 0x8f for native
|
||||
PCIIDE doesn't change register values and brings no
|
||||
weirdness.
|
||||
*/
|
||||
|
||||
/* ide: 0x40 - use primary only */
|
||||
val = pcicfgread(ide, 0x40) &~ 03;
|
||||
val |= 02;
|
||||
pcicfgwrite(ide, 0x40, val);
|
||||
|
||||
/* ide: 0x3d/3c - turn off PCI pin */
|
||||
val = pcicfgread(ide, 0x3c) & 0xffff00ff;
|
||||
pcicfgwrite(ide, 0x3c, val);
|
||||
#endif
|
||||
/*
|
||||
* //// USBx2, audio, and modem fixup ////
|
||||
* - disable USB #0 and #1 (pcib 0x48 and 0x85)
|
||||
* - disable AC97 audio and MC97 modem (pcib 0x85)
|
||||
*/
|
||||
|
||||
/* pcib: 0x48 - disable USB #0 at function 2 */
|
||||
val = pcicfgread(pcib, 0x48);
|
||||
pcicfgwrite(pcib, 0x48, val | 04);
|
||||
|
||||
/* pcib: 0x85 - disable USB #1 at function 3 */
|
||||
/* pcib: 0x85 - disable AC97/MC97 at function 5/6 */
|
||||
val = pcicfgread(pcib, 0x84);
|
||||
pcicfgwrite(pcib, 0x84, val | 0x1c00);
|
||||
|
||||
/*
|
||||
* //// fxp fixup ////
|
||||
* - use PCI pin A line 25 (fxp 0x3d/3c)
|
||||
*/
|
||||
/* 0x3d/3c - PCI pin/line */
|
||||
val = pcicfgread(nic, 0x3c) & 0xffff0000;
|
||||
val |= (('A' - '@') << 8) | 25;
|
||||
pcicfgwrite(nic, 0x3c, val);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: nvt.c,v 1.14 2008/05/14 23:14:11 nisimura Exp $ */
|
||||
/* $NetBSD: nvt.c,v 1.15 2008/05/30 14:54:16 nisimura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2007 The NetBSD Foundation, Inc.
|
||||
|
|
@ -62,6 +62,25 @@ void *nvt_init(unsigned, void *);
|
|||
int nvt_send(void *, char *, unsigned);
|
||||
int nvt_recv(void *, char *, unsigned, unsigned);
|
||||
|
||||
struct desc {
|
||||
uint32_t xd0, xd1, xd2, xd3;
|
||||
};
|
||||
#define T0_OWN (1U << 31) /* 1: loaded for HW to send */
|
||||
#define T0_TERR (1U << 15) /* Tx error; ABT|CBH */
|
||||
#define T0_UDF (1U << 11) /* FIFO underflow */
|
||||
#define T0_CRS (1U << 10) /* found carrier sense lost */
|
||||
#define T0_OWC (1U << 9) /* found out of window collision */
|
||||
#define T0_ABT (1U << 8) /* excess collision Tx abort */
|
||||
#define T0_CBH (1U << 7) /* heartbeat check failure */
|
||||
#define T0_COLS (1U << 4) /* collision detected */
|
||||
#define T0_NCRMASK 0x3 /* number of collision retries */
|
||||
#define T1_IC (1U << 23) /* post Tx done interrupt */
|
||||
#define T1_STP (1U << 22) /* first frame segment */
|
||||
#define T1_EDP (1U << 21) /* last frame segment */
|
||||
#define T1_CRC (1U << 16) /* _disable_ CRC generation */
|
||||
#define T1_CHN (1U << 15) /* "more bit," not the last seg. */
|
||||
#define T_FLMASK 0x00007fff /* Tx frame/segment length */
|
||||
|
||||
#define R0_OWN (1U << 31) /* 1: empty for HW to load anew */
|
||||
#define R0_FLMASK 0x7fff0000 /* frame length */
|
||||
#define R0_RXOK (1U << 15)
|
||||
|
|
@ -80,26 +99,6 @@ int nvt_recv(void *, char *, unsigned, unsigned);
|
|||
#define R0_RERR (1U << 0) /* Rx error summary */
|
||||
#define R1_FLMASK 0x00007ffc /* Rx segment buffer length */
|
||||
|
||||
#define T0_OWN (1U << 31) /* 1: loaded for HW to send */
|
||||
#define T0_TERR (1U << 15) /* Tx error; ABT|CBH */
|
||||
#define T0_UDF (1U << 11) /* FIFO underflow */
|
||||
#define T0_CRS (1U << 10) /* found carrier sense lost */
|
||||
#define T0_OWC (1U << 9) /* found out of window collision */
|
||||
#define T0_ABT (1U << 8) /* excess collision Tx abort */
|
||||
#define T0_CBH (1U << 7) /* heartbeat check failure */
|
||||
#define T0_COLS (1U << 4) /* collision detected */
|
||||
#define T0_NCRMASK 0x3 /* number of collision retries */
|
||||
#define T1_IC (1U << 23) /* post Tx done interrupt */
|
||||
#define T1_STP (1U << 22) /* first frame segment */
|
||||
#define T1_EDP (1U << 21) /* last frame segment */
|
||||
#define T1_CRC (1U << 16) /* _disable_ CRC generation */
|
||||
#define T1_CHN (1U << 15) /* "more bit," not the last seg. */
|
||||
#define T_FLMASK 0x00007fff /* Tx frame/segment length */
|
||||
|
||||
struct desc {
|
||||
uint32_t xd0, xd1, xd2, xd3;
|
||||
};
|
||||
|
||||
#define VR_PAR0 0x00 /* SA [0] */
|
||||
#define VR_PAR1 0x01 /* SA [1] */
|
||||
#define VR_PAR2 0x02 /* SA [2] */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pcn.c,v 1.13 2008/05/14 23:14:11 nisimura Exp $ */
|
||||
/* $NetBSD: pcn.c,v 1.14 2008/05/30 14:54:16 nisimura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2007 The NetBSD Foundation, Inc.
|
||||
|
|
@ -60,6 +60,10 @@ void *pcn_init(unsigned, void *);
|
|||
int pcn_send(void *, char *, unsigned);
|
||||
int pcn_recv(void *, char *, unsigned, unsigned);
|
||||
|
||||
struct desc {
|
||||
uint32_t xd0, xd1, xd2;
|
||||
uint32_t hole;
|
||||
};
|
||||
#define T1_OWN (1U << 31) /* 1: empty for HW to load anew */
|
||||
#define T1_STP (1U << 25) /* first frame segment */
|
||||
#define T1_ENP (1U << 24) /* last frame segment */
|
||||
|
|
@ -70,11 +74,6 @@ int pcn_recv(void *, char *, unsigned, unsigned);
|
|||
#define R1_ONES 0xf000 /* filler */
|
||||
#define R1_FLMASK 0x0fff /* Rx frame length */
|
||||
|
||||
struct desc {
|
||||
uint32_t xd0, xd1, xd2;
|
||||
uint32_t hole;
|
||||
};
|
||||
|
||||
#define PCN_RDP 0x10
|
||||
#define PCN_RAP 0x12
|
||||
#define PCN_16RESET 0x14
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: rge.c,v 1.12 2008/05/14 23:14:11 nisimura Exp $ */
|
||||
/* $NetBSD: rge.c,v 1.13 2008/05/30 14:54:16 nisimura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2007 The NetBSD Foundation, Inc.
|
||||
|
|
@ -61,6 +61,9 @@ void *rge_init(unsigned, void *);
|
|||
int rge_send(void *, char *, unsigned);
|
||||
int rge_recv(void *, char *, unsigned, unsigned);
|
||||
|
||||
struct desc {
|
||||
uint32_t xd0, xd1, xd2, xd3;
|
||||
};
|
||||
#define T0_OWN 0x80000000 /* loaded for HW to send */
|
||||
#define T0_EOR 0x40000000 /* end of ring */
|
||||
#define T0_FS 0x20000000 /* first descriptor */
|
||||
|
|
@ -90,10 +93,6 @@ int rge_recv(void *, char *, unsigned, unsigned);
|
|||
#define R1_TAVA 0x00010000 /* VTAG exists */
|
||||
#define R1_VTAG 0x0000ffff /* TAG value */
|
||||
|
||||
struct desc {
|
||||
uint32_t xd0, xd1, xd2, xd3;
|
||||
};
|
||||
|
||||
#define RGE_IDR0 0x00 /* MAC address [0] */
|
||||
#define RGE_IDR1 0x01 /* MAC address [1] */
|
||||
#define RGE_IDR2 0x02 /* MAC address [2] */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: sip.c,v 1.14 2008/05/14 23:14:11 nisimura Exp $ */
|
||||
/* $NetBSD: sip.c,v 1.15 2008/05/30 14:54:16 nisimura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2007 The NetBSD Foundation, Inc.
|
||||
|
|
@ -58,13 +58,12 @@ void *sip_init(unsigned, void *);
|
|||
int sip_send(void *, char *, unsigned);
|
||||
int sip_recv(void *, char *, unsigned, unsigned);
|
||||
|
||||
#define XD1_OWN (1U << 31)
|
||||
#define XD1_OK (1U << 27)
|
||||
|
||||
struct desc {
|
||||
uint32_t xd0, xd1, xd2;
|
||||
uint32_t hole;
|
||||
};
|
||||
#define XD1_OWN (1U << 31)
|
||||
#define XD1_OK (1U << 27)
|
||||
|
||||
#define SIP_CR 0x00
|
||||
#define CR_RST (1U << 8) /* software reset */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: tlp.c,v 1.18 2008/05/14 23:14:11 nisimura Exp $ */
|
||||
/* $NetBSD: tlp.c,v 1.19 2008/05/30 14:54:16 nisimura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2007 The NetBSD Foundation, Inc.
|
||||
|
|
@ -57,25 +57,26 @@ void *tlp_init(unsigned, void *);
|
|||
int tlp_send(void *, char *, unsigned);
|
||||
int tlp_recv(void *, char *, unsigned, unsigned);
|
||||
|
||||
struct desc {
|
||||
uint32_t xd0, xd1, xd2, xd3;
|
||||
};
|
||||
#define T0_OWN (1U<<31) /* desc is ready to tx */
|
||||
#define T0_ES (1U<<15) /* Tx error summary */
|
||||
#define T1_LS (1U<<30) /* last segment */
|
||||
#define T1_FS (1U<<29) /* first segment */
|
||||
#define T1_SET (1U<<27) /* "setup packet" */
|
||||
#define T1_TER (1U<<25) /* end of ring mark */
|
||||
#define T1_TCH (1U<<24) /* TDES3 points the next desc */
|
||||
#define T1_TBS_MASK 0x7ff /* segment size 10:0 */
|
||||
#define R0_OWN (1U<<31) /* desc is empty */
|
||||
#define R0_FS (1U<<30) /* first desc of frame */
|
||||
#define R0_LS (1U<<8) /* last desc of frame */
|
||||
#define R0_ES (1U<<15) /* Rx error summary */
|
||||
#define R1_RER (1U<<25) /* end of ring mark */
|
||||
#define R1_RCH (1U<<24) /* RDES3 points the next desc */
|
||||
#define R0_FLMASK 0x3fff0000 /* frame length 29:16 */
|
||||
#define R1_RBS_MASK 0x7ff /* segment size 10:0 */
|
||||
|
||||
struct desc {
|
||||
uint32_t xd0, xd1, xd2, xd3;
|
||||
};
|
||||
|
||||
#define TLP_BMR 0x00 /* 0: bus mode */
|
||||
#define BMR_RST 01
|
||||
#define BMR_CAL8 0x00004000 /* 32B cache alignment */
|
||||
|
|
@ -186,20 +187,20 @@ tlp_init(unsigned tag, void *data)
|
|||
txd = &l->txd;
|
||||
rxd = &l->rxd[0];
|
||||
rxd[0].xd0 = htole32(R0_OWN);
|
||||
rxd[0].xd1 = htole32(FRAMESIZE);
|
||||
rxd[0].xd1 = htole32(R1_RCH | FRAMESIZE);
|
||||
rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0]));
|
||||
rxd[0].xd3 = htole32(VTOPHYS(&rxd[1]));
|
||||
rxd[1].xd0 = htole32(R0_OWN);
|
||||
rxd[1].xd1 = htole32(R1_RER | FRAMESIZE);
|
||||
rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1]));
|
||||
rxd[1].xd3 = htole32(VTOPHYS(&rxd[0]));
|
||||
/* R1_RER neglects xd3 */
|
||||
l->rx = 0;
|
||||
|
||||
/* "setup frame" to have own station address */
|
||||
txd = &l->txd;
|
||||
txd->xd3 = htole32(VTOPHYS(txd));
|
||||
txd->xd2 = htole32(VTOPHYS(l->txstore));
|
||||
txd->xd1 = htole32(T1_SET | T1_TER | sizeof(l->txstore));
|
||||
txd->xd1 = htole32(T1_SET | sizeof(l->txstore));
|
||||
txd->xd0 = htole32(T0_OWN);
|
||||
p = (uint32_t *)l->txstore;
|
||||
p[0] = htole32(en[1] << 8 | en[0]);
|
||||
|
|
@ -229,19 +230,20 @@ tlp_send(void *dev, char *buf, unsigned len)
|
|||
{
|
||||
struct local *l = dev;
|
||||
volatile struct desc *txd;
|
||||
unsigned loop;
|
||||
unsigned txstat, loop;
|
||||
|
||||
/* send a single frame with no T1_TER|T1_TCH designation */
|
||||
wbinv(buf, len);
|
||||
txd = &l->txd;
|
||||
txd->xd3 = htole32(VTOPHYS(txd));
|
||||
txd->xd2 = htole32(VTOPHYS(buf));
|
||||
txd->xd1 = htole32(T1_FS | T1_LS | T1_TER | (len & T1_TBS_MASK));
|
||||
txd->xd1 = htole32(T1_FS | T1_LS | (len & T1_TBS_MASK));
|
||||
txd->xd0 = htole32(T0_OWN);
|
||||
wbinv(txd, sizeof(struct desc));
|
||||
CSR_WRITE(l, TLP_TPD, 01);
|
||||
loop = 100;
|
||||
do {
|
||||
if ((le32toh(txd->xd0) & T0_OWN) == 0)
|
||||
txstat = le32toh(txd->xd0);
|
||||
if ((txstat & T0_OWN) == 0)
|
||||
goto done;
|
||||
DELAY(10);
|
||||
inv(txd, sizeof(struct desc));
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: vge.c,v 1.15 2008/05/14 23:14:12 nisimura Exp $ */
|
||||
/* $NetBSD: vge.c,v 1.16 2008/05/30 14:54:16 nisimura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2007 The NetBSD Foundation, Inc.
|
||||
|
|
@ -62,33 +62,16 @@ void *vge_init(unsigned, void *);
|
|||
int vge_send(void *, char *, unsigned);
|
||||
int vge_recv(void *, char *, unsigned, unsigned);
|
||||
|
||||
#define R0_OWN (1U << 31) /* 1: empty for HW to load anew */
|
||||
#define R0_FLMASK 0x3fff0000 /* frame length */
|
||||
#define R0_RXOK (1U << 15)
|
||||
#define R0_MAR (1U << 13) /* multicast frame */
|
||||
#define R0_BAR (1U << 12) /* broadcast frame */
|
||||
#define R0_PHY (1U << 11) /* unicast frame */
|
||||
#define R0_VTAG (1U << 10) /* VTAG indicator */
|
||||
#define R0_STP (1U << 9) /* first frame segment */
|
||||
#define R0_EDP (1U << 8) /* last frame segment */
|
||||
#define R0_DETAG (1U << 7) /* VTAG has removed */
|
||||
#define R0_SNTAG (1U << 6) /* tagged SNAP frame */
|
||||
#define R0_SYME (1U << 5) /* symbol error */
|
||||
#define R0_LENE (1U << 4) /* frame length error */
|
||||
#define R0_CSUME (1U << 3) /* TCP/IP bad csum */
|
||||
#define R0_FAE (1U << 2) /* frame alignment error */
|
||||
#define R0_CRCE (1U << 1) /* CRC error */
|
||||
#define R0_VIDM (1U << 0) /* VTAG filter miss */
|
||||
#define R1_IPOK (1U << 22) /* IP csum was fine */
|
||||
#define R1_TUPOK (1U << 21) /* TCP/UDP csum was fine */
|
||||
#define R1_FRAG (1U << 20) /* fragmented IP */
|
||||
#define R1_CKSMZO (1U << 19) /* UDP csum field was zero */
|
||||
#define R1_IPKT (1U << 18) /* frame was IPv4 */
|
||||
#define R1_TPKT (1U << 17) /* frame was TCPv4 */
|
||||
#define R1_UPKT (1U << 16) /* frame was UDPv4 */
|
||||
#define R3_IC (1U << 31) /* post Rx interrupt */
|
||||
#define R_FLMASK 0x00003ffd /* Rx segment buffer length */
|
||||
|
||||
struct tdesc {
|
||||
uint32_t t0, t1;
|
||||
struct {
|
||||
uint32_t lo;
|
||||
uint32_t hi;
|
||||
} tf[7];
|
||||
};
|
||||
struct rdesc {
|
||||
uint32_t r0, r1, r2, r3;
|
||||
};
|
||||
#define T0_OWN (1U << 31) /* 1: loaded for HW to send */
|
||||
#define T0_TERR (1U << 15) /* Tx error summary */
|
||||
#define T0_UDF (1U << 12) /* found link down when Tx */
|
||||
|
|
@ -116,17 +99,32 @@ int vge_recv(void *, char *, unsigned, unsigned);
|
|||
#define T_FLMASK 0x00003fff /* Tx frame/segment length */
|
||||
#define TF0_Q (1U << 31) /* "Q" bit of tf[0].hi */
|
||||
|
||||
struct tdesc {
|
||||
uint32_t t0, t1;
|
||||
struct {
|
||||
uint32_t lo;
|
||||
uint32_t hi;
|
||||
} tf[7];
|
||||
};
|
||||
|
||||
struct rdesc {
|
||||
uint32_t r0, r1, r2, r3;
|
||||
};
|
||||
#define R0_OWN (1U << 31) /* 1: empty for HW to load anew */
|
||||
#define R0_FLMASK 0x3fff0000 /* frame length */
|
||||
#define R0_RXOK (1U << 15)
|
||||
#define R0_MAR (1U << 13) /* multicast frame */
|
||||
#define R0_BAR (1U << 12) /* broadcast frame */
|
||||
#define R0_PHY (1U << 11) /* unicast frame */
|
||||
#define R0_VTAG (1U << 10) /* VTAG indicator */
|
||||
#define R0_STP (1U << 9) /* first frame segment */
|
||||
#define R0_EDP (1U << 8) /* last frame segment */
|
||||
#define R0_DETAG (1U << 7) /* VTAG has removed */
|
||||
#define R0_SNTAG (1U << 6) /* tagged SNAP frame */
|
||||
#define R0_SYME (1U << 5) /* symbol error */
|
||||
#define R0_LENE (1U << 4) /* frame length error */
|
||||
#define R0_CSUME (1U << 3) /* TCP/IP bad csum */
|
||||
#define R0_FAE (1U << 2) /* frame alignment error */
|
||||
#define R0_CRCE (1U << 1) /* CRC error */
|
||||
#define R0_VIDM (1U << 0) /* VTAG filter miss */
|
||||
#define R1_IPOK (1U << 22) /* IP csum was fine */
|
||||
#define R1_TUPOK (1U << 21) /* TCP/UDP csum was fine */
|
||||
#define R1_FRAG (1U << 20) /* fragmented IP */
|
||||
#define R1_CKSMZO (1U << 19) /* UDP csum field was zero */
|
||||
#define R1_IPKT (1U << 18) /* frame was IPv4 */
|
||||
#define R1_TPKT (1U << 17) /* frame was TCPv4 */
|
||||
#define R1_UPKT (1U << 16) /* frame was UDPv4 */
|
||||
#define R3_IC (1U << 31) /* post Rx interrupt */
|
||||
#define R_FLMASK 0x00003ffd /* Rx segment buffer length */
|
||||
|
||||
#define VR_PAR0 0x00 /* SA [0] */
|
||||
#define VR_PAR1 0x01 /* SA [1] */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: wm.c,v 1.7 2008/05/14 23:14:12 nisimura Exp $ */
|
||||
/* $NetBSD: wm.c,v 1.8 2008/05/30 14:54:16 nisimura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2007 The NetBSD Foundation, Inc.
|
||||
|
|
@ -60,18 +60,33 @@ void *wm_init(unsigned, void *);
|
|||
int wm_send(void *, char *, unsigned);
|
||||
int wm_recv(void *, char *, unsigned, unsigned);
|
||||
|
||||
struct rdesc {
|
||||
uint32_t lo; /* 31:0 */
|
||||
uint32_t hi; /* 63:32 */
|
||||
uint32_t r2; /* 31:16 checksum, 15:0 Rx frame length */
|
||||
uint32_t r3; /* 31:16 special, 15:8 errors, 7:0 status */
|
||||
};
|
||||
struct tdesc {
|
||||
uint32_t lo; /* 31:0 */
|
||||
uint32_t hi; /* 63:32 */
|
||||
uint32_t t2; /* 31:16 command, 15:0 Tx frame length */
|
||||
uint32_t t3; /* 31:16 VTAG, 15:8 opt, 7:0 Tx status */
|
||||
};
|
||||
struct rdesc {
|
||||
uint32_t lo; /* 31:0 */
|
||||
uint32_t hi; /* 63:32 */
|
||||
uint32_t r2; /* 31:16 checksum, 15:0 Rx frame length */
|
||||
uint32_t r3; /* 31:16 special, 15:8 errors, 7:0 status */
|
||||
};
|
||||
/* T2 command */
|
||||
#define T2_FLMASK 0xffff /* 15:0 */
|
||||
#define T2_DTYP_C (1U << 20) /* data descriptor */
|
||||
#define T2_EOP (1U << 24) /* end of packet */
|
||||
#define T2_IFCS (1U << 25) /* insert FCS */
|
||||
#define T2_RS (1U << 27) /* report status */
|
||||
#define T2_RPS (1U << 28) /* report packet sent */
|
||||
#define T2_DEXT (1U << 29) /* descriptor extention */
|
||||
#define T2_VLE (1U << 30) /* VLAN enable */
|
||||
#define T2_IDE (1U << 31) /* interrupt delay enable */
|
||||
/* T3 status */
|
||||
#define T3_DD (1U << 0) /* 1: Tx has done and vacant */
|
||||
/* T3 option */
|
||||
#define T3_IXSM (1U << 16) /* generate IP csum */
|
||||
#define T3_TXSM (1U << 17) /* generate TCP/UDP csum */
|
||||
|
||||
#define R2_FLMASK 0xffff /* 15:0 */
|
||||
/* R3 status */
|
||||
|
|
@ -91,22 +106,6 @@ struct tdesc {
|
|||
#define R3_IPE (1U << 14) /* IP csum error found */
|
||||
#define R3_RXE (1U << 15) /* Rx data error */
|
||||
|
||||
/* T2 command */
|
||||
#define T2_FLMASK 0xffff /* 15:0 */
|
||||
#define T2_DTYP_C (1U << 20) /* data descriptor */
|
||||
#define T2_EOP (1U << 24) /* end of packet */
|
||||
#define T2_IFCS (1U << 25) /* insert FCS */
|
||||
#define T2_RS (1U << 27) /* report status */
|
||||
#define T2_RPS (1U << 28) /* report packet sent */
|
||||
#define T2_DEXT (1U << 29) /* descriptor extention */
|
||||
#define T2_VLE (1U << 30) /* VLAN enable */
|
||||
#define T2_IDE (1U << 31) /* interrupt delay enable */
|
||||
/* T3 status */
|
||||
#define T3_DD (1U << 0) /* 1: Tx has done and vacant */
|
||||
/* T3 option */
|
||||
#define T3_IXSM (1U << 16) /* generate IP csum */
|
||||
#define T3_TXSM (1U << 17) /* generate TCP/UDP csum */
|
||||
|
||||
#define FRAMESIZE 1536
|
||||
|
||||
struct local {
|
||||
|
|
|
|||
Loading…
Reference in New Issue