more usb phy / clk init
This commit is contained in:
jmcneill
parent
c7663cfa5a
commit
acbde51a8a
@ -1,4 +1,4 @@
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/* $NetBSD: amlogic_board.c,v 1.3 2015/02/28 15:20:43 jmcneill Exp $ */
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/* $NetBSD: amlogic_board.c,v 1.4 2015/02/28 18:50:57 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -29,7 +29,7 @@
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#include "opt_amlogic.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.3 2015/02/28 15:20:43 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.4 2015/02/28 18:50:57 jmcneill Exp $");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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@ -59,7 +59,7 @@ struct arm32_bus_dma_tag amlogic_dma_tag = {
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AMLOGIC_CBUS_OFFSET + (x))
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#define CBUS_WRITE(x, v) \
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bus_space_write_4(&amlogic_bs_tag, amlogic_core_bsh, \
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AMLOGIC_CBUS_OFFSET + (x), (v))
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AMLOGIC_CBUS_OFFSET + (x), (v))
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void
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amlogic_bootstrap(void)
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@ -157,15 +157,40 @@ amlogic_get_rate_a9periph(void)
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return amlogic_get_rate_a9() / div;
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}
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static void
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amlogic_usbphy_clkgate_enable(int port)
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{
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switch (port) {
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case 0:
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CBUS_WRITE(EE_CLK_GATING1_REG,
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CBUS_READ(EE_CLK_GATING1_REG) |
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EE_CLK_GATING1_USB_GENERAL |
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EE_CLK_GATING1_USB0);
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CBUS_WRITE(EE_CLK_GATING2_REG,
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CBUS_READ(EE_CLK_GATING2_REG) |
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EE_CLK_GATING2_USB0_TO_DDR);
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break;
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case 1:
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CBUS_WRITE(EE_CLK_GATING1_REG,
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CBUS_READ(EE_CLK_GATING1_REG) |
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EE_CLK_GATING1_USB_GENERAL |
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EE_CLK_GATING1_USB1);
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CBUS_WRITE(EE_CLK_GATING2_REG,
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CBUS_READ(EE_CLK_GATING2_REG) |
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EE_CLK_GATING2_USB1_TO_DDR);
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break;
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}
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}
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void
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amlogic_usbphy_init(int port)
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{
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bus_space_tag_t bst = &amlogic_bs_tag;
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bus_space_handle_t bsh = amlogic_core_bsh;
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bus_size_t ctrl_reg, cfg_reg, gpioao_reg;
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uint32_t ctrl, cfg, gpioao;
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bus_size_t ctrl_reg, cfg_reg, adp_bc_reg, gpioao_reg;
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uint32_t ctrl, cfg, adp_bc, gpioao;
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u_int pin, pol;
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bool gpio_power = false, gpio_reset = false;
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bool gpio_power = false, gpio_reset = false, aca_enable = false;
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gpioao_reg = AMLOGIC_GPIOAO_OFFSET;
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@ -173,6 +198,7 @@ amlogic_usbphy_init(int port)
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case 0:
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cfg_reg = PREI_USB_PHY_A_CFG_REG;
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ctrl_reg = PREI_USB_PHY_A_CTRL_REG;
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adp_bc_reg = PREI_USB_PHY_A_ADP_BC_REG;
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pin = 5;
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pol = 1;
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gpio_power = true;
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@ -180,17 +206,26 @@ amlogic_usbphy_init(int port)
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case 1:
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cfg_reg = PREI_USB_PHY_B_CFG_REG;
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ctrl_reg = PREI_USB_PHY_B_CTRL_REG;
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adp_bc_reg = PREI_USB_PHY_B_ADP_BC_REG;
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pin = 4;
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pol = 0;
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gpio_reset = true;
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aca_enable = true;
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break;
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default:
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return;
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}
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if (port == 0) {
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CBUS_WRITE(RESET1_REG, RESET1_USB);
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}
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amlogic_usbphy_clkgate_enable(port);
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if (gpio_power) {
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gpioao = bus_space_read_4(bst, bsh, gpioao_reg);
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gpioao |= __BIT(pin); /* OEN */
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bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
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if (pol) {
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gpioao |= __BIT(pin + 16); /* OUT */
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} else {
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@ -199,8 +234,6 @@ amlogic_usbphy_init(int port)
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bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
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}
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CBUS_WRITE(RESET1_REG, RESET1_USB);
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delay(1000);
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cfg = CBUS_READ(cfg_reg);
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@ -229,15 +262,40 @@ amlogic_usbphy_init(int port)
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if ((ctrl & PREI_USB_PHY_CTRL_CLK_DET) == 0)
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printf("WARNING: USB PHY port %d clock not detected\n", port);
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if (aca_enable) {
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adp_bc = CBUS_READ(adp_bc_reg);
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adp_bc |= PREI_USB_PHY_ADP_BC_ACA_ENABLE;
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CBUS_WRITE(adp_bc_reg, adp_bc);
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delay(1000);
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adp_bc = CBUS_READ(adp_bc_reg);
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if (adp_bc & PREI_USB_PHY_ADP_BC_ACA_FLOATING)
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printf("WARNING: USB PHY port %d failed to enable "
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"ACA detection\n", port);
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}
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if (gpio_reset) {
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/* Reset */
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gpioao = bus_space_read_4(bst, bsh, gpioao_reg);
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gpioao |= __BIT(pin); /* OEN */
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bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
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if (pol) {
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gpioao |= __BIT(pin + 16); /* OUT */
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} else {
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gpioao &= ~__BIT(pin + 16); /* OUT */
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}
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bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
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delay(1000);
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if (pol) {
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gpioao &= ~__BIT(pin + 16); /* OUT */
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} else {
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gpioao |= __BIT(pin + 16); /* OUT */
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}
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bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
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delay(60000);
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}
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: amlogic_crureg.h,v 1.3 2015/02/28 15:20:43 jmcneill Exp $ */
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/* $NetBSD: amlogic_crureg.h,v 1.4 2015/02/28 18:50:57 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -31,6 +31,17 @@
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#define CBUS_REG(n) ((n) << 2)
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#define EE_CLK_GATING0_REG CBUS_REG(0x1050)
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#define EE_CLK_GATING1_REG CBUS_REG(0x1051)
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#define EE_CLK_GATING2_REG CBUS_REG(0x1052)
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#define EE_CLK_GATING3_REG CBUS_REG(0x1054)
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#define EE_CLK_GATING1_USB_GENERAL __BIT(26)
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#define EE_CLK_GATING1_USB1 __BIT(22)
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#define EE_CLK_GATING1_USB0 __BIT(21)
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#define EE_CLK_GATING2_USB0_TO_DDR __BIT(9)
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#define EE_CLK_GATING2_USB1_TO_DDR __BIT(8)
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#define HHI_SYS_CPU_CLK_CNTL1_REG CBUS_REG(0x1057)
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#define HHI_SYS_CPU_CLK_CNTL1_SDIV __BITS(29,20)
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#define HHI_SYS_CPU_CLK_CNTL1_PERIPH_CLK_MUX __BITS(8,6)
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@ -53,8 +64,10 @@
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#define PREI_USB_PHY_A_CFG_REG CBUS_REG(0x2200)
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#define PREI_USB_PHY_A_CTRL_REG CBUS_REG(0x2201)
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#define PREI_USB_PHY_A_ADP_BC_REG CBUS_REG(0x2203)
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#define PREI_USB_PHY_B_CFG_REG CBUS_REG(0x2208)
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#define PREI_USB_PHY_B_CTRL_REG CBUS_REG(0x2209)
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#define PREI_USB_PHY_B_ADP_BC_REG CBUS_REG(0x220b)
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#define PREI_USB_PHY_CFG_CLK_32K_ALT_SEL __BIT(15)
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@ -64,6 +77,9 @@
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#define PREI_USB_PHY_CTRL_POR __BIT(15)
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#define PREI_USB_PHY_CTRL_CLK_DET __BIT(8)
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#define PREI_USB_PHY_ADP_BC_ACA_FLOATING __BIT(26)
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#define PREI_USB_PHY_ADP_BC_ACA_ENABLE __BIT(16)
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#define WATCHDOG_TC_REG CBUS_REG(0x2640)
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#define WATCHDOG_TC_CPUS __BITS(27,24)
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#define WATCHDOG_TC_ENABLE __BIT(19)
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@ -1,4 +1,4 @@
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/* $NetBSD: amlogic_dwctwo.c,v 1.1 2015/02/28 15:20:43 jmcneill Exp $ */
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/* $NetBSD: amlogic_dwctwo.c,v 1.2 2015/02/28 18:50:57 jmcneill Exp $ */
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/*-
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: amlogic_dwctwo.c,v 1.1 2015/02/28 15:20:43 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: amlogic_dwctwo.c,v 1.2 2015/02/28 18:50:57 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -62,28 +62,28 @@ struct amlogic_dwctwo_softc {
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static struct dwc2_core_params amlogic_dwctwo_params = {
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.otg_cap = 2, /* 0 - HNP/SRP capable */
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.otg_ver = 1, /* 1 - 2.0 */
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.dma_enable = 1, /* 1 - DMA (default, if available) */
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.dma_desc_enable = 1, /* 1 - Descriptor DMA (default, if available) */
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.speed = 0, /* 0 - High Speed */
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.dma_enable = -1, /* 1 - DMA (default, if available) */
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.dma_desc_enable = 0, /* 1 - Descriptor DMA (default, if available) */
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.speed = -1, /* 0 - High Speed */
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.enable_dynamic_fifo = 1, /* 1 - Allow dynamic FIFO sizing (default, if available) */
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.en_multiple_tx_fifo = 1, /* Specifies whether dedicated per-endpoint transmit FIFOs are enabled */
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.host_rx_fifo_size = 520, /* 520 DWORDs */
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.host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
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.host_perio_tx_fifo_size = 256, /* 256 DWORDs */
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.max_transfer_size = 65535,/* 2047 to 65,535 */
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.max_packet_count = 511, /* 15 to 511 */
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.host_channels = 8, /* 1 to 16 */
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.en_multiple_tx_fifo = -1, /* Specifies whether dedicated per-endpoint transmit FIFOs are enabled */
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.host_rx_fifo_size = 512, /* 512 DWORDs */
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.host_nperio_tx_fifo_size = 500, /* 500 DWORDs */
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.host_perio_tx_fifo_size = -1, /* 256 DWORDs */
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.max_transfer_size = -1, /* 2047 to 65,535 */
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.max_packet_count = -1, /* 15 to 511 */
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.host_channels = -1, /* 1 to 16 */
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.phy_type = 1, /* 1- UTMI+ Phy */
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.phy_utmi_width = 8, /* 8 bits */
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.phy_ulpi_ddr = 0, /* Single */
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.phy_ulpi_ext_vbus = 0,
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.i2c_enable = 0,
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.ulpi_fs_ls = 0, /* 0 - No (default) */
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.host_support_fs_ls_low_power = 0, /* 0 - Don't support low power mode (default) */
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.host_ls_low_power_phy_clk = 0, /* 1 - 48 MHz default when phy_type is UTMI+ or ULPI*/
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.ts_dline = 0, /* 0 - No (default) */
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.reload_ctl = 0, /* 0 - No (default for core < 2.92a) */
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.ahbcfg = 0x7, /* INCR16 */
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.phy_utmi_width = -1, /* 8 bits */
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.phy_ulpi_ddr = -1, /* Single */
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.phy_ulpi_ext_vbus = -1,
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.i2c_enable = -1,
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.ulpi_fs_ls = -1, /* 0 - No (default) */
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.host_support_fs_ls_low_power = -1, /* 0 - Don't support low power mode (default) */
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.host_ls_low_power_phy_clk = -1, /* 1 - 48 MHz default when phy_type is UTMI+ or ULPI*/
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.ts_dline = -1, /* 0 - No (default) */
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.reload_ctl = -1, /* 0 - No (default for core < 2.92a) */
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.ahbcfg = 0x3, /* INCR4 */
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.uframe_sched = 1, /* True to enable microframe scheduler */
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};
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