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- slave CPU using LPC UART or console 

- don't use VERBOSE_INIT_ARM
- dont configure obio UART
- using intr -1 for now, causes callout interrupt polling
  can use that until serirq from 8712 works
This commit is contained in:
cliff 2008-11-10 04:39:43 +00:00
parent 129e7690e8
commit ac51de51b3
1 changed files with 10 additions and 3 deletions
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13
sys/arch/evbarm/conf/GEMINI_SLAVE
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@ -126,7 +126,7 @@ options KTRACE # system call tracing, a la ktrace(1)
options DIAGNOSTIC # internally consistency checks options DIAGNOSTIC # internally consistency checks
#options DEBUG #options DEBUG
#options PMAP_DEBUG # Enable pmap_debug_level code #options PMAP_DEBUG # Enable pmap_debug_level code
options VERBOSE_INIT_ARM # verbose bootstraping messages #options VERBOSE_INIT_ARM # verbose bootstraping messages
options DDB # in-kernel debugger options DDB # in-kernel debugger
options DDB_ONPANIC=1 options DDB_ONPANIC=1
options DDB_HISTORY_SIZE=100 # Enable history editing in DDB options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
@ -161,8 +161,15 @@ options MEMSIZE=64
obio0 at mainbus? obio0 at mainbus?
# On-board 16550 UART(s) # On-board 16550 UART(s)
com0 at obio? addr 0x42000000 intr 18 mult 4 ##com0 at obio? addr 0x42000000 intr 18 mult 4
options CONSADDR=0x42000000, CONSPEED=19200 ##options CONSADDR=0x42000000, CONSPEED=19200
# Aux COM at IT8712
geminilpchc0 at obio? addr 0x47000000 intr 20
lpc0 at geminilpchc0 addr 0x47800000
com0 at lpc? ldn 0x01 addr 0x3f8 intr -1
##com0 at lpc? ldn 0x01 addr 0x3f8 intr -1
options CONSADDR=0x478003f8, CONSPEED=19200
# Interrupt controller # Interrupt controller
##geminiicu0 at obio0 addr 0x48000000 intrbase 0 ##geminiicu0 at obio0 addr 0x48000000 intrbase 0