Fix a bug that IFF_ALLMULTI is almost always set.
OpenBSD's ac_multirangecnt is not NetBSD's ec_multicnt.
This commit is contained in:
msaitoh
parent
540580a78d
commit
ac1069da8f
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@ -1,4 +1,4 @@
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/* $NetBSD: if_age.c,v 1.63 2019/11/21 06:22:09 msaitoh Exp $ */
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/* $NetBSD: if_age.c,v 1.64 2019/11/21 09:12:30 msaitoh Exp $ */
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/* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */
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/*-
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@ -31,7 +31,7 @@
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/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.63 2019/11/21 06:22:09 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.64 2019/11/21 09:12:30 msaitoh Exp $");
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#include "vlan.h"
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@ -2275,27 +2275,37 @@ age_rxfilter(struct age_softc *sc)
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*/
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rxcfg |= MAC_CFG_BCAST;
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if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) {
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ifp->if_flags |= IFF_ALLMULTI;
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if (ifp->if_flags & IFF_PROMISC)
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rxcfg |= MAC_CFG_PROMISC;
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else
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rxcfg |= MAC_CFG_ALLMULTI;
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mchash[0] = mchash[1] = 0xFFFFFFFF;
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} else {
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/* Program new filter. */
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if ((ifp->if_flags & IFF_PROMISC) != 0)
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goto update;
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memset(mchash, 0, sizeof(mchash));
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ETHER_LOCK(ec);
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ETHER_FIRST_MULTI(step, ec, enm);
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while (enm != NULL) {
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if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
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/* XXX Use ETHER_F_ALLMULTI in future. */
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ifp->if_flags |= IFF_ALLMULTI;
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ETHER_UNLOCK(ec);
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goto update;
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}
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crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
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mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
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ETHER_NEXT_MULTI(step, enm);
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}
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ETHER_UNLOCK(ec);
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}
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update:
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if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
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if (ifp->if_flags & IFF_PROMISC) {
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rxcfg |= MAC_CFG_PROMISC;
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/* XXX Use ETHER_F_ALLMULTI in future. */
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ifp->if_flags |= IFF_ALLMULTI;
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} else
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rxcfg |= MAC_CFG_ALLMULTI;
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mchash[0] = mchash[1] = 0xFFFFFFFF;
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}
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CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
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CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
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CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
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@ -1,4 +1,4 @@
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/* $NetBSD: if_alc.c,v 1.43 2019/10/30 07:26:28 msaitoh Exp $ */
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/* $NetBSD: if_alc.c,v 1.44 2019/11/21 09:12:30 msaitoh Exp $ */
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/* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */
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/*-
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* Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
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@ -3443,27 +3443,37 @@ alc_iff(struct alc_softc *sc)
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*/
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rxcfg |= MAC_CFG_BCAST;
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if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) {
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ifp->if_flags |= IFF_ALLMULTI;
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if (ifp->if_flags & IFF_PROMISC)
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rxcfg |= MAC_CFG_PROMISC;
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else
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rxcfg |= MAC_CFG_ALLMULTI;
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mchash[0] = mchash[1] = 0xFFFFFFFF;
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} else {
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/* Program new filter. */
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if ((ifp->if_flags & IFF_PROMISC) != 0)
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goto update;
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memset(mchash, 0, sizeof(mchash));
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ETHER_LOCK(ec);
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ETHER_FIRST_MULTI(step, ec, enm);
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while (enm != NULL) {
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if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
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/* XXX Use ETHER_F_ALLMULTI in future. */
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ifp->if_flags |= IFF_ALLMULTI;
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ETHER_UNLOCK(ec);
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goto update;
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}
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crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
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mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
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ETHER_NEXT_MULTI(step, enm);
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}
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ETHER_UNLOCK(ec);
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}
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update:
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if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
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if (ifp->if_flags & IFF_PROMISC) {
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rxcfg |= MAC_CFG_PROMISC;
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/* XXX Use ETHER_F_ALLMULTI in future. */
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ifp->if_flags |= IFF_ALLMULTI;
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} else
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rxcfg |= MAC_CFG_ALLMULTI;
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mchash[0] = mchash[1] = 0xFFFFFFFF;
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}
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CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
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CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
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CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
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@ -1,4 +1,4 @@
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/* $NetBSD: if_ale.c,v 1.34 2019/10/30 07:26:28 msaitoh Exp $ */
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/* $NetBSD: if_ale.c,v 1.35 2019/11/21 09:12:30 msaitoh Exp $ */
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/*-
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* Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
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@ -32,7 +32,7 @@
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/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.34 2019/10/30 07:26:28 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.35 2019/11/21 09:12:30 msaitoh Exp $");
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#include "vlan.h"
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@ -136,10 +136,9 @@ ale_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
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if (phy != sc->ale_phyaddr)
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return -1;
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#if 1
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if (sc->ale_flags & ALE_FLAG_FASTETHER) {
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switch (reg) {
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case MII_100T2CR:
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case MII_100T2SR:
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case MII_EXTSR:
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*val = 0;
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return 0;
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@ -147,6 +146,7 @@ ale_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
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break;
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}
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}
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#endif
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CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
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MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
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@ -177,19 +177,23 @@ ale_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
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if (phy != sc->ale_phyaddr)
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return -1;
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#if 1
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if (sc->ale_flags & ALE_FLAG_FASTETHER) {
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#if 0
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switch (reg) {
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case MII_100T2CR:
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case MII_100T2SR:
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case MII_EXTSR:
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printf("%s: XXXX write EXTSR with %04hx\n", __func__,
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val);
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return 0;
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default:
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break;
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}
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#endif
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}
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#endif
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CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
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(val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
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((uint32_t)val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
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MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
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for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
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DELAY(5);
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@ -255,6 +259,9 @@ ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
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struct ale_softc *sc = ifp->if_softc;
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struct mii_data *mii = &sc->sc_miibus;
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if ((ifp->if_flags & IFF_UP) == 0)
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return;
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mii_pollstat(mii);
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ifmr->ifm_status = mii->mii_media_status;
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ifmr->ifm_active = mii->mii_media_active;
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@ -267,6 +274,7 @@ ale_mediachange(struct ifnet *ifp)
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struct mii_data *mii = &sc->sc_miibus;
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int error;
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printf("%s: called\n", __func__);
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if (mii->mii_instance != 0) {
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struct mii_softc *miisc;
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@ -335,16 +343,20 @@ ale_get_macaddr(struct ale_softc *sc)
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void
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ale_phy_reset(struct ale_softc *sc)
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{
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// int error;
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printf("%s: called\n", __func__);
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/* Reset magic from Linux. */
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CSR_WRITE_2(sc, ALE_GPHY_CTRL,
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GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
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GPHY_CTRL_PHY_PLL_ON);
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DELAY(1000);
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DELAY(2000);
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CSR_WRITE_2(sc, ALE_GPHY_CTRL,
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GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
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GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
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DELAY(1000);
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DELAY(2000);
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#define ATPHY_INT_CTRL 0x12
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#define ATPHY_DBG_ADDR 0x1D
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#define ATPHY_DBG_DATA 0x1E
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@ -374,9 +386,10 @@ ale_phy_reset(struct ale_softc *sc)
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ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr,
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ATPHY_DBG_DATA, 0x2C46);
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DELAY(1000);
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#undef ATPHY_DBG_ADDR
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#undef ATPHY_DBG_DATA
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DELAY(1000);
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}
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void
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@ -389,7 +402,7 @@ ale_attach(device_t parent, device_t self, void *aux)
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const char *intrstr;
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struct ifnet *ifp;
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struct mii_data * const mii = &sc->sc_miibus;
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pcireg_t memtype;
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pcireg_t memtype, pcireg, capoff;
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int mii_flags, error = 0;
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uint32_t rxf_len, txf_len;
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const char *chipname;
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@ -423,6 +436,26 @@ ale_attach(device_t parent, device_t self, void *aux)
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return;
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}
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pcireg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
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PCI_COMMAND_STATUS_REG);
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printf("%s: command = %08x\n", __func__, pcireg);
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pcireg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
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pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, pcireg);
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#if 1
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if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, &capoff,
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NULL) != 0) {
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pcireg = pci_conf_read(pa->pa_pc, pa->pa_tag,
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PCI_COMMAND_STATUS_REG);
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printf("%s: CSR was %#08x\n", __func__, pcireg);
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pcireg = pci_conf_read(pa->pa_pc, pa->pa_tag,
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capoff + PCI_PMCSR);
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printf("%s: PMCSR was %#08x\n", __func__, pcireg);
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pci_conf_write(pa->pa_pc, pa->pa_tag, capoff + PCI_PMCSR, 0);
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delay(1000);
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}
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#endif
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if (pci_intr_map(pa, &ih) != 0) {
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aprint_error_dev(self, "could not map interrupt\n");
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goto fail;
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@ -446,11 +479,6 @@ ale_attach(device_t parent, device_t self, void *aux)
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sc->ale_phyaddr = ALE_PHY_ADDR;
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/* Reset PHY. */
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ale_phy_reset(sc);
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/* Reset the ethernet controller. */
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ale_reset(sc);
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/* Get PCI and chip id/revision. */
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sc->ale_rev = PCI_REVISION(pa->pa_class);
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if (sc->ale_rev >= 0xF0) {
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@ -470,6 +498,11 @@ ale_attach(device_t parent, device_t self, void *aux)
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}
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aprint_normal_dev(self, "%s, %s\n", chipname, intrstr);
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ale_phy_reset(sc);
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/* Reset the ethernet controller. */
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ale_reset(sc);
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/*
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* All known controllers seems to require 4 bytes alignment
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* of Tx buffers to make Tx checksum offload with custom
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@ -1046,13 +1079,13 @@ ale_start(struct ifnet *ifp)
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struct mbuf *m_head;
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int enq;
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if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
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return;
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/* Reclaim transmitted frames. */
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if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
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ale_txeof(sc);
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if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
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return;
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enq = 0;
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for (;;) {
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IFQ_DEQUEUE(&ifp->if_snd, m_head);
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@ -1248,7 +1281,6 @@ ale_stats_update(struct ale_softc *sc)
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stat->tx_multi_colls += smb->tx_multi_colls;
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stat->tx_late_colls += smb->tx_late_colls;
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stat->tx_excess_colls += smb->tx_excess_colls;
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stat->tx_abort += smb->tx_abort;
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stat->tx_underrun += smb->tx_underrun;
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stat->tx_desc_underrun += smb->tx_desc_underrun;
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stat->tx_lenerrs += smb->tx_lenerrs;
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@ -1261,17 +1293,10 @@ ale_stats_update(struct ale_softc *sc)
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ifp->if_collisions += smb->tx_single_colls +
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smb->tx_multi_colls * 2 + smb->tx_late_colls +
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smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
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smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT;
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/*
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* XXX
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* tx_pkts_truncated counter looks suspicious. It constantly
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* increments with no sign of Tx errors. This may indicate
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* the counter name is not correct one so I've removed the
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* counter in output errors.
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*/
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ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
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smb->tx_underrun;
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ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls +
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smb->tx_underrun + smb->tx_pkts_truncated;
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ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
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smb->rx_runts + smb->rx_pkts_truncated +
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@ -1287,6 +1312,7 @@ ale_intr(void *xsc)
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uint32_t status;
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status = CSR_READ_4(sc, ALE_INTR_STATUS);
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printf("%s: status = %#08x\n", __func__, status);
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if ((status & ALE_INTRS) == 0)
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return 0;
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@ -1561,6 +1587,7 @@ ale_tick(void *xsc)
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struct mii_data *mii = &sc->sc_miibus;
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int s;
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printf("%s: called\n", __func__);
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s = splnet();
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mii_tick(mii);
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ale_stats_update(sc);
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@ -1575,10 +1602,8 @@ ale_reset(struct ale_softc *sc)
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uint32_t reg;
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int i;
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/* Initialize PCIe module. From Linux. */
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CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
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CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_LED_MODE | MASTER_RESET);
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CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
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for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
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DELAY(10);
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if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
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@ -1596,6 +1621,9 @@ ale_reset(struct ale_softc *sc)
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if (i == 0)
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printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev),
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reg);
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/* Initialize PCIe module. From Linux. */
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CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
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}
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static int
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@ -1996,27 +2024,37 @@ ale_rxfilter(struct ale_softc *sc)
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*/
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rxcfg |= MAC_CFG_BCAST;
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if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) {
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ifp->if_flags |= IFF_ALLMULTI;
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if (ifp->if_flags & IFF_PROMISC)
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rxcfg |= MAC_CFG_PROMISC;
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else
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rxcfg |= MAC_CFG_ALLMULTI;
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mchash[0] = mchash[1] = 0xFFFFFFFF;
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} else {
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/* Program new filter. */
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if ((ifp->if_flags & IFF_PROMISC) != 0)
|
||||
goto update;
|
||||
|
||||
memset(mchash, 0, sizeof(mchash));
|
||||
|
||||
ETHER_LOCK(ec);
|
||||
ETHER_FIRST_MULTI(step, ec, enm);
|
||||
while (enm != NULL) {
|
||||
if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
|
||||
/* XXX Use ETHER_F_ALLMULTI in future. */
|
||||
ifp->if_flags |= IFF_ALLMULTI;
|
||||
ETHER_UNLOCK(ec);
|
||||
goto update;
|
||||
}
|
||||
crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
|
||||
mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
|
||||
ETHER_NEXT_MULTI(step, enm);
|
||||
}
|
||||
ETHER_UNLOCK(ec);
|
||||
}
|
||||
|
||||
update:
|
||||
if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
|
||||
if (ifp->if_flags & IFF_PROMISC) {
|
||||
rxcfg |= MAC_CFG_PROMISC;
|
||||
/* XXX Use ETHER_F_ALLMULTI in future. */
|
||||
ifp->if_flags |= IFF_ALLMULTI;
|
||||
} else
|
||||
rxcfg |= MAC_CFG_ALLMULTI;
|
||||
mchash[0] = mchash[1] = 0xFFFFFFFF;
|
||||
}
|
||||
CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
|
||||
CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
|
||||
CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: if_cas.c,v 1.35 2019/05/28 07:41:49 msaitoh Exp $ */
|
||||
/* $NetBSD: if_cas.c,v 1.36 2019/11/21 09:12:30 msaitoh Exp $ */
|
||||
/* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.35 2019/05/28 07:41:49 msaitoh Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.36 2019/11/21 09:12:30 msaitoh Exp $");
|
||||
|
||||
#ifndef _MODULE
|
||||
#include "opt_inet.h"
|
||||
|
|
@ -1905,13 +1905,9 @@ cas_iff(struct cas_softc *sc)
|
|||
CAS_MAC_RX_PROMISC_GRP);
|
||||
ifp->if_flags &= ~IFF_ALLMULTI;
|
||||
|
||||
if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) {
|
||||
ifp->if_flags |= IFF_ALLMULTI;
|
||||
if (ifp->if_flags & IFF_PROMISC)
|
||||
rxcfg |= CAS_MAC_RX_PROMISCUOUS;
|
||||
else
|
||||
rxcfg |= CAS_MAC_RX_PROMISC_GRP;
|
||||
} else {
|
||||
if ((ifp->if_flags & IFF_PROMISC) != 0)
|
||||
goto update;
|
||||
|
||||
/*
|
||||
* Set up multicast address filter by passing all multicast
|
||||
* addresses through a crc generator, and then using the
|
||||
|
|
@ -1921,8 +1917,6 @@ cas_iff(struct cas_softc *sc)
|
|||
* (where bit 0 is the MSB).
|
||||
*/
|
||||
|
||||
rxcfg |= CAS_MAC_RX_HASH_FILTER;
|
||||
|
||||
/* Clear hash table */
|
||||
for (i = 0; i < 16; i++)
|
||||
hash[i] = 0;
|
||||
|
|
@ -1930,8 +1924,14 @@ cas_iff(struct cas_softc *sc)
|
|||
ETHER_LOCK(ec);
|
||||
ETHER_FIRST_MULTI(step, ec, enm);
|
||||
while (enm != NULL) {
|
||||
crc = ether_crc32_le(enm->enm_addrlo,
|
||||
ETHER_ADDR_LEN);
|
||||
if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
|
||||
/* XXX Use ETHER_F_ALLMULTI in future. */
|
||||
ifp->if_flags |= IFF_ALLMULTI;
|
||||
ETHER_UNLOCK(ec);
|
||||
goto update;
|
||||
}
|
||||
|
||||
crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
|
||||
|
||||
/* Just want the 8 most significant bits. */
|
||||
crc >>= 24;
|
||||
|
|
@ -1943,14 +1943,24 @@ cas_iff(struct cas_softc *sc)
|
|||
}
|
||||
ETHER_UNLOCK(ec);
|
||||
|
||||
rxcfg |= CAS_MAC_RX_HASH_FILTER;
|
||||
|
||||
/* Now load the hash table into the chip (if we are using it) */
|
||||
for (i = 0; i < 16; i++) {
|
||||
bus_space_write_4(t, h,
|
||||
CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0),
|
||||
hash[i]);
|
||||
}
|
||||
}
|
||||
|
||||
update:
|
||||
if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
|
||||
if (ifp->if_flags & IFF_PROMISC) {
|
||||
rxcfg |= CAS_MAC_RX_PROMISCUOUS;
|
||||
/* XXX Use ETHER_F_ALLMULTI in future. */
|
||||
ifp->if_flags |= IFF_ALLMULTI;
|
||||
} else
|
||||
rxcfg |= CAS_MAC_RX_PROMISC_GRP;
|
||||
}
|
||||
bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue