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Move parts of cpu.h that are not needed by MI code in <arm/locore.h> 

Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>
This commit is contained in:
matt 2013-08-18 06:28:18 +00:00
parent 7c5d0d300c
commit ab152917fb
65 changed files with 525 additions and 460 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
sys/arch/arm/arm/arm_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: arm_machdep.c,v 1.36 2012/08/31 23:59:51 matt Exp $ */
/* $NetBSD: arm_machdep.c,v 1.37 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@ -78,7 +78,7 @@
#include <sys/param.h>
__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.36 2012/08/31 23:59:51 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.37 2013/08/18 06:28:18 matt Exp $");
#include <sys/exec.h>
#include <sys/proc.h>
@ -94,7 +94,7 @@ __KERNEL_RCSID(0, "$NetBSD: arm_machdep.c,v 1.36 2012/08/31 23:59:51 matt Exp $"
#include <sys/exec_aout.h>
#endif
#include <arm/cpufunc.h>
#include <arm/locore.h>
#include <machine/vmparam.h>

10
sys/arch/arm/arm/ast.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ast.c,v 1.21 2012/08/16 17:35:01 matt Exp $ */
/* $NetBSD: ast.c,v 1.22 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1994,1995 Mark Brinicombe
@ -41,11 +41,12 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ast.c,v 1.21 2012/08/16 17:35:01 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: ast.c,v 1.22 2013/08/18 06:28:18 matt Exp $");
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/cpu.h>
#include <sys/proc.h>
#include <sys/acct.h>
#include <sys/systm.h>
@ -54,10 +55,7 @@ __KERNEL_RCSID(0, "$NetBSD: ast.c,v 1.21 2012/08/16 17:35:01 matt Exp $");
#include <sys/vmmeter.h>
#include <sys/userret.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <arm/cpufunc.h>
#include <arm/locore.h>
#include <uvm/uvm_extern.h>

13
sys/arch/arm/arm/bcopyinout.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: bcopyinout.S,v 1.19 2012/10/29 14:09:38 chs Exp $ */
/* $NetBSD: bcopyinout.S,v 1.20 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@ -41,7 +41,8 @@
#include "assym.h"
#include <machine/asm.h>
#include <machine/cpu.h>
#include <arm/locore.h>
#if defined(__XSCALE__) || defined(_ARM_ARCH_6)
/*
@ -51,7 +52,7 @@
#include "bcopyinout_xscale.S"
#else
RCSID("$NetBSD: bcopyinout.S,v 1.19 2012/10/29 14:09:38 chs Exp $")
RCSID("$NetBSD: bcopyinout.S,v 1.20 2013/08/18 06:28:18 matt Exp $")
.text
.align 0
@ -282,6 +283,7 @@ ENTRY(copyin)
RESTORE_REGS
RET
END(copyin)
/*
* r0 = kernel space address
@ -485,6 +487,7 @@ ENTRY(copyout)
RESTORE_REGS
RET
END(copyout)
/*
* r0 = kernel space source address
@ -676,6 +679,7 @@ ENTRY(kcopy)
RESTORE_REGS
RET
END(kcopy)
#endif /* !__XSCALE__ */
#ifdef __PROG32
@ -701,6 +705,7 @@ ENTRY(badaddr_read_1)
mov r0, #0 /* No fault */
1: str ip, [r2, #PCB_ONFAULT]
RET
END(badaddr_read_1)
/*
* int badaddr_read_2(const uint16_t *src, uint16_t *dest)
@ -724,6 +729,7 @@ ENTRY(badaddr_read_2)
mov r0, #0 /* No fault */
1: str ip, [r2, #PCB_ONFAULT]
RET
END(badaddr_read_2)
/*
* int badaddr_read_4(const uint32_t *src, uint32_t *dest)
@ -747,4 +753,5 @@ ENTRY(badaddr_read_4)
mov r0, #0 /* No fault */
1: str ip, [r2, #PCB_ONFAULT]
RET
END(badaddr_read_4)
#endif /* __PROG32 */

8
sys/arch/arm/arm/bcopyinout_xscale.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: bcopyinout_xscale.S,v 1.9 2013/08/12 05:54:51 matt Exp $ */
/* $NetBSD: bcopyinout_xscale.S,v 1.10 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@ -35,7 +35,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
RCSID("$NetBSD: bcopyinout_xscale.S,v 1.9 2013/08/12 05:54:51 matt Exp $")
RCSID("$NetBSD: bcopyinout_xscale.S,v 1.10 2013/08/18 06:28:18 matt Exp $")
.text
.align 0
@ -457,6 +457,7 @@ ENTRY(copyin)
ldrbt ip, [r0]
strb ip, [r1]
RET
END(copyin)
/*
@ -896,7 +897,7 @@ ENTRY(copyout)
ldrb ip, [r0]
strbt ip, [r1]
RET
END(copyout)
/*
* r0 = kernel space source address
@ -1314,3 +1315,4 @@ ENTRY(kcopy)
ldrb ip, [r0]
strb ip, [r1]
RET
END(kcopy)

32
sys/arch/arm/arm/blockio.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: blockio.S,v 1.7 2013/08/11 03:09:41 matt Exp $ */
/* $NetBSD: blockio.S,v 1.8 2013/08/18 06:29:29 matt Exp $ */
/*
* Copyright (c) 2001 Ben Harris.
@ -48,7 +48,7 @@
#include <machine/asm.h>
RCSID("$NetBSD: blockio.S,v 1.7 2013/08/11 03:09:41 matt Exp $")
RCSID("$NetBSD: blockio.S,v 1.8 2013/08/18 06:29:29 matt Exp $")
/*
* Read bytes from an I/O address into a block of memory
@ -101,6 +101,7 @@ ENTRY(read_multi_1)
ldrbgt r3, [r0]
strbgt r3, [r1], #1
ldmdb fp, {fp, sp, pc}
END(read_multi_1)
/*
* Write bytes to an I/O address from a block of memory
@ -152,6 +153,7 @@ ENTRY(write_multi_1)
ldrbgt r3, [r1], #1
strbgt r3, [r0]
ldmdb fp, {fp, sp, pc}
END(write_multi_1)
/*
* Reads short ints (16 bits) from an I/O address into a block of memory
@ -164,7 +166,7 @@ ENTRY(write_multi_1)
ENTRY(insw)
/* Make sure that we have a positive length */
cmp r2, #0x00000000
movle pc, lr
RETc(le)
/* If the destination address and the size is word aligned, do it fast */
@ -182,7 +184,7 @@ ENTRY(insw)
strb r3, [r1], #0x0001
bgt .Linswloop
mov pc, lr
RET
/* Word aligned insw */
@ -198,7 +200,8 @@ ENTRY(insw)
subs r2, r2, #0x00000002 /* Next */
bgt .Lfastinswloop
mov pc, lr
RET
END(insw)
/*
@ -212,7 +215,7 @@ ENTRY(insw)
ENTRY(outsw)
/* Make sure that we have a positive length */
cmp r2, #0x00000000
movle pc, lr
RETc(le)
/* If the destination address and the size is word aligned, do it fast */
@ -231,7 +234,7 @@ ENTRY(outsw)
str r3, [r0]
bgt .Loutswloop
mov pc, lr
RET
/* Word aligned outsw */
@ -259,7 +262,8 @@ ENTRY(outsw)
bgt .Lfastoutswloop
mov pc, lr
RET
END(outsw)
/*
* reads short ints (16 bits) from an I/O address into a block of memory
@ -274,7 +278,7 @@ ENTRY(outsw)
ENTRY(insw16)
/* Make sure that we have a positive length */
cmp r2, #0x00000000
movle pc, lr
RETc(le)
/* If the destination address is word aligned and the size suitably
aligned, do it fast */
@ -318,6 +322,7 @@ ENTRY(insw16)
bgt .Linsw16loop
pop {r4,r5,pc} /* Restore regs and go home */
END(insw16)
/*
@ -331,7 +336,7 @@ ENTRY(insw16)
ENTRY(outsw16)
/* Make sure that we have a positive length */
cmp r2, #0x00000000
movle pc, lr
RETc(le)
/* If the destination address is word aligned and the size suitably
aligned, do it fast */
@ -385,6 +390,7 @@ ENTRY(outsw16)
bgt .Loutsw16loop
pop {r4,r5,pc} /* and go home */
END(outsw16)
/*
* reads short ints (16 bits) from an I/O address into a block of memory
@ -400,7 +406,7 @@ ENTRY(outsw16)
ENTRY(inswm8)
/* Make sure that we have a positive length */
cmp r2, #0x00000000
movle pc, lr
RETc(le)
/* If the destination address is word aligned and the size suitably
aligned, do it fast */
@ -481,6 +487,7 @@ ENTRY(inswm8)
.Linswm8_l1:
pop {r4-r9,pc} /* And go home */
END(inswm8)
/*
* write short ints (16 bits) to an I/O address from a block of memory
@ -496,7 +503,7 @@ ENTRY(inswm8)
ENTRY(outswm8)
/* Make sure that we have a positive length */
cmp r2, #0x00000000
movle pc, lr
RETc(le)
/* If the destination address is word aligned and the size suitably
aligned, do it fast */
@ -585,3 +592,4 @@ ENTRY(outswm8)
.Loutswm8_l1:
pop {r4-r8,pc} /* And go home */
END(outswm8)

10
sys/arch/arm/arm/bus_space_a2x.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_space_a2x.S,v 1.2 2012/07/15 20:48:53 matt Exp $ */
/* $NetBSD: bus_space_a2x.S,v 1.3 2013/08/18 06:28:18 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@ -30,10 +30,10 @@
*/
#include <arm/asm.h>
#include <arm/cpu.h>
#include <arm/locore.h>
#include <arm/byte_swap.h>
RCSID("$NetBSD: bus_space_a2x.S,v 1.2 2012/07/15 20:48:53 matt Exp $")
RCSID("$NetBSD: bus_space_a2x.S,v 1.3 2013/08/18 06:28:18 matt Exp $")
/*
* bus_space_read_[124](void *cookie, bus_space_handle_t handle,
@ -120,6 +120,7 @@ ENTRY_NP(a2x_bs_w_2)
strh r3, [r1, r2]
RET
END(a2x_bs_w_2)
END(a2x_bs_w_2_swap)
#endif
ENTRY_NP(a2x_bs_w_4_swap)
@ -128,6 +129,7 @@ ENTRY_NP(a2x_bs_w_4)
str r3, [r1, r2, lsl #1]
RET
END(a2x_bs_w_4)
END(a2x_bs_w_4_swap)
/*
* bus_space_write_multi_[124](void *cookie, bus_space_handle_t handle,
@ -154,7 +156,7 @@ END(a2x_bs_wm_2_swap)
ENTRY_NP(a2x_bs_wm_4)
lsl r2, r2, #1
b generic_bs_wm_4
END(a2x_bs_wm_1)
END(a2x_bs_wm_4)
ENTRY_NP(a2x_bs_wm_4_swap)
lsl r2, r2, #1

8
sys/arch/arm/arm/bus_space_a4x.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_space_a4x.S,v 1.2 2012/07/15 20:48:53 matt Exp $ */
/* $NetBSD: bus_space_a4x.S,v 1.3 2013/08/18 06:28:18 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@ -30,10 +30,10 @@
*/
#include <arm/asm.h>
#include <arm/cpu.h>
#include <arm/locore.h>
#include <arm/byte_swap.h>
RCSID("$NetBSD: bus_space_a4x.S,v 1.2 2012/07/15 20:48:53 matt Exp $")
RCSID("$NetBSD: bus_space_a4x.S,v 1.3 2013/08/18 06:28:18 matt Exp $")
/*
* bus_space_read_[124](void *cookie, bus_space_handle_t handle,
@ -120,6 +120,7 @@ ENTRY_NP(a4x_bs_w_2)
strh r3, [r1, r2]
RET
END(a4x_bs_w_2)
END(a4x_bs_w_2_swap)
#endif
ENTRY_NP(a4x_bs_w_4_swap)
@ -128,6 +129,7 @@ ENTRY_NP(a4x_bs_w_4)
str r3, [r1, r2, lsl #2]
RET
END(a4x_bs_w_4)
END(a4x_bs_w_4_swap)
/*
* bus_space_write_multi_[124](void *cookie, bus_space_handle_t handle,

6
sys/arch/arm/arm/bus_space_asm_generic.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_space_asm_generic.S,v 1.9 2013/03/19 17:11:13 skrll Exp $ */
/* $NetBSD: bus_space_asm_generic.S,v 1.10 2013/08/18 06:29:29 matt Exp $ */
/*
* Copyright (c) 1997 Causality Limited.
@ -106,6 +106,7 @@ ENTRY_NP(generic_armv4_bs_w_2)
DSB
RET
END(generic_armv4_bs_w_2)
END(generic_armv4_bs_w_2_swap)
#endif
ENTRY_NP(generic_bs_w_4_swap)
@ -115,6 +116,7 @@ ENTRY_NP(generic_bs_w_4)
DSB
RET
END(generic_bs_w_4)
END(generic_bs_w_4_swap)
/*
* read multiple
@ -504,6 +506,7 @@ ENTRY_NP(generic_armv4_bs_sr_2)
DSB
RET
END(generic_armv4_bs_sr_2)
END(generic_armv4_bs_sr_2_swap)
#endif
ENTRY_NP(generic_bs_sr_4_swap)
@ -522,6 +525,7 @@ ENTRY_NP(generic_bs_sr_4)
DSB
RET
END(generic_bs_sr_4)
END(generic_bs_sr_4_swap)
/*
* copy region

15
sys/arch/arm/arm/bus_space_notimpl.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_space_notimpl.S,v 1.4 2005/12/11 12:16:41 christos Exp $ */
/* $NetBSD: bus_space_notimpl.S,v 1.5 2013/08/18 06:29:29 matt Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
@ -43,7 +43,7 @@
#define __C(x,y) __CONCAT(x,y)
#define __S(s) __STRING(s)
#define NAME(func) __C(BUS_SPACE,__C(_bs_,func))
#define LNAME(func) __C(L,NAME(func))
#define LNAME(func) __C(.L,NAME(func))
#define __L(x) _C_LABEL(x)
#define GLOBAL(func) .global __L(NAME(func))
@ -56,22 +56,23 @@
#define NOT_IMPL(func) \
GLOBAL(func) ; \
LABEL(func) ; \
stmfd sp!, {r0-r3} ; \
push {r0-r3} ; \
adr r1, LNAME(__C(func,_funcname)) ; \
mov r2, sp ; \
b bs_notimpl_panic ; \
b .Lbs_notimpl_panic ; \
; \
LLABEL(__C(func,_funcname)) ; \
.asciz __S(func) ; \
.align 0 ; \
END(NAME(func))
bs_notimpl_message:
.Lbs_notimpl_message:
.ascii __S(BUS_SPACE)
.asciz "_%s: args at %p"
.align 0
bs_notimpl_panic:
adr r0, bs_notimpl_message
.Lbs_notimpl_panic:
adr r0, .Lbs_notimpl_message
b _C_LABEL(panic)
/*

25
sys/arch/arm/arm/copystr.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: copystr.S,v 1.10 2009/01/18 01:19:32 bjh21 Exp $ */
/* $NetBSD: copystr.S,v 1.11 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@ -42,10 +42,12 @@
#include "opt_cpuoptions.h"
#include "assym.h"
#include <machine/asm.h>
#include <machine/cpu.h>
RCSID("$NetBSD: copystr.S,v 1.10 2009/01/18 01:19:32 bjh21 Exp $")
#include <machine/asm.h>
#include <arm/locore.h>
RCSID("$NetBSD: copystr.S,v 1.11 2013/08/18 06:28:18 matt Exp $")
#include <sys/errno.h>
@ -60,7 +62,7 @@ RCSID("$NetBSD: copystr.S,v 1.10 2009/01/18 01:19:32 bjh21 Exp $")
* Copy string from r0 to r1
*/
ENTRY(copystr)
stmfd sp!, {r4-r5} /* stack is 8 byte aligned */
push {r4-r5} /* stack is 8 byte aligned */
teq r2, #0x00000000
mov r5, #0x00000000
moveq r0, #ENAMETOOLONG
@ -80,12 +82,13 @@ ENTRY(copystr)
2: teq r3, #0x00000000
strne r5, [r3]
ldmfd sp!, {r4-r5} /* stack is 8 byte aligned */
pop {r4-r5} /* stack is 8 byte aligned */
RET
END(copystr)
#ifdef __PROG32
#define SAVE_REGS stmfd sp!, {r4-r6}
#define RESTORE_REGS ldmfd sp!, {r4-r6}
#define SAVE_REGS push {r3-r6}
#define RESTORE_REGS pop {r3-r6}
#else
/* Need to save R14_svc because it'll get trampled if we take a page fault. */
#define SAVE_REGS stmfd sp!, {r4-r6, r14}
@ -137,6 +140,7 @@ ENTRY(copyinstr)
RESTORE_REGS
RET
END(copyinstr)
/*
* r0 - kernel space address
@ -195,11 +199,12 @@ ENTRY(copyoutstr)
.Lcopystrpcbfault:
mov r2, r1
mov r1, r0
adr r0, Lcopystrpcbfaulttext
adr r0, .Lcopystrpcbfaulttext
bic sp, sp, #7 /* align stack to 8 bytes */
b _C_LABEL(panic)
Lcopystrpcbfaulttext:
.Lcopystrpcbfaulttext:
.asciz "No valid PCB during copyinoutstr() addr1=%08x addr2=%08x\n"
.align 0
#endif
END(copyoutstr)

50
sys/arch/arm/arm/cpufunc_asm.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm.S,v 1.15 2012/02/16 02:35:52 christos Exp $ */
/* $NetBSD: cpufunc_asm.S,v 1.16 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1997,1998 Mark Brinicombe.
@ -49,6 +49,7 @@
ENTRY(cpufunc_nullop)
RET
END(cpufunc_nullop)
/*
* Generic functions to read the internal coprocessor registers
@ -63,22 +64,27 @@ ENTRY(cpufunc_nullop)
ENTRY(cpufunc_id)
mrc p15, 0, r0, c0, c0, 0
RET
ENTRY(cpu_get_control)
mrc p15, 0, r0, c1, c0, 0
RET
END(cpufunc_id)
ENTRY(cpu_read_cache_config)
mrc p15, 0, r0, c0, c0, 1
RET
END(cpu_read_cache_config)
ENTRY(cpu_get_control)
mrc p15, 0, r0, c1, c0, 0
RET
END(cpu_get_control)
ENTRY(cpufunc_faultstatus)
mrc p15, 0, r0, c5, c0, 0
RET
END(cpufunc_faultstatus)
ENTRY(cpufunc_faultaddress)
mrc p15, 0, r0, c6, c0, 0
RET
END(cpufunc_faultaddress)
/*
@ -101,6 +107,7 @@ ENTRY(cpufunc_control)
ENTRY(cpufunc_domains)
mcr p15, 0, r0, c3, c0, 0
RET
END(cpufunc_domains)
/*
* Generic functions to read/modify/write the internal coprocessor registers
@ -114,13 +121,17 @@ ENTRY(cpufunc_domains)
ENTRY(cpufunc_control)
mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
bic r2, r3, r0 /* Clear bits */
eor r2, r2, r1 /* XOR bits */
bics r2, r3, r0 /* Clear bits */
eors r2, r2, r1 /* XOR bits */
teq r2, r3 /* Only write if there is a change */
#ifdef __thumb__
it ne
#endif
mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
mov r0, r3 /* Return old value */
movs r0, r3 /* Return old value */
RET
END(cpufunc_control)
/*
* other potentially useful software functions are:
@ -135,16 +146,19 @@ ENTRY(cpufunc_control)
* instruction doing the store. This offset is defined to be the same
* for all STRs and STMs on a given implementation. Code based on
* section 2.4.3 of the ARM ARM (2nd Ed.), with modifications to work
* in 26-bit modes as well.
* in 26-bit modes as well. In Thumb mode, the PC can't be directly
* stored.
*/
ENTRY(get_pc_str_offset)
mov ip, sp
stmfd sp!, {fp, ip, lr, pc}
sub fp, ip, #4
sub sp, sp, #4
#ifdef __thumb__
mov r0, #4
RET
#else
mov r1, pc /* R1 = addr of following STR */
mov r0, r0
str pc, [sp] /* [SP] = . + offset */
ldr r0, [sp]
sub r0, r0, r1
ldmdb fp, {fp, sp, pc}
mov r8, r8
push {pc} /* [SP] = . + offset */
pop {r0}
subs r0, r0, r1
RET
#endif
END(get_pc_str_offset)

4
sys/arch/arm/arm/cpufunc_asm_arm10.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_arm10.S,v 1.9 2010/01/03 04:25:16 uebayasi Exp $ */
/* $NetBSD: cpufunc_asm_arm10.S,v 1.10 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002 ARM Limited
@ -31,8 +31,8 @@
* ARM10 assembly functions for CPU / MMU / TLB specific operations
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
/*
* TLB functions

16
sys/arch/arm/arm/cpufunc_asm_arm11.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_arm11.S,v 1.9 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_arm11.S,v 1.10 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002, 2005 ARM Limited
@ -35,8 +35,8 @@
*/
#include "assym.h"
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
/*
* Functions to set the MMU Translation Table Base register
@ -55,6 +55,7 @@ ENTRY(arm11_setttb)
mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
mcrne p15, 0, r0, c7, c10, 4 /* drain write buffer */
RET
END(arm11_setttb)
/*
* TLB functions
@ -64,12 +65,14 @@ ENTRY(arm11_tlb_flushID_SE)
mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
RET
END(arm11_tlb_flushID_SE)
ENTRY(arm11_tlb_flushI_SE)
mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
RET
END(arm11_tlb_flushI_SE)
/*
* Context switch.
@ -91,6 +94,7 @@ ENTRY(arm11_context_switch)
nop
nop
RET
END(arm11_context_switch)
/*
* TLB functions
@ -99,21 +103,25 @@ ENTRY(arm11_tlb_flushID)
mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
RET
END(arm11_tlb_flushID)
ENTRY(arm11_tlb_flushI)
mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
RET
END(arm11_tlb_flushI)
ENTRY(arm11_tlb_flushD)
mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
RET
END(arm11_tlb_flushD)
ENTRY(arm11_tlb_flushD_SE)
mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
RET
END(arm11_tlb_flushD_SE)
/*
* Other functions
@ -121,8 +129,10 @@ ENTRY(arm11_tlb_flushD_SE)
ENTRY(arm11_drain_writebuf)
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
RET
END(arm11_drain_writebuf)
ENTRY_NP(arm11_sleep)
mov r0, #0
mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
RET
END(arm11_sleep)

7
sys/arch/arm/arm/cpufunc_asm_arm1136.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_arm1136.S,v 1.3 2012/07/21 12:19:15 skrll Exp $ */
/* $NetBSD: cpufunc_asm_arm1136.S,v 1.4 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2007 Microsoft
@ -30,10 +30,10 @@
*/
#include "assym.h"
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
RCSID("$NetBSD: cpufunc_asm_arm1136.S,v 1.3 2012/07/21 12:19:15 skrll Exp $")
RCSID("$NetBSD: cpufunc_asm_arm1136.S,v 1.4 2013/08/18 06:28:18 matt Exp $")
ENTRY_NP(arm1136_sleep_rev0) /* errata 336501 */
mov r0, #0
@ -41,3 +41,4 @@ ENTRY_NP(arm1136_sleep_rev0) /* errata 336501 */
mcr p15, 0, r0, c7, c10, 5 /* data memory barrier */
mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
RET
END(arm1136_sleep_rev0)

7
sys/arch/arm/arm/cpufunc_asm_arm11x6.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.2 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.3 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2007 Microsoft
@ -60,10 +60,10 @@
#include "assym.h"
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.2 2012/09/22 00:33:37 matt Exp $")
RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.3 2013/08/18 06:28:18 matt Exp $")
#if 0
#define Invalidate_I_cache(Rtmp1, Rtmp2) \
@ -219,3 +219,4 @@ ENTRY_NP(arm11x6_sleep)
nop
bne 1b
RET
END(arm11x6_sleep)

4
sys/arch/arm/arm/cpufunc_asm_arm3.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_arm3.S,v 1.2 2011/12/11 03:30:23 kiyohara Exp $ */
/* $NetBSD: cpufunc_asm_arm3.S,v 1.3 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1997,1998 Mark Brinicombe.
@ -35,8 +35,8 @@
* ARM3 assembly functions for CPU / MMU / TLB specific operations
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
#ifdef CPU_ARM3
/*

4
sys/arch/arm/arm/cpufunc_asm_arm67.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_arm67.S,v 1.5 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_arm67.S,v 1.6 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1997,1998 Mark Brinicombe.
@ -35,8 +35,8 @@
* ARM6/ARM7 assembly functions for CPU / MMU / TLB specific operations
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
/*
* Functions to set the MMU Translation Table Base register

4
sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_arm7tdmi.S,v 1.5 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_arm7tdmi.S,v 1.6 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2001 John Fremlin
@ -34,8 +34,8 @@
* ARM7TDMI assembly functions for CPU / MMU / TLB specific operations
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
/*
* Functions to set the MMU Translation Table Base register

4
sys/arch/arm/arm/cpufunc_asm_arm8.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_arm8.S,v 1.7 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_arm8.S,v 1.8 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1997 ARM Limited
@ -35,8 +35,8 @@
* ARM8 assembly functions for CPU / MMU / TLB specific operations
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
ENTRY(arm8_clock_config)
mrc p15, 0, r3, c15, c0, 0 /* Read the clock register */

4
sys/arch/arm/arm/cpufunc_asm_arm9.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_arm9.S,v 1.9 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_arm9.S,v 1.10 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2001, 2004 ARM Limited
@ -31,8 +31,8 @@
* ARM9 assembly functions for CPU / MMU / TLB specific operations
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
#include "assym.h"

19
sys/arch/arm/arm/cpufunc_asm_armv4.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_armv4.S,v 1.2 2008/10/14 16:01:22 matt Exp $ */
/* $NetBSD: cpufunc_asm_armv4.S,v 1.3 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2001 ARM Limited
@ -36,33 +36,38 @@
* ARM9 assembly functions for CPU / MMU / TLB specific operations
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
/*
* TLB functions
*/
ENTRY(armv4_tlb_flushID)
mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
mov pc, lr
RET
END(armv4_tlb_flushID)
ENTRY(armv4_tlb_flushI)
mov r0, #0
mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
mov pc, lr
RET
END(armv4_tlb_flushI)
ENTRY(armv4_tlb_flushD)
mov r0, #0
mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
mov pc, lr
RET
END(armv4_tlb_flushD)
ENTRY(armv4_tlb_flushD_SE)
mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
mov pc, lr
RET
END(armv4_tlb_flushD_SE)
/*
* Other functions
*/
ENTRY(armv4_drain_writebuf)
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
mov pc, lr
RET
END(armv4_drain_writebuf)

4
sys/arch/arm/arm/cpufunc_asm_armv5.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_armv5.S,v 1.5 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_armv5.S,v 1.6 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002, 2005 ARM Limited
@ -33,8 +33,8 @@
* operations.
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
#include "assym.h"

4
sys/arch/arm/arm/cpufunc_asm_armv5_ec.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_armv5_ec.S,v 1.3 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_armv5_ec.S,v 1.4 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002, 2005 ARM Limited
@ -36,8 +36,8 @@
* This source was derived from that file.
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
#include "assym.h"

17
sys/arch/arm/arm/cpufunc_asm_armv6.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_armv6.S,v 1.5 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_armv6.S,v 1.6 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002, 2005 ARM Limited
@ -35,8 +35,8 @@
*/
#include "assym.h"
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
.arch armv6
@ -58,6 +58,7 @@ ENTRY(armv6_setttb)
mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
RET
END(armv6_setttb)
/*
* Cache operations.
@ -71,6 +72,7 @@ ENTRY_NP(armv6_icache_sync_range)
mcrr p15, 0, r1, r0, c12 /* clean D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_icache_sync_range)
/* LINTSTUB: void armv6_icache_sync_all(void); */
ENTRY_NP(armv6_icache_sync_all)
@ -83,6 +85,7 @@ ENTRY_NP(armv6_icache_sync_all)
mcr p15, 0, r0, c7, c10, 0 /* Clean D cache */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_icache_sync_all)
/* LINTSTUB: void armv6_dcache_wb_range(vaddr_t, vsize_t); */
ENTRY(armv6_dcache_wb_range)
@ -91,7 +94,8 @@ ENTRY(armv6_dcache_wb_range)
mcrr p15, 0, r1, r0, c12 /* clean D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_dcache_wb_range)
/* LINTSTUB: void armv6_dcache_wbinv_range(vaddr_t, vsize_t); */
ENTRY(armv6_dcache_wbinv_range)
add r1, r1, r0
@ -99,7 +103,8 @@ ENTRY(armv6_dcache_wbinv_range)
mcrr p15, 0, r1, r0, c14 /* clean and invaliate D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_dcache_wbinv_range)
/*
* Note, we must not invalidate everything. If the range is too big we
* must use wb-inv of the entire cache.
@ -112,6 +117,7 @@ ENTRY(armv6_dcache_inv_range)
mcrr p15, 0, r1, r0, c6 /* invaliate D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_dcache_inv_range)
/* LINTSTUB: void armv6_idcache_wbinv_range(vaddr_t, vsize_t); */
ENTRY(armv6_idcache_wbinv_range)
@ -121,6 +127,7 @@ ENTRY(armv6_idcache_wbinv_range)
mcrr p15, 0, r1, r0, c14 /* clean & invaliate D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_idcache_wbinv_range)
/* LINTSTUB: void armv6_idcache_wbinv_all(void); */
ENTRY_NP(armv6_idcache_wbinv_all)
@ -137,3 +144,5 @@ ENTRY(armv6_dcache_wbinv_all)
mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_dcache_wbinv_all)
END(armv6_idcache_wbinv_all)

2
sys/arch/arm/arm/cpufunc_asm_armv7.S
View File

@ -28,8 +28,8 @@
*/
#include "assym.h"
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
.arch armv7a

4
sys/arch/arm/arm/cpufunc_asm_fa526.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_fa526.S,v 1.5 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_fa526.S,v 1.6 2013/08/18 06:28:18 matt Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@ -28,8 +28,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/locore.h>
#define CACHELINE_SIZE 16

6
sys/arch/arm/arm/cpufunc_asm_ixp12x0.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_ixp12x0.S,v 1.2 2002/08/17 16:36:31 thorpej Exp $ */
/* $NetBSD: cpufunc_asm_ixp12x0.S,v 1.3 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@ -35,8 +35,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/asm.h>
#include <arm/locore.h>
/*
* This function is the same as sa110_context_switch for now, the plan

6
sys/arch/arm/arm/cpufunc_asm_pj4b.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_pj4b.S,v 1.2 2013/05/19 16:53:58 rkujawa Exp $ */
/* $NetBSD: cpufunc_asm_pj4b.S,v 1.3 2013/08/18 06:28:18 matt Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@ -38,8 +38,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "assym.h"
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/asm.h>
#include <arm/locore.h>
#define TTB_RGN_OC_WB (3 << 3)
#define TTB_IRGN_WB ((1 << 0) | (1 << 6))

6
sys/arch/arm/arm/cpufunc_asm_sa1.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_sa1.S,v 1.12 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_sa1.S,v 1.13 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1997,1998 Mark Brinicombe.
@ -35,8 +35,8 @@
* SA-1 assembly functions for CPU / MMU / TLB specific operations
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/asm.h>
#include <arm/locore.h>
.Lblock_userspace_access:
.word _C_LABEL(block_userspace_access)

6
sys/arch/arm/arm/cpufunc_asm_sa11x0.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_sa11x0.S,v 1.3 2002/08/17 16:36:32 thorpej Exp $ */
/* $NetBSD: cpufunc_asm_sa11x0.S,v 1.4 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@ -35,8 +35,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/asm.h>
#include <arm/locore.h>
.data
.global _C_LABEL(sa11x0_idle_mem)

4
sys/arch/arm/arm/cpufunc_asm_sheeva.S
View File

@ -29,8 +29,8 @@
* SUCH DAMAGE.
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/asm.h>
#include <arm/locore.h>
#include "assym.h"

44
sys/arch/arm/arm/cpufunc_asm_xscale.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc_asm_xscale.S,v 1.20 2012/09/22 00:33:37 matt Exp $ */
/* $NetBSD: cpufunc_asm_xscale.S,v 1.21 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@ -71,8 +71,8 @@
* XScale assembly functions for CPU / MMU / TLB specific operations
*/
#include <machine/cpu.h>
#include <machine/asm.h>
#include <arm/asm.h>
#include <arm/locore.h>
/*
* Size of the XScale core D-cache.
@ -105,6 +105,7 @@
ENTRY(xscale_cpwait)
CPWAIT_AND_RETURN(r0)
END(xscale_cpwait)
/*
* We need a separate cpu_control() entry point, since we have to
@ -122,6 +123,7 @@ ENTRY(xscale_control)
mov r0, r3 /* Return old value */
CPWAIT_AND_RETURN(r1)
END(xscale_control)
/*
* Functions to set the MMU Translation Table Base register
@ -171,7 +173,8 @@ ENTRY(xscale_setttb)
#else
str r2, [r3]
#endif
mov pc, lr
RET
END(xscale_setttb)
/*
* TLB functions
@ -182,7 +185,8 @@ ENTRY(xscale_setttb)
ENTRY(xscale_tlb_flushID_SE)
mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
mov pc, lr
RET
END(xscale_tlb_flushID_SE)
/*
* Cache functions
@ -190,18 +194,22 @@ ENTRY(xscale_tlb_flushID_SE)
ENTRY(xscale_cache_flushID)
mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
CPWAIT_AND_RETURN(r0)
END(xscale_cache_flushID)
ENTRY(xscale_cache_flushI)
mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
CPWAIT_AND_RETURN(r0)
END(xscale_cache_flushI)
ENTRY(xscale_cache_flushD)
mcr p15, 0, r0, c7, c6, 0 /* flush D cache */
CPWAIT_AND_RETURN(r0)
END(xscale_cache_flushD)
ENTRY(xscale_cache_flushI_SE)
mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
CPWAIT_AND_RETURN(r0)
END(xscale_cache_flushI_SE)
ENTRY(xscale_cache_flushD_SE)
/*
@ -212,10 +220,12 @@ ENTRY(xscale_cache_flushD_SE)
mcr p15, 0, r0, c7, c10, 1
mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
CPWAIT_AND_RETURN(r0)
END(xscale_cache_flushD_SE)
ENTRY(xscale_cache_cleanD_E)
mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
CPWAIT_AND_RETURN(r0)
END(xscale_cache_cleanD_E)
/*
* Information for the XScale cache clean/purge functions:
@ -322,7 +332,12 @@ ENTRY(xscale_cache_cleanD)
CPWAIT(r0)
XSCALE_CACHE_CLEAN_EPILOGUE
mov pc, lr
RET
END(xscale_cache_cleanD)
END(xscale_cache_purgeD)
END(xscale_cache_cleanID)
END(xscale_cache_purgeID)
END(xscale_cache_syncI)
/*
* Clean the mini-data cache.
@ -342,6 +357,7 @@ ENTRY(xscale_cache_clean_minidata)
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
CPWAIT_AND_RETURN(r1)
END(xscale_cache_clean_minidata)
ENTRY(xscale_cache_purgeID_E)
mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
@ -350,6 +366,7 @@ ENTRY(xscale_cache_purgeID_E)
mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
CPWAIT_AND_RETURN(r1)
END(xscale_cache_purgeID_E)
ENTRY(xscale_cache_purgeD_E)
mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
@ -357,6 +374,7 @@ ENTRY(xscale_cache_purgeD_E)
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
CPWAIT_AND_RETURN(r1)
END(xscale_cache_purgeD_E)
/*
* Soft functions
@ -382,6 +400,8 @@ ENTRY(xscale_cache_cleanD_rng)
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
CPWAIT_AND_RETURN(r0)
END(xscale_cache_cleanD_rng)
END(xscale_cache_cleanID_rng)
ENTRY(xscale_cache_purgeID_rng)
cmp r1, #0x4000
@ -403,6 +423,7 @@ ENTRY(xscale_cache_purgeID_rng)
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
CPWAIT_AND_RETURN(r0)
END(xscale_cache_purgeID_rng)
ENTRY(xscale_cache_purgeD_rng)
cmp r1, #0x4000
@ -423,6 +444,7 @@ ENTRY(xscale_cache_purgeD_rng)
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
CPWAIT_AND_RETURN(r0)
END(xscale_cache_purgeD_rng)
ENTRY(xscale_cache_syncI_rng)
cmp r1, #0x4000
@ -443,6 +465,7 @@ ENTRY(xscale_cache_syncI_rng)
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
CPWAIT_AND_RETURN(r0)
END(xscale_cache_syncI_rng)
ENTRY(xscale_cache_flushD_rng)
and r2, r0, #0x1f
@ -457,6 +480,7 @@ ENTRY(xscale_cache_flushD_rng)
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
CPWAIT_AND_RETURN(r0)
END(xscale_cache_flushD_rng)
/*
* Context switch.
@ -479,6 +503,7 @@ ENTRY(xscale_context_switch)
mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
CPWAIT_AND_RETURN(r0)
END(xscale_context_switch)
/*
* xscale_cpu_sleep
@ -491,9 +516,8 @@ ENTRY(xscale_context_switch)
*/
ENTRY(xscale_cpu_sleep)
tst r0, #0x00000000
bne 1f
RETc(ne)
mov r0, #0x1
mcr p14, 0, r0, c7, c0, 0
1:
mov pc, lr
RET
END(xscale_cpu_sleep)

25
sys/arch/arm/arm/fiq_subr.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: fiq_subr.S,v 1.4 2008/04/27 18:58:43 matt Exp $ */
/* $NetBSD: fiq_subr.S,v 1.5 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@ -52,12 +52,17 @@
#endif
#ifdef __PROG32
#ifdef _ARM_ARCH_6
#define SWITCH_TO_FIQ_MODE \
cps #PSR_FIQ32_MODE
#else
#define SWITCH_TO_FIQ_MODE \
mrs r2, cpsr_all ; \
mov r3, r2 ; \
bic r2, r2, #(PSR_MODE) ; \
orr r2, r2, #(PSR_FIQ32_MODE) ; \
msr cpsr_all, r2
#endif
#else
#define SWITCH_TO_FIQ_MODE ; \
mov r1, r15 ; \
@ -67,8 +72,13 @@
#endif /* __PROG32 */
#ifdef __PROG32
#ifdef _ARM_ARCH_6
#define BACK_TO_SVC_MODE \
cps #PSR_SVC32_MODE
#else
#define BACK_TO_SVC_MODE \
msr cpsr_all, r3
#endif
#else
#define BACK_TO_SVC_MODE ; \
teqp r1, #0 ; \
@ -84,10 +94,16 @@
ENTRY(fiq_getregs)
SWITCH_TO_FIQ_MODE
#ifdef __thumb__
stmia r0!, {r8-r12}
str sp, [r0]
#else
stmia r0, {r8-r13}
#endif
BACK_TO_SVC_MODE
RET
END(fiq_getregs)
/*
* fiq_setregs:
@ -98,10 +114,16 @@ ENTRY(fiq_getregs)
ENTRY(fiq_setregs)
SWITCH_TO_FIQ_MODE
#ifdef __thumb__
ldmia r0!, {r8-r12}
ldr sp, [r0]
#else
ldmia r0, {r8-r13}
#endif
BACK_TO_SVC_MODE
RET
END(fiq_setregs)
/*
* fiq_nullhandler:
@ -113,3 +135,4 @@ ENTRY(fiq_setregs)
_C_LABEL(fiq_nullhandler):
subs pc, lr, #4
_C_LABEL(fiq_nullhandler_end):
.size _C_LABEL(fiq_nullhandler), . - _C_LABEL(fiq_nullhandler)

28
sys/arch/arm/arm/fusu.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: fusu.S,v 1.2 2009/01/18 16:42:09 bjh21 Exp $ */
/* $NetBSD: fusu.S,v 1.3 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1996-1998 Mark Brinicombe.
@ -36,8 +36,10 @@
#include "opt_cpuoptions.h"
#include "assym.h"
#include <machine/asm.h>
#include <machine/cpu.h>
#include <arm/locore.h>
/*
* On PROG26 systems (i.e. acorn26) taking a page fault corrupts R14_svc.
@ -74,6 +76,7 @@ ENTRY(fuword)
str r1, [r2, #PCB_ONFAULT]
mov r0, r3
FUSU_RET
END(fuword)
/*
* fusword(void *uaddr);
@ -102,6 +105,7 @@ ENTRY(fusword)
mov r1, #0x00000000
str r1, [r2, #PCB_ONFAULT]
FUSU_RET
END(fusword)
/*
* fuswintr(void *uaddr);
@ -110,7 +114,7 @@ ENTRY(fusword)
*/
ENTRY(fuswintr)
ldr r2, Lblock_userspace_access
ldr r2, .Lblock_userspace_access
ldr r2, [r2]
teq r2, #0
mvnne r0, #0x00000000
@ -138,8 +142,9 @@ ENTRY(fuswintr)
mov r1, #0x00000000
str r1, [r2, #PCB_ONFAULT]
FUSU_RET
END(fuswintr)
Lblock_userspace_access:
.Lblock_userspace_access:
.word _C_LABEL(block_userspace_access)
.data
@ -182,6 +187,7 @@ ENTRY(fubyte)
str r0, [r2, #PCB_ONFAULT]
mvn r0, #0x00000000
FUSU_RET
END(fubyte)
/*
* Handle faults from [fs]u*(). Clean up and return -1. This differs from
@ -190,12 +196,12 @@ ENTRY(fubyte)
*/
/* label must be global as fault.c references it */
.global _C_LABEL(fusubailout)
_C_LABEL(fusubailout):
_ENTRY(fusubailout)
mov r0, #0x00000000
str r0, [r2, #PCB_ONFAULT]
mvn r0, #0x00000000
FUSU_RET
END(fusubailout)
#ifdef DIAGNOSTIC
/*
@ -204,10 +210,10 @@ _C_LABEL(fusubailout):
.Lfusupcbfault:
mov r1, r0
adr r0, fusupcbfaulttext
adr r0, .Lfusupcbfaulttext
b _C_LABEL(panic)
fusupcbfaulttext:
.Lfusupcbfaulttext:
.asciz "Yikes - no valid PCB during fusuxxx() addr=%08x\n"
.align 0
#endif
@ -234,6 +240,7 @@ ENTRY(suword)
mov r0, #0x00000000
str r0, [r2, #PCB_ONFAULT]
FUSU_RET
END(suword)
/*
* suswintr(void *uaddr, short x);
@ -242,7 +249,7 @@ ENTRY(suword)
*/
ENTRY(suswintr)
ldr r2, Lblock_userspace_access
ldr r2, .Lblock_userspace_access
ldr r2, [r2]
teq r2, #0
mvnne r0, #0x00000000
@ -271,6 +278,7 @@ ENTRY(suswintr)
mov r0, #0x00000000
str r0, [r2, #PCB_ONFAULT]
FUSU_RET
END(suswintr)
/*
* susword(void *uaddr, short x);
@ -301,6 +309,7 @@ ENTRY(susword)
mov r0, #0x00000000
str r0, [r2, #PCB_ONFAULT]
FUSU_RET
END(susword)
/*
* subyte(void *uaddr, char x);
@ -324,3 +333,4 @@ ENTRY(subyte)
mov r0, #0x00000000
str r0, [r2, #PCB_ONFAULT]
FUSU_RET
END(subyte)

7
sys/arch/arm/arm/idle_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: idle_machdep.c,v 1.4 2008/04/28 20:23:13 martin Exp $ */
/* $NetBSD: idle_machdep.c,v 1.5 2013/08/18 06:28:18 matt Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@ -31,11 +31,12 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: idle_machdep.c,v 1.4 2008/04/28 20:23:13 martin Exp $");
__KERNEL_RCSID(0, "$NetBSD: idle_machdep.c,v 1.5 2013/08/18 06:28:18 matt Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
#include <arm/cpufunc.h>
#include <arm/locore.h>
void
cpu_idle(void)

7
sys/arch/arm/arm/lock_cas.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: lock_cas.S,v 1.10 2013/08/11 04:40:05 matt Exp $ */
/* $NetBSD: lock_cas.S,v 1.11 2013/08/18 06:28:18 matt Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@ -33,8 +33,10 @@
#include "opt_arm_debug.h"
#include "assym.h"
#include <machine/asm.h>
#include <machine/cpu.h>
#include <arm/locore.h>
#if defined(MULTIPROCESSOR) && !defined(_ARM_ARCH_6)
#error need to write MP support for ucas_* functions
@ -142,6 +144,7 @@ _C_LABEL(ucas_32_ras_start):
strteq r2, [ip]
mov r0, #0
#endif
.size _C_LABEL(ucas_32_ras_start), . - _C_LABEL(ucas_32_ras_start)
.globl _C_LABEL(ucas_32_ras_end)
_C_LABEL(ucas_32_ras_end):

12
sys/arch/arm/arm/process_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: process_machdep.c,v 1.25 2012/12/08 06:46:49 matt Exp $ */
/* $NetBSD: process_machdep.c,v 1.26 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1993 The Regents of the University of California.
@ -133,18 +133,18 @@
#include <sys/param.h>
__KERNEL_RCSID(0, "$NetBSD: process_machdep.c,v 1.25 2012/12/08 06:46:49 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: process_machdep.c,v 1.26 2013/08/18 06:28:18 matt Exp $");
#include <sys/proc.h>
#include <sys/ptrace.h>
#include <sys/systm.h>
#include <machine/frame.h>
#include <machine/pcb.h>
#include <machine/reg.h>
#include <arm/armreg.h>
#include <arm/vfpreg.h>
#include <arm/locore.h>
#include <machine/pcb.h>
#include <machine/reg.h>
int
process_read_regs(struct lwp *l, struct reg *regs)

9
sys/arch/arm/arm/sig_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: sig_machdep.c,v 1.46 2013/03/04 23:12:52 matt Exp $ */
/* $NetBSD: sig_machdep.c,v 1.47 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@ -44,9 +44,10 @@
#include <sys/param.h>
__KERNEL_RCSID(0, "$NetBSD: sig_machdep.c,v 1.46 2013/03/04 23:12:52 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: sig_machdep.c,v 1.47 2013/08/18 06:28:18 matt Exp $");
#include <sys/mount.h> /* XXX only needed by syscallargs.h */
#include <sys/cpu.h>
#include <sys/proc.h>
#include <sys/signal.h>
#include <sys/syscallargs.h>
@ -54,10 +55,8 @@ __KERNEL_RCSID(0, "$NetBSD: sig_machdep.c,v 1.46 2013/03/04 23:12:52 matt Exp $"
#include <sys/ras.h>
#include <sys/ucontext.h>
#include <arm/armreg.h>
#include <arm/locore.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <machine/pcb.h>
#ifndef acorn26
#include <arm/cpufunc.h>

18
sys/arch/arm/arm/syscall.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: syscall.c,v 1.57 2013/06/26 06:31:53 matt Exp $ */
/* $NetBSD: syscall.c,v 1.58 2013/08/18 06:28:18 matt Exp $ */
/*-
* Copyright (c) 2000, 2003 The NetBSD Foundation, Inc.
@ -71,8 +71,9 @@
#include <sys/param.h>
__KERNEL_RCSID(0, "$NetBSD: syscall.c,v 1.57 2013/06/26 06:31:53 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: syscall.c,v 1.58 2013/08/18 06:28:18 matt Exp $");
#include <sys/cpu.h>
#include <sys/device.h>
#include <sys/errno.h>
#include <sys/kernel.h>
@ -85,9 +86,9 @@ __KERNEL_RCSID(0, "$NetBSD: syscall.c,v 1.57 2013/06/26 06:31:53 matt Exp $");
#include <uvm/uvm_extern.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <arm/swi.h>
#include <arm/locore.h>
#ifdef acorn26
#include <machine/machdep.h>
@ -141,12 +142,8 @@ swi_handler(trapframe_t *tf)
#ifdef THUMB_CODE
if (tf->tf_spsr & PSR_T_bit) {
/* Map a Thumb SWI onto the bottom 256 ARM SWIs. */
insn = fusword((void *)(tf->tf_pc - THUMB_INSN_SIZE));
if (insn & 0x00ff)
insn = (insn & 0x00ff) | 0xef000000;
else
insn = tf->tf_ip | 0xef000000;
insn = 0xef000000 | SWI_OS_NETBSD | tf->tf_r0;
tf->tf_r0 = tf->tf_ip;
}
else
#endif
@ -154,6 +151,9 @@ swi_handler(trapframe_t *tf)
/* XXX fuword? */
#ifdef __PROG32
insn = *(uint32_t *)(tf->tf_pc - INSN_SIZE);
#if defined(__ARMEB__) && defined(_ARM_ARCH_7)
insn = le32toh(insn); /* BE armv7 insn are in LE */
#endif
#else
insn = *(uint32_t *)((tf->tf_r15 & R15_PC) - INSN_SIZE);
#endif

30
sys/arch/arm/arm/undefined.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: undefined.c,v 1.48 2012/11/12 18:00:35 skrll Exp $ */
/* $NetBSD: undefined.c,v 1.49 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2001 Ben Harris.
@ -54,7 +54,7 @@
#include <sys/kgdb.h>
#endif
__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.48 2012/11/12 18:00:35 skrll Exp $");
__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.49 2013/08/18 06:28:18 matt Exp $");
#include <sys/kmem.h>
#include <sys/queue.h>
@ -71,12 +71,12 @@ __KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.48 2012/11/12 18:00:35 skrll Exp $")
#include <uvm/uvm_extern.h>
#include <machine/frame.h>
#include <arm/locore.h>
#include <arm/undefined.h>
#include <machine/pcb.h>
#include <machine/trap.h>
#include <arm/undefined.h>
#include <arch/arm/arm/disassem.h>
#ifdef DDB
@ -132,7 +132,7 @@ cp15_trapper(u_int addr, u_int insn, struct trapframe *frame, int code)
{
struct lwp * const l = curlwp;
#ifdef THUMB_CODE
#if defined(THUMB_CODE) && !defined(CPU_ARMV7)
if (frame->tf_spsr & PSR_T_bit)
return 1;
#endif
@ -303,7 +303,18 @@ undefinedinstruction(trapframe_t *frame)
#ifdef THUMB_CODE
if (frame->tf_spsr & PSR_T_bit) {
fault_instruction = fusword((void *)(fault_pc & ~1));
const uint16_t *pc = (const uint16_t *)(fault_pc & ~1);
fault_instruction = pc[0];
#if defined(__ARMEB__) && defined(_ARM_ARCH_7)
fault_instruction = le16toh(fault_instruction);
#endif
if (fault_instruction >= 0xe000) {
uint16_t tmp = pc[1];
#if defined(__ARMEB__) && defined(_ARM_ARCH_7)
tmp = le16toh(tmp);
#endif
fault_instruction = (fault_instruction << 16) | tmp;
}
}
else
#endif
@ -332,7 +343,10 @@ undefinedinstruction(trapframe_t *frame)
* not really matter does it ?
*/
fault_instruction = *(uint32_t *)fault_pc;
fault_instruction = *(const uint32_t *)fault_pc;
#if defined(__ARMEB__) && defined(_ARM_ARCH_7)
fault_instruction = le32toh(fault_instruction);
#endif
}
/* Update vmmeter statistics */

4
sys/arch/arm/arm/vectors.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: vectors.S,v 1.7 2013/06/12 21:34:12 matt Exp $ */
/* $NetBSD: vectors.S,v 1.8 2013/08/18 06:29:29 matt Exp $ */
/*
* Copyright (C) 1994-1997 Mark Brinicombe
@ -69,6 +69,7 @@ _C_LABEL(page0rel):
#elif !defined(ARM_HAS_VBAR)
b .Lfiqvector
#endif
END(page0rel)
#endif /* CPU_ARMV7 || CPU_ARM11 || ARM_HAS_VBAR */
#ifndef ARM_HAS_VBAR
@ -85,6 +86,7 @@ _C_LABEL(page0):
#ifdef __ARM_FIQ_INDIRECT
ldr pc, .Lfiq_target
#endif
END(page0)
#endif /* !ARM_HAS_VBAR */
#ifndef __ARM_FIQ_INDIRECT
.Lfiqvector:

5
sys/arch/arm/arm32/arm32_boot.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: arm32_boot.c,v 1.4 2013/06/12 07:14:26 matt Exp $ */
/* $NetBSD: arm32_boot.c,v 1.5 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved.
@ -123,7 +123,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.4 2013/06/12 07:14:26 matt Exp $");
__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.5 2013/08/18 06:28:18 matt Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@ -135,6 +135,7 @@ __KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.4 2013/06/12 07:14:26 matt Exp $");
#include <uvm/uvm_extern.h>
#include <arm/locore.h>
#include <arm/undefined.h>
#include <arm/arm32/machdep.h>

6
sys/arch/arm/arm32/arm32_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: arm32_machdep.c,v 1.95 2013/08/15 22:13:48 matt Exp $ */
/* $NetBSD: arm32_machdep.c,v 1.96 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.95 2013/08/15 22:13:48 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.96 2013/08/18 06:28:18 matt Exp $");
#include "opt_modular.h"
#include "opt_md.h"
@ -71,6 +71,8 @@ __KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.95 2013/08/15 22:13:48 matt Exp
#include <dev/cons.h>
#include <dev/mm.h>
#include <arm/locore.h>
#include <arm/arm32/katelib.h>
#include <arm/arm32/machdep.h>

5
sys/arch/arm/arm32/arm32_reboot.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: arm32_reboot.c,v 1.5 2013/05/11 07:38:42 skrll Exp $ */
/* $NetBSD: arm32_reboot.c,v 1.6 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved.
@ -122,7 +122,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: arm32_reboot.c,v 1.5 2013/05/11 07:38:42 skrll Exp $");
__KERNEL_RCSID(0, "$NetBSD: arm32_reboot.c,v 1.6 2013/08/18 06:28:18 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@ -133,6 +133,7 @@ __KERNEL_RCSID(0, "$NetBSD: arm32_reboot.c,v 1.5 2013/05/11 07:38:42 skrll Exp $
#include <uvm/uvm_extern.h>
#include <arm/locore.h>
#include <arm/arm32/machdep.h>
void

22
sys/arch/arm/arm32/bcopy_page.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: bcopy_page.S,v 1.8 2005/12/11 12:16:41 christos Exp $ */
/* $NetBSD: bcopy_page.S,v 1.9 2013/08/18 06:29:29 matt Exp $ */
/*
* Copyright (c) 1995 Scott Stevens
@ -73,8 +73,8 @@
#endif /* ! COPY_CHUNK */
#ifndef SAVE_REGS
#define SAVE_REGS stmfd sp!, {r4-r8, lr}
#define RESTORE_REGS ldmfd sp!, {r4-r8, pc}
#define SAVE_REGS push {r4-r8, lr}
#define RESTORE_REGS pop {r4-r8, pc}
#endif
ENTRY(bcopy_page)
@ -115,6 +115,7 @@ ENTRY(bcopy_page)
bne 1b
RESTORE_REGS /* ...and return. */
END(bcopy_page)
/*
* bzero_page(dest)
@ -130,7 +131,7 @@ ENTRY(bcopy_page)
*/
ENTRY(bzero_page)
stmfd sp!, {r4-r8, lr}
push {r4-r8, lr}
#ifdef BIG_LOOPS
mov r2, #(PAGE_SIZE >> 9)
#else
@ -175,7 +176,8 @@ ENTRY(bzero_page)
subs r2, r2, #1
bne 1b
ldmfd sp!, {r4-r8, pc}
pop {r4-r8, pc}
END(bzero_page)
#else /* __XSCALE__ */
@ -184,7 +186,7 @@ ENTRY(bzero_page)
*/
ENTRY(bcopy_page)
pld [r0]
stmfd sp!, {r4, r5}
push {r4, r5}
mov ip, #32
ldr r2, [r0], #0x04 /* 0x00 */
ldr r3, [r0], #0x04 /* 0x04 */
@ -242,8 +244,9 @@ ENTRY(bcopy_page)
ldrgt r3, [r0], #0x04 /* 0x84 */
strd r4, [r1], #0x08
bgt 1b
ldmfd sp!, {r4, r5}
mov pc, lr
pop {r4, r5}
RET
END(bcopy_page)
/*
* XSCALE version of bzero_page
@ -270,5 +273,6 @@ ENTRY(bzero_page)
strd r2, [r0], #8
subs r1, r1, #128
bne 1b
mov pc, lr
RET
END(bzero_page)
#endif /* __XSCALE__ */

6
sys/arch/arm/arm32/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.96 2013/06/12 01:16:48 matt Exp $ */
/* $NetBSD: cpu.c,v 1.97 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@ -46,7 +46,7 @@
#include <sys/param.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.96 2013/06/12 01:16:48 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.97 2013/08/18 06:28:18 matt Exp $");
#include <sys/systm.h>
#include <sys/conf.h>
@ -57,7 +57,7 @@ __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.96 2013/06/12 01:16:48 matt Exp $");
#include <uvm/uvm_extern.h>
#include <arm/cpuconf.h>
#include <arm/locore.h>
#include <arm/undefined.h>
char cpu_model[256];

22
sys/arch/arm/arm32/cpuswitch.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpuswitch.S,v 1.77 2013/02/27 17:52:44 matt Exp $ */
/* $NetBSD: cpuswitch.S,v 1.78 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@ -88,7 +88,7 @@
#include <machine/cpu.h>
#include <machine/frame.h>
RCSID("$NetBSD: cpuswitch.S,v 1.77 2013/02/27 17:52:44 matt Exp $")
RCSID("$NetBSD: cpuswitch.S,v 1.78 2013/08/18 06:28:18 matt Exp $")
/* LINTSTUB: include <sys/param.h> */
@ -133,7 +133,7 @@
*/
ENTRY(cpu_switchto)
mov ip, sp
stmfd sp!, {r4-r7, ip, lr}
push {r4-r7, ip, lr}
/* move lwps into caller saved registers */
mov r6, r1
@ -313,7 +313,7 @@ ENTRY(cpu_switchto)
* Pull the registers that got pushed when cpu_switchto() was called,
* and return.
*/
ldmfd sp, {r4-r7, sp, pc}
pop {r4-r7, ip, pc}
.Lswitch_do_ras:
ldr r1, [r1, #(TF_PC)] /* second ras_lookup() arg */
@ -323,6 +323,7 @@ ENTRY(cpu_switchto)
ldrne r1, [r6, #(L_MD_TF)]
strne r0, [r1, #(TF_PC)]
b .Lswitch_return
END(cpu_switchto)
ENTRY_NP(lwp_trampoline)
/*
@ -355,6 +356,7 @@ ENTRY_NP(lwp_trampoline)
PULLFRAME
movs pc, lr /* Exit */
END(lwp_trampoline)
AST_ALIGNMENT_FAULT_LOCALS
@ -365,7 +367,7 @@ AST_ALIGNMENT_FAULT_LOCALS
* r1 = ipl for softint_dispatch
*/
ENTRY_NP(softint_switch)
stmfd sp!, {r4, r6, r7, lr}
push {r4, r6, r7, lr}
ldr r7, [r0, #L_CPU] /* get curcpu */
#if defined(TPIDRPRW_IS_CURLWP)
@ -380,8 +382,8 @@ ENTRY_NP(softint_switch)
*/
mov r2, sp /* think ip */
adr r3, softint_tramp /* think lr */
stmfd sp!, {r2-r3}
stmfd sp!, {r4-r7}
push {r2-r3}
push {r4-r7}
mov r5, r0 /* save new lwp */
@ -451,8 +453,8 @@ ENTRY_NP(softint_switch)
/*
* Grab the registers that got pushed at the start and return.
*/
ldmfd sp!, {r4-r7, ip, lr} /* eat switch frame */
ldmfd sp!, {r4, r6, r7, pc} /* pop stack and return */
pop {r4-r7, ip, lr} /* eat switch frame */
pop {r4, r6, r7, pc} /* pop stack and return */
END(softint_switch)
@ -471,6 +473,6 @@ ENTRY_NP(softint_tramp)
str r3, [r0, #(L_CTXSWTCH)] /* the soft lwp blocked */
msr cpsr_c, r6 /* restore interrupts */
ldmfd sp!, {r4, r6, r7, pc} /* pop stack and return */
pop {r4, r6, r7, pc} /* pop stack and return */
END(softint_tramp)
#endif /* __HAVE_FAST_SOFTINTS */

78
sys/arch/arm/arm32/exception.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: exception.S,v 1.18 2012/09/12 23:06:15 matt Exp $ */
/* $NetBSD: exception.S,v 1.19 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
@ -46,11 +46,12 @@
*/
#include "assym.h"
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/frame.h>
RCSID("$NetBSD: exception.S,v 1.18 2012/09/12 23:06:15 matt Exp $")
#include <arm/asm.h>
#include <arm/locore.h>
RCSID("$NetBSD: exception.S,v 1.19 2013/08/18 06:28:18 matt Exp $")
.text
.align 0
@ -62,21 +63,22 @@ AST_ALIGNMENT_FAULT_LOCALS
*
* Handler for Reset exception.
*/
ASENTRY_NP(reset_entry)
adr r0, Lreset_panicmsg
ARM_ASENTRY_NP(reset_entry)
adr r0, .Lreset_panicmsg
mov r1, lr
bl _C_LABEL(panic)
/* NOTREACHED */
Lreset_panicmsg:
.Lreset_panicmsg:
.asciz "Reset vector called, LR = 0x%08x"
.balign 4
ASEND(reset_entry)
/*
* swi_entry
*
* Handler for the Software Interrupt exception.
*/
ASENTRY_NP(swi_entry)
ARM_ASENTRY_NP(swi_entry)
PUSHFRAME
ENABLE_ALIGNMENT_FAULTS
@ -86,13 +88,14 @@ ASENTRY_NP(swi_entry)
DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
PULLFRAME
movs pc, lr /* Exit */
ASEND(swi_entry)
/*
* prefetch_abort_entry:
*
* Handler for the Prefetch Abort exception.
*/
ASENTRY_NP(prefetch_abort_entry)
ARM_ASENTRY_NP(prefetch_abort_entry)
#ifdef __XSCALE__
nop /* Make absolutely sure any pending */
nop /* imprecise aborts have occurred. */
@ -102,28 +105,28 @@ ASENTRY_NP(prefetch_abort_entry)
PUSHFRAMEINSVC
ENABLE_ALIGNMENT_FAULTS
ldr r1, Lprefetch_abort_handler_address
adr lr, exception_exit
ldr r1, .Lprefetch_abort_handler_address
adr lr, .Lexception_exit
mov r0, sp /* pass the stack pointer as r0 */
ldr pc, [r1]
Lprefetch_abort_handler_address:
.Labortprefetch:
adr r0, .Labortprefetchmsg
b _C_LABEL(panic)
.Lprefetch_abort_handler_address:
.word _C_LABEL(prefetch_abort_handler_address)
.Labortprefetchmsg:
.asciz "abortprefetch"
.align 0
ASEND(prefetch_abort_entry)
.data
.p2align 2
.global _C_LABEL(prefetch_abort_handler_address)
_C_LABEL(prefetch_abort_handler_address):
.word abortprefetch
.text
abortprefetch:
adr r0, abortprefetchmsg
b _C_LABEL(panic)
abortprefetchmsg:
.asciz "abortprefetch"
.align 0
.word .Labortprefetch
/*
* data_abort_entry:
@ -141,28 +144,29 @@ ASENTRY_NP(data_abort_entry)
/* to SVC32 mode */
ENABLE_ALIGNMENT_FAULTS
ldr r1, Ldata_abort_handler_address
adr lr, exception_exit
ldr r1, .Ldata_abort_handler_address
adr lr, .Lexception_exit
mov r0, sp /* pass the stack pointer as r0 */
ldr pc, [r1]
Ldata_abort_handler_address:
.Ldata_abort_handler_address:
.word _C_LABEL(data_abort_handler_address)
.data
.p2align 2
.global _C_LABEL(data_abort_handler_address)
_C_LABEL(data_abort_handler_address):
.word abortdata
.word .Labortdata
.text
abortdata:
adr r0, abortdatamsg
.Labortdata:
adr r0, .Labortdatamsg
b _C_LABEL(panic)
abortdatamsg:
.Labortdatamsg:
.asciz "abortdata"
.align 0
ASEND(data_abort_entry)
/*
* address_exception_entry:
@ -177,10 +181,10 @@ ASENTRY_NP(address_exception_entry)
mrs r1, cpsr_all
mrs r2, spsr_all
mov r3, lr
adr r0, Laddress_exception_msg
adr r0, .Laddress_exception_msg
bl _C_LABEL(printf) /* XXX CLOBBERS LR!! */
b data_abort_entry
Laddress_exception_msg:
b _ASM_LABEL(data_abort_entry)
.Laddress_exception_msg:
.asciz "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n"
.balign 4
@ -199,9 +203,10 @@ Laddress_exception_msg:
* followed by ENABLE_ALIGNMENT_FAULTS.
*/
exception_exit:
.Lexception_exit:
DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
PULLFRAMEFROMSVCANDEXIT
ASEND(address_exception_entry)
/*
* undefined_entry:
@ -220,6 +225,7 @@ ASENTRY_NP(undefined_entry)
ldr r1, [sp], #0x0004
str r1, [r0, #0x0004]
ldmia r0, {r0, r1, pc}
ASEND(undefined_entry)
/*
* assembly bounce code for calling the kernel
@ -232,5 +238,7 @@ ENTRY_NP(undefinedinstruction_bounce)
ENABLE_ALIGNMENT_FAULTS
mov r0, sp
adr lr, exception_exit
adr lr, .Lexception_exit
b _C_LABEL(undefinedinstruction)
END(undefinedinstruction_bounce)
ASEND(undefined_entry)

8
sys/arch/arm/arm32/fault.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: fault.c,v 1.89 2013/07/02 05:50:53 matt Exp $ */
/* $NetBSD: fault.c,v 1.90 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@ -81,7 +81,7 @@
#include "opt_kgdb.h"
#include <sys/types.h>
__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.89 2013/07/02 05:50:53 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.90 2013/08/18 06:28:18 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -89,6 +89,7 @@ __KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.89 2013/07/02 05:50:53 matt Exp $");
#include <sys/kernel.h>
#include <sys/kauth.h>
#include <sys/cpu.h>
#include <sys/intr.h>
#include <uvm/uvm_extern.h>
#include <uvm/uvm_stat.h>
@ -96,11 +97,10 @@ __KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.89 2013/07/02 05:50:53 matt Exp $");
#include <uvm/uvm.h>
#endif
#include <arm/cpuconf.h>
#include <arm/locore.h>
#include <arm/arm32/katelib.h>
#include <machine/intr.h>
#include <machine/pcb.h>
#if defined(DDB) || defined(KGDB)
#include <machine/db_machdep.h>

18
sys/arch/arm/arm32/irq_dispatch.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: irq_dispatch.S,v 1.14 2012/10/21 10:29:53 matt Exp $ */
/* $NetBSD: irq_dispatch.S,v 1.15 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002 Fujitsu Component Limited
@ -70,8 +70,8 @@
#include "assym.h"
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <arm/locore.h>
#include "opt_arm_intr_impl.h"
#ifdef ARM_INTR_IMPL
@ -90,9 +90,8 @@
* which can be used by different platforms.
*/
.text
.p2align 5
ASENTRY_NP(irq_entry)
ARM_ASENTRY_NP(irq_entry)
sub lr, lr, #0x00000004 /* Adjust the lr */
PUSHFRAMEINSVC /* Push an interrupt frame */
@ -124,16 +123,20 @@ ASENTRY_NP(irq_entry)
DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
PULLFRAMEFROMSVCANDEXIT
#ifdef __thumb__
subs pc, lr, #0 /* Exit */
#else
movs pc, lr /* Exit */
#endif
.align 0
LOCK_CAS_CHECK_LOCALS
AST_ALIGNMENT_FAULT_LOCALS
ASEND(irq_entry)
.p2align 5
ASENTRY_NP(irq_idle_entry)
ARM_ASENTRY_NP(irq_idle_entry)
PUSHIDLEFRAME
/*
@ -171,3 +174,4 @@ ASENTRY_NP(irq_idle_entry)
bne _C_LABEL(dosoftints) /* dosoftints(void) */
#endif
RET
ASEND(irq_idle_entry)

25
sys/arch/arm/arm32/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.32 2013/06/17 04:41:30 matt Exp $ */
/* $NetBSD: locore.S,v 1.33 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (C) 1994-1997 Mark Brinicombe
@ -34,14 +34,13 @@
#include "assym.h"
#include <sys/syscall.h>
#include <sys/errno.h>
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <arm/asm.h>
#include <arm/locore.h>
/* What size should this really be ? It is only used by init_arm() */
#define INIT_ARM_STACK_SIZE 2048
RCSID("$NetBSD: locore.S,v 1.32 2013/06/17 04:41:30 matt Exp $")
RCSID("$NetBSD: locore.S,v 1.33 2013/08/18 06:28:18 matt Exp $")
/*
* This is for kvm_mkdb, and should be the address of the beginning
@ -91,7 +90,7 @@ ASENTRY_NP(start)
mov fp, #0x00000000 /* trace back starts here */
mov ip, sp
stmfd sp!, {fp, ip, lr, pc}
push {fp, ip, lr, pc}
sub fp, ip, #4
bl _C_LABEL(main) /* call main()! */
@ -113,6 +112,7 @@ ASENTRY_NP(start)
.Lmainreturned:
.asciz "main() returned"
.align 0
ASEND(start)
.bss
svcstk:
@ -176,6 +176,7 @@ ENTRY_NP(cpu_reset)
.word _C_LABEL(cpu_reset_address)
.Lcpu_reset_address_paddr:
.word _C_LABEL(cpu_reset_address_paddr)
END(cpu_reset)
#endif /* OFW */
/*
@ -184,12 +185,14 @@ ENTRY_NP(cpu_reset)
ENTRY(setjmp)
stmia r0, {r4-r14}
mov r0, #0x00000000
mov pc, lr
RET
END(setjmp)
ENTRY(longjmp)
ldmia r0, {r4-r14}
mov r0, #0x00000001
mov pc, lr
RET
END(longjmp)
.data
.global _C_LABEL(esym)
@ -197,6 +200,7 @@ _C_LABEL(esym): .word _C_LABEL(end)
ENTRY_NP(abort)
b _C_LABEL(abort)
END(abort)
/*
* Part of doing a system dump, we need to save a switchframe onto the
@ -205,7 +209,7 @@ ENTRY_NP(abort)
ENTRY(dumpsys)
/* push registers onto stack */
mov ip, sp
stmfd sp!, {r4-r7, ip, lr}
push {r4-r7, ip, lr}
/* fill in dumppcb */
ldr r0, .Ldumppcb
@ -222,9 +226,10 @@ ENTRY(dumpsys)
bl _C_LABEL(dodumpsys)
/* unwind the stack */
ldmfd sp, {r4-r7, sp, pc}
pop {r4-r7, ip, pc}
.Ldumppcb:
.word _C_LABEL(dumppcb)
END(dumpsys)
/* End of locore.S */

10
sys/arch/arm/arm32/setcpsr.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: setcpsr.S,v 1.2 2002/08/15 01:37:02 briggs Exp $ */
/* $NetBSD: setcpsr.S,v 1.3 2013/08/18 06:29:29 matt Exp $ */
/*
* Copyright (c) 1994 Mark Brinicombe.
@ -63,7 +63,8 @@ ENTRY_NP(SetCPSR)
mov r0, r3 /* Return the old CPSR */
mov pc, lr
RET
END(SetCPSR)
/* Gets the CPSR register
@ -73,6 +74,5 @@ ENTRY_NP(SetCPSR)
ENTRY_NP(GetCPSR)
mrs r0, cpsr /* Get the CPSR */
mov pc, lr
RET
END(GetCPSR)

12
sys/arch/arm/arm32/setstack.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: setstack.S,v 1.5 2012/02/16 02:35:52 christos Exp $ */
/* $NetBSD: setstack.S,v 1.6 2013/08/18 06:29:29 matt Exp $ */
/*
* Copyright (c) 1994 Mark Brinicombe.
@ -49,7 +49,7 @@
#include <arm/armreg.h>
#include <machine/asm.h>
RCSID("$NetBSD: setstack.S,v 1.5 2012/02/16 02:35:52 christos Exp $")
RCSID("$NetBSD: setstack.S,v 1.6 2013/08/18 06:29:29 matt Exp $")
/* To set the stack pointer for a particular mode we must switch
* to that mode update the banked r13 and then switch back.
@ -69,7 +69,8 @@ ENTRY(set_stackptr)
msr cpsr_c, r3 /* Restore the old mode */
mov pc, lr /* Exit */
RET /* Exit */
END(set_stackptr)
/* To get the stack pointer for a particular mode we must switch
* to that mode copy the banked r13 and then switch back.
@ -84,10 +85,11 @@ ENTRY(get_stackptr)
orr r2, r2, r0
msr cpsr_c, r2
mov r0, sp /* Set the stack pointer */
mov r0, sp /* Get the stack pointer */
msr cpsr_c, r3 /* Restore the old mode */
mov pc, lr /* Exit */
RET /* Exit */
END(get_stackptr)
/* End of setstack.S */

8
sys/arch/arm/arm32/spl.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: spl.S,v 1.8 2008/04/27 18:58:44 matt Exp $ */
/* $NetBSD: spl.S,v 1.9 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1996-1998 Mark Brinicombe.
@ -39,11 +39,11 @@
*/
#include "assym.h"
#include <arm/asm.h>
#include <arm/locore.h>
#include <arm/arm32/psl.h>
#include <machine/asm.h>
#include <machine/cpu.h>
RCSID("$NetBSD: spl.S,v 1.8 2008/04/27 18:58:44 matt Exp $")
RCSID("$NetBSD: spl.S,v 1.9 2013/08/18 06:28:18 matt Exp $")
.text
.align 0

5
sys/arch/arm/arm32/sys_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: sys_machdep.c,v 1.16 2013/01/31 14:58:51 matt Exp $ */
/* $NetBSD: sys_machdep.c,v 1.17 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1995-1997 Mark Brinicombe.
@ -41,7 +41,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: sys_machdep.c,v 1.16 2013/01/31 14:58:51 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: sys_machdep.c,v 1.17 2013/08/18 06:28:18 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -56,6 +56,7 @@ __KERNEL_RCSID(0, "$NetBSD: sys_machdep.c,v 1.16 2013/01/31 14:58:51 matt Exp $"
#include <machine/sysarch.h>
#include <machine/pcb.h>
#include <arm/vfpreg.h>
#include <arm/locore.h>
/* Prototypes */
static int arm32_sync_icache(struct lwp *, const void *, register_t *);

156
sys/arch/arm/include/cpu.h
View File

@ -66,76 +66,17 @@
* Kernel-only definitions
*/
#if !defined(_LKM) && defined(_KERNEL_OPT)
#if !defined(_MODULE) && defined(_KERNEL_OPT)
#include "opt_multiprocessor.h"
#include "opt_cpuoptions.h"
#include "opt_lockdebug.h"
#include "opt_cputypes.h"
#endif /* !_LKM && _KERNEL_OPT */
#include <arm/cpuconf.h>
#ifndef _LOCORE
#include <machine/frame.h>
#endif /* !_LOCORE */
#include <arm/armreg.h>
#endif /* !_MODULE && _KERNEL_OPT */
#ifndef _LOCORE
/* 1 == use cpu_sleep(), 0 == don't */
extern int cpu_do_powersave;
extern int cpu_fpu_present;
#endif
#ifdef _LOCORE
#if defined(_ARM_ARCH_6)
#define IRQdisable cpsid i
#define IRQenable cpsie i
#elif defined(__PROG32)
#define IRQdisable \
stmfd sp!, {r0} ; \
mrs r0, cpsr ; \
orr r0, r0, #(I32_bit) ; \
msr cpsr_c, r0 ; \
ldmfd sp!, {r0}
#define IRQenable \
stmfd sp!, {r0} ; \
mrs r0, cpsr ; \
bic r0, r0, #(I32_bit) ; \
msr cpsr_c, r0 ; \
ldmfd sp!, {r0}
#else
/* Not yet used in 26-bit code */
#endif
#if defined (TPIDRPRW_IS_CURCPU)
#define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4
#define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
#elif defined (TPIDRPRW_IS_CURLWP)
#define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4
#define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU]
#elif !defined(MULTIPROCESSOR)
#define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store)
#define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
#endif
#define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB]
#else /* !_LOCORE */
#ifdef __PROG32
#define IRQdisable __set_cpsr_c(I32_bit, I32_bit);
#define IRQenable __set_cpsr_c(I32_bit, 0);
#else
#define IRQdisable set_r15(R15_IRQ_DISABLE, R15_IRQ_DISABLE);
#define IRQenable set_r15(R15_IRQ_DISABLE, 0);
#endif
#endif /* !_LOCORE */
#ifndef _LOCORE
/* All the CLKF_* macros take a struct clockframe * as an argument. */
@ -144,20 +85,20 @@ extern int cpu_fpu_present;
* frame came from USR mode or not.
*/
#ifdef __PROG32
#define CLKF_USERMODE(frame) ((frame->cf_tf.tf_spsr & PSR_MODE) == PSR_USR32_MODE)
#define CLKF_USERMODE(cf) (((cf)->cf_tf.tf_spsr & PSR_MODE) == PSR_USR32_MODE)
#else
#define CLKF_USERMODE(frame) ((frame->cf_if.if_r15 & R15_MODE) == R15_MODE_USR)
#define CLKF_USERMODE(cf) (((cf)->cf_if.if_r15 & R15_MODE) == R15_MODE_USR)
#endif
/*
* CLKF_INTR: True if we took the interrupt from inside another
* interrupt handler.
*/
#ifdef __PROG32
#if defined(__PROG32) && !defined(__ARM_EABI__)
/* Hack to treat FPE time as interrupt time so we can measure it */
#define CLKF_INTR(frame) \
((curcpu()->ci_intr_depth > 1) || \
(frame->cf_tf.tf_spsr & PSR_MODE) == PSR_UND32_MODE)
#define CLKF_INTR(cf) \
((curcpu()->ci_intr_depth > 1) || \
((cf)->cf_tf.tf_spsr & PSR_MODE) == PSR_UND32_MODE)
#else
#define CLKF_INTR(frame) (curcpu()->ci_intr_depth > 1)
#endif
@ -180,41 +121,6 @@ extern int cpu_fpu_present;
#define LWP_PC(l) (lwp_trapframe(l)->tf_r15 & R15_PC)
#endif
/*
* Validate a PC or PSR for a user process. Used by various system calls
* that take a context passed by the user and restore it.
*/
#ifdef __PROG32
#define VALID_R15_PSR(r15,psr) \
(((psr) & PSR_MODE) == PSR_USR32_MODE && \
((psr) & (I32_bit | F32_bit)) == 0)
#else
#define VALID_R15_PSR(r15,psr) \
(((r15) & R15_MODE) == R15_MODE_USR && \
((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0)
#endif
/* The address of the vector page. */
extern vaddr_t vector_page;
#ifdef __PROG32
void arm32_vector_init(vaddr_t, int);
#define ARM_VEC_RESET (1 << 0)
#define ARM_VEC_UNDEFINED (1 << 1)
#define ARM_VEC_SWI (1 << 2)
#define ARM_VEC_PREFETCH_ABORT (1 << 3)
#define ARM_VEC_DATA_ABORT (1 << 4)
#define ARM_VEC_ADDRESS_EXCEPTION (1 << 5)
#define ARM_VEC_IRQ (1 << 6)
#define ARM_VEC_FIQ (1 << 7)
#define ARM_NVEC 8
#define ARM_VEC_ALL 0xffffffff
#endif
/*
* Per-CPU information. For now we assume one CPU.
*/
@ -222,9 +128,9 @@ static inline int curcpl(void);
static inline void set_curcpl(int);
static inline void cpu_dosoftints(void);
#include <sys/cpu_data.h>
#include <sys/device_if.h>
#include <sys/evcnt.h>
#include <sys/cpu_data.h>
struct cpu_info {
struct cpu_data ci_data; /* MI per-cpu data */
@ -239,19 +145,15 @@ struct cpu_info {
int ci_want_resched; /* resched() was called */
int ci_intr_depth; /* */
struct cpu_softc *ci_softc; /* platform softc */
#ifdef __HAVE_FAST_SOFTINTS
lwp_t *ci_softlwps[SOFTINT_COUNT];
volatile uint32_t ci_softints;
#endif
lwp_t *ci_curlwp; /* current lwp */
struct evcnt ci_arm700bugcount;
int32_t ci_mtx_count;
int ci_mtx_oldspl;
register_t ci_undefsave[3];
uint32_t ci_vfp_id;
#if defined(_ARM_ARCH_7)
uint64_t ci_lastintr;
#endif
struct evcnt ci_abt_evs[FAULT_TYPE_MASK+1];
#if defined(MP_CPU_INFO_MEMBERS)
MP_CPU_INFO_MEMBERS
@ -259,6 +161,7 @@ struct cpu_info {
};
extern struct cpu_info cpu_info_store;
#if defined(TPIDRPRW_IS_CURLWP)
static inline struct lwp *
_curlwp(void)
@ -376,44 +279,7 @@ vaddr_t cpu_uarea_alloc_idlelwp(struct cpu_info *);
void cpu_attach(device_t, cpuid_t);
#endif
/*
* Random cruft
*/
struct lwp;
/* locore.S */
void atomic_set_bit(u_int *, u_int);
void atomic_clear_bit(u_int *, u_int);
/* cpuswitch.S */
struct pcb;
void savectx(struct pcb *);
/* ast.c */
void userret(register struct lwp *);
/* *_machdep.c */
void bootsync(void);
/* fault.c */
int badaddr_read(void *, size_t, void *);
/* syscall.c */
void swi_handler(trapframe_t *);
/* arm_machdep.c */
void ucas_ras_check(trapframe_t *);
/* vfp_init.c */
void vfp_attach(void);
void vfp_discardcontext(void);
void vfp_savecontext(void);
void vfp_kernel_acquire(void);
void vfp_kernel_release(void);
extern const pcu_ops_t arm_vfp_ops;
#endif /* !_LOCORE */
#endif /* !_LOCORE */
#endif /* _KERNEL */

8
sys/arch/arm/iomd/iomd_fiq.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: iomd_fiq.S,v 1.3 2013/08/12 16:07:03 matt Exp $ */
/* $NetBSD: iomd_fiq.S,v 1.4 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@ -41,8 +41,8 @@
* Created : 27/09/94
*/
#include <machine/asm.h>
#include <machine/cpu.h>
#include <arm/asm.h>
#include <arm/locore.h>
/*
@ -76,6 +76,7 @@ ENTRY_NP(floppy_read_fiq)
bne _C_LABEL(floppy_read_fiq)
#endif
subs pc, lr, #0x00000004
END(_floppy_read_fiq)
.global _C_LABEL(floppy_read_fiq_end)
_C_LABEL(floppy_read_fiq_end):
@ -106,6 +107,7 @@ ENTRY_NP(floppy_write_fiq)
bne _C_LABEL(floppy_write_fiq)
#endif
subs pc, lr, #0x00000004
END(floppy_write_fiq)
.global _C_LABEL(floppy_write_fiq_end)
_C_LABEL(floppy_write_fiq_end):

7
sys/arch/arm/iomd/iomd_irq.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: iomd_irq.S,v 1.14 2012/08/29 07:06:27 matt Exp $ */
/* $NetBSD: iomd_irq.S,v 1.15 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@ -42,9 +42,8 @@
#include "opt_irqstats.h"
#include "assym.h"
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <arm/asm.h>
#include <arm/locore.h>
#include <arm/iomd/iomdreg.h>
.text

31
sys/arch/arm/mainbus/mainbus_io_asm.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus_io_asm.S,v 1.1 2001/02/24 19:38:02 reinoud Exp $ */
/* $NetBSD: mainbus_io_asm.S,v 1.2 2013/08/18 06:29:29 matt Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
@ -45,17 +45,20 @@
ENTRY(mainbus_bs_r_1)
ldrb r0, [r1, r2, lsl #2]
mov pc, lr
RET
END(mainbus_bs_r_1)
ENTRY(mainbus_bs_r_2)
ldr r0, [r1, r2, lsl #2]
bic r0, r0, #0xff000000
bic r0, r0, #0x00ff0000
mov pc, lr
RET
END(mainbus_bs_r_2)
ENTRY(mainbus_bs_r_4)
ldr r0, [r1, r2, lsl #2]
mov pc, lr
RET
END(mainbus_bs_r_4)
/*
* write single
@ -63,17 +66,20 @@ ENTRY(mainbus_bs_r_4)
ENTRY(mainbus_bs_w_1)
strb r3, [r1, r2, lsl #2]
mov pc, lr
RET
END(mainbus_bs_w_1)
ENTRY(mainbus_bs_w_2)
mov r3, r3, lsl #16
orr r3, r3, r3, lsr #16
str r3, [r1, r2, lsl #2]
mov pc, lr
RET
END(mainbus_bs_w_2)
ENTRY(mainbus_bs_w_4)
str r3, [r1, r2, lsl #2]
mov pc, lr
RET
END(mainbus_bs_w_4)
/*
* read multiple
@ -84,6 +90,7 @@ ENTRY(mainbus_bs_rm_2)
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(insw16)
END(mainbus_bs_rm_2)
/*
* write multiple
@ -95,18 +102,20 @@ ENTRY(mainbus_bs_wm_1)
/* Make sure that we have a positive length */
cmp r2, #0x00000000
movle pc, lr
RETc(le)
mainbus_wm_1_loop:
.Lmainbus_wm_1_loop:
ldrb r1, [r3], #0x0001
str r1, [r0]
subs r2, r2, #0x00000001
bgt mainbus_wm_1_loop
bgt .Lmainbus_wm_1_loop
mov pc, lr
RET
END(mainbus_bs_wm_1)
ENTRY(mainbus_bs_wm_2)
add r0, r1, r2, lsl #2
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(outsw16)
END(mainbus_bs_wm_2)

8
sys/arch/arm/ofw/ofw_irq.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: ofw_irq.S,v 1.13 2012/08/29 07:06:27 matt Exp $ */
/* $NetBSD: ofw_irq.S,v 1.14 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@ -40,9 +40,9 @@
*/
#include "assym.h"
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <arm/asm.h>
#include <arm/locore.h>
#include <machine/irqhandler.h>
.text

24
sys/arch/arm/omap/omap_nobyteacc_io.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: omap_nobyteacc_io.S,v 1.2 2012/08/20 12:38:29 matt Exp $ */
/* $NetBSD: omap_nobyteacc_io.S,v 1.3 2013/08/18 06:28:18 matt Exp $ */
/*
* Redistribution and use in source and binary forms, with or without
@ -32,17 +32,31 @@
ENTRY(nobyteacc_bs_w_1)
tst r2, #1 /* even or odd byte offset? */
#ifndef _ARM_ARCH_7
andeq r3, r3, #0x00ff /* mask out junk in hi bytes */
lslne r3, r3, #8 /* odd: or data shifted to hi byte */
#endif
bic r2, r2, #1 /* halfword-align offset */
add r1, r1, r2 /* halfword address */
mrs r2, cpsr /* r2 = old interrupt state */
#ifdef _ARM_ARCH_6
cpsid if /* interrupts off */
#else
orr r0, r2, #(I32_bit | F32_bit) /* interrupts off */
msr cpsr, r0
#endif
ldrh r0, [r1] /* read the halfword */
andeq r0, r0, #0xff00 /* even: preserve existing hi byte */
andeq r3, r3, #0x00ff /* even: mask junk in new hi byte */
orreq r0, r0, r3 /* even: or in new data in lo byte */
#ifdef __thumb__
ite eq
#endif
#ifdef _ARM_ARCH_7
bfieq r0, r3, #0, #8 /* even: insert new data in lo byte */
bfine r0, r3, #8, #8 /* even: insert new data in hi byte */
#else
biceq r0, r0, #0x00ff /* even: preserve existing hi byte */
andne r0, r0, #0x00ff /* odd: preserve existing lo byte */
orrne r0, r0, r3, lsl #8 /* odd: or data shifted to hi byte */
orr r0, r0, r3 /* or in data */
#endif
strh r0, [r1] /* store back halfword */
msr cpsr, r2 /* restore interrupts */
RET

8
sys/arch/arm/sa11x0/sa11x0_irq.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: sa11x0_irq.S,v 1.16 2012/08/29 07:06:27 matt Exp $ */
/* $NetBSD: sa11x0_irq.S,v 1.17 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 1998 Mark Brinicombe.
@ -40,9 +40,9 @@
#include "opt_irqstats.h"
#include "assym.h"
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <arm/asm.h>
#include <arm/locore.h>
#include <arm/sa11x0/sa11x0_reg.h>

3
sys/arch/arm/vfp/vfp_init.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: vfp_init.c,v 1.22 2013/08/03 20:16:44 matt Exp $ */
/* $NetBSD: vfp_init.c,v 1.23 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@ -36,6 +36,7 @@
#include <sys/proc.h>
#include <sys/cpu.h>
#include <arm/locore.h>
#include <arm/pcb.h>
#include <arm/undefined.h>
#include <arm/vfpreg.h>

7
sys/arch/arm/xscale/i80200_irq.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: i80200_irq.S,v 1.16 2008/04/27 18:58:45 matt Exp $ */
/* $NetBSD: i80200_irq.S,v 1.17 2013/08/18 06:28:18 matt Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@ -38,9 +38,8 @@
#include "assym.h"
#include "opt_perfctrs.h"
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <arm/asm.h>
#include <arm/locore.h>
#include <arm/xscale/i80200reg.h>

4
sys/arch/arm/xscale/pxa2x0_apm_asm.S
View File

@ -16,8 +16,8 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <machine/asm.h>
#include <machine/cpu.h>
#include <arm/asm.h>
#include <arm/locore.h>
#include <arch/arm/xscale/pxa2x0reg.h>
#include <arch/arm/sa11x0/sa11x0_reg.h>