Some changes to bring back exynos4 support and make exynos5 support more
modern/generic - Provide a exynos_platform_early_putchar based on CONSADDR and remove EXYNOS_CONSOLE_EARLY - Provide devmaps for exynos4 and exynos5 - Simplify exynos_bootstrap - Update exynos_start.S to use exynos_platform_early_putchar - this needs a fix in a9_subr.S for arm_cpuinit to save lr in a callee save register and not use ip. Maybe this change is safe now, but too much testing required to commit it now.
This commit is contained in:
skrll
parent
66f17364ec
commit
aa08d109a0
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/* $NetBSD: exynos4_reg.h,v 1.15 2018/08/19 07:27:33 skrll Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Reinoud Zandijk.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_SAMSUNG_EXYNOS4_REG_H_
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#define _ARM_SAMSUNG_EXYNOS4_REG_H_
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/*
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* Physical memory layout of Exynos SoCs as per documentation
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*
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* Base Address Limit Address Size Description
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* 0x00000000 0x00010000 64 KB iROM
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* 0x02000000 0x02010000 64 KB iROM (mirror of 0x0 to 0x10000)
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* 0x02020000 0x02060000 256 KB iRAM
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* 0x03000000 0x03020000 128 KB Data memory or general purpose of Samsung
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* Reconfigurable Processor SRP.
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* 0x03020000 0x03030000 64 KB I-cache or general purpose of SRP.
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* 0x03030000 0x03039000 36 KB Configuration memory (write only) of SRP
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* 0x03810000 0x03830000 AudioSS's SFR region
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* 0x04000000 0x05000000 16 MB Bank0 of Static ROM Controller (SMC)
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* (16-bit only)
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* 0x05000000 0x06000000 16 MB Bank1 of SMC
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* 0x06000000 0x07000000 16 MB Bank2 of SMC
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* 0x07000000 0x08000000 16 MB Bank3 of SMC
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* 0x08000000 0x0C000000 64 MB Reserved
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* 0x0C000000 0x0CD00000 Reserved
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* 0x0CE00000 0x0D000000 SFR region of Nand Flash Contr. (NFCON)
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* 0x10000000 0x14000000 SFR region
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* 0x40000000 0xA0000000 1.5 GB Memory of Dynamic Memory Contr. (DMC)-0
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* 0xA0000000 0x00000000 1.5 GB Memory of DMC-1
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*/
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/*
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*
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* The exynos can boot from its iROM or from an external Nand memory. Since
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* these are normally hardly used they are excluded from the normal register
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* space here.
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*
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* XXX What about the audio subsystem region. Where are the docs?
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*
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* EXYNOS_CORE_PBASE points to the main SFR region.
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*
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* Notes:
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*
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* SFR Special Function Register
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* ISP In-System Programming, like a JTAG
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* ACP Accelerator Coherency Port
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* SSS Security Sub System
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* GIC Generic Interurrupt Controller
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* PMU Power Management Unit
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* DMC 2D Graphics engine
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* LEFTBUS Data bus / Peripheral bus
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* RIGHTBUS ,,
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* G3D 3D Graphics engine
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* MFC Multi-Format Codec
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* LCD0 LCD display
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* MCT Multi Core Timer
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* CMU Clock Management Unit
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* TMU Thermal Management Unit
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* PPMU Pin Parametric Measurement Unit (?)
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* MMU Memory Management Unit
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* MCTimer ?
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* WDT Watch Dog Timer
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* RTC Real Time Clock
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* KEYIF Keypad interface
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* SECKEY ?
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* TZPC TrustZone Protection Controller
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* UART Universal asynchronous receiver/transmitter
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* I2C Inter IC Connect
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* SPI Serial Peripheral Interface Bus
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* I2S Inter-IC Sound, Integrated Interchip Sound, or IIS
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* PCM Pulse-code modulation, audio stream at set fixed rate
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* SPDIF Sony/Philips Digital Interface Format
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* Slimbus Serial Low-power Inter-chip Media Bus
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* SMMU System mmu. No idea as how its programmed (or not)
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* PERI-L UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus
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* PERI-R CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF,
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* SECKEY, TZPC
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*/
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/*
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* Note that this table is not 80-char friendly, this is done to allow more
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* elaborate comments to clarify the register offsets use
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*/
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/* CORE */
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#define EXYNOS4_CORE_SIZE 0x04000000
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#define EXYNOS4_SDRAM_PBASE 0x40000000
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#define EXYNOS4_SYSREG_OFFSET 0x00010000
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#define EXYNOS4_PMU_OFFSET 0x00020000 /* Power Management Unit */
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#define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* Clock(s) management unit */
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#define EXYNOS4_CMU_EPLL 0x0003C010 /* Audio and ext. interf. clock */
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#define EXYNOS4_CMU_VPLL 0x0003C020 /* Video core (dither?) clock */
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#define EXYNOS4_CMU_CORE_ISP_PART_OFFSET 0x00040000 /* Clock(s) management unit */
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#define EXYNOS4_CMU_MPLL 0x00040008 /* MEM cntr. clock */
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#define EXYNOS4_CMU_APLL 0x00044000 /* ARM core clock */
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#define EXYNOS4_MCT_OFFSET 0x00050000 /* Multi Core Timer */
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#define EXYNOS4_WDT_OFFSET 0x00060000 /* Watch Dog Timer */
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#define EXYNOS4_RTC_OFFSET 0x00070000 /* Real Time Clock */
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#define EXYNOS4_KEYIF_OFFSET 0x000A0000 /* Keypad interface */
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#define EXYNOS4_HDMI_CEC_OFFSET 0x000B0000 /* HDMI Consumer Electronic Control */
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#define EXYNOS4_TMU_OFFSET 0x000C0000 /* Thermal Managment */
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#define EXYNOS4_SECKEY_OFFSET 0x00100000 /* XXX unknown XXX */
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#define EXYNOS4_TZPC0_OFFSET 0x00110000 /* ARM Trusted Zone Protection Controller */
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#define EXYNOS4_TZPC1_OFFSET 0x00120000
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#define EXYNOS4_TZPC2_OFFSET 0x00130000
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#define EXYNOS4_TZPC3_OFFSET 0x00140000
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#define EXYNOS4_TZPC4_OFFSET 0x00150000
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#define EXYNOS4_TZPC5_OFFSET 0x00160000
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#define EXYNOS4_INTCOMBINER_OFFSET 0x00440000 /* combines first 32 interrupt sources */
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#define EXYNOS4_GIC_CNTR_OFFSET 0x00480000 /* generic interrupt controller offset */
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#define EXYNOS4_GIC_DISTRIBUTOR_OFFSET 0x00490000
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#define EXYNOS4_AP_C2C_OFFSET 0x00540000 /* Chip 2 Chip XXX doc? XXX */
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#define EXYNOS4_CP_C2C_MODEM_OFFSET 0x00580000
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#define EXYNOS4_DMC0_OFFSET 0x00600000 /* Dynamic Memory Controller */
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#define EXYNOS4_DMC1_OFFSET 0x00610000
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#define EXYNOS4_PPMU_DMC_L_OFFSET 0x006A0000 /* event counters XXX ? */
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#define EXYNOS4_PPMU_DMC_R_OFFSET 0x006B0000
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#define EXYNOS4_PPMU_CPU_OFFSET 0x006C0000
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#define EXYNOS4_GPIO_C2C_OFFSET 0x006E0000
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#define EXYNOS4_TZASC_LR_OFFSET 0x00700000 /* trust zone access control */
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#define EXYNOS4_TZASC_LW_OFFSET 0x00710000
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#define EXYNOS4_TZASC_RR_OFFSET 0x00720000
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#define EXYNOS4_TZASC_RW_OFFSET 0x00730000
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#define EXYNOS4_G2D_ACP_OFFSET 0x00800000 /* 2D graphics engine */
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#define EXYNOS4_SSS_OFFSET 0x00830000 /* Security Sub System */
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#define EXYNOS4_CORESIGHT_1_OFFSET 0x00880000 /* 1st region */
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#define EXYNOS4_CORESIGHT_2_OFFSET 0x00890000 /* 2nd region */
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#define EXYNOS4_CORESIGHT_3_OFFSET 0x008B0000 /* 3rd region */
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#define EXYNOS4_SMMUG2D_ACP_OFFSET 0x00A40000 /* system mmu for 2D graphics engine */
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#define EXYNOS4_SMMUSSS_OFFSET 0x00A50000 /* system mmu for SSS */
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#define EXYNOS4_GPIO_RIGHT_OFFSET 0x01000000
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#define EXYNOS4_GPIO_LEFT_OFFSET 0x01400000
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#define EXYNOS4_FIMC0_OFFSET 0x01800000 /* image for display */
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#define EXYNOS4_FIMC1_OFFSET 0x01810000
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#define EXYNOS4_FIMC2_OFFSET 0x01820000
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#define EXYNOS4_FIMC3_OFFSET 0x01830000
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#define EXYNOS4_JPEG_OFFSET 0x01840000 /* JPEG Codec */
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#define EXYNOS4_MIPI_CSI0_OFFSET 0x01880000 /* MIPI-Slim bus Interface */
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#define EXYNOS4_MIPI_CSI1_OFFSET 0x01890000
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#define EXYNOS4_SMMUFIMC0_OFFSET 0x01A20000 /* system mmus */
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#define EXYNOS4_SMMUFIMC1_OFFSET 0x01A30000
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#define EXYNOS4_SMMUFIMC2_OFFSET 0x01A40000
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#define EXYNOS4_SMMUFIMC3_OFFSET 0x01A50000
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#define EXYNOS4_SMMUJPEG_OFFSET 0x01A60000
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#define EXYNOS4_FIMD0_OFFSET 0x01C00000 /* LCD0 */
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#define EXYNOS4_MIPI_DSI0_OFFSET 0x01C80000 /* LCD0 */
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#define EXYNOS4_SMMUFIMD0_OFFSET 0x01E20000 /* system mmus */
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#define EXYNOS4_FIMC_ISP_OFFSET 0x02000000 /* (digital) camera video input */
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#define EXYNOS4_FIMC_DRC_TOP_OFFSET 0x02010000
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#define EXYNOS4_FIMC_FD_TOP_OFFSET 0x02040000
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#define EXYNOS4_MPWM_ISP_OFFSET 0x02110000 /* (specialised?) PWM */
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#define EXYNOS4_I2C0_ISP_OFFSET 0x02130000 /* I2C bus */
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#define EXYNOS4_I2C1_ISP_OFFSET 0x02140000
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#define EXYNOS4_MTCADC_ISP_OFFSET 0x02150000 /* (specialised?) AD Converter */
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#define EXYNOS4_PWM_ISP_OFFSET 0x02160000 /* PWM */
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#define EXYNOS4_WDT_ISP_OFFSET 0x02170000 /* Watch Dog Timer */
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#define EXYNOS4_MCUCTL_ISP_OFFSET 0x02180000 /* XXX unknown XXX */
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#define EXYNOS4_UART_ISP_OFFSET 0x02190000 /* uart base clock */
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#define EXYNOS4_SPI0_ISP_OFFSET 0x021A0000
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#define EXYNOS4_SPI1_ISP_OFFSET 0x021B0000
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#define EXYNOS4_GIC_C_ISP_OFFSET 0x021E0000
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#define EXYNOS4_GIC_D_ISP_OFFSET 0x021F0000
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#define EXYNOS4_SYSMMU_FIMC_ISP_OFFSET 0x02260000
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#define EXYNOS4_SYSMMU_FIMC_DRC_OFFSET 0x02270000
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#define EXYNOS4_SYSMMU_FIMC_FD_OFFSET 0x022A0000
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#define EXYNOS4_SYSMMU_ISPCPU_OFFSET 0x022B0000
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#define EXYNOS4_FIMC_LITE0_OFFSET 0x02390000 /* external image input? */
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#define EXYNOS4_FIMC_LITE1_OFFSET 0x023A0000
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#define EXYNOS4_SYSMMU_FIMC_LITE0_OFFSET 0x023B0000
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#define EXYNOS4_SYSMMU_FIMC_LITE1_OFFSET 0x023C0000
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#define EXYNOS4_USBDEV0_OFFSET 0x02480000 /* XXX unknown XXX */
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#define EXYNOS4_USBDEV0_1_OFFSET 0x02480000
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#define EXYNOS4_USBDEV0_2_OFFSET 0x02490000
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#define EXYNOS4_USBDEV0_3_OFFSET 0x024A0000
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#define EXYNOS4_USBDEV0_4_OFFSET 0x024B0000
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#define EXYNOS4_TSI_OFFSET 0x02500000 /* Transport Stream Interface */
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#define EXYNOS4_SDMMC0_OFFSET 0x02510000 /* SD card interface */
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#define EXYNOS4_SDMMC1_OFFSET 0x02520000
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#define EXYNOS4_SDMMC2_OFFSET 0x02530000
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#define EXYNOS4_SDMMC3_OFFSET 0x02540000
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#define EXYNOS4_SDMMC4_OFFSET 0x02550000
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#define EXYNOS4_MIPI_HSI_OFFSET 0x02560000 /* LCD0 */
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#define EXYNOS4_SROMC_OFFSET 0x02570000
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#define EXYNOS4_USB2HOST_OFFSET 0x02580000
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#define EXYNOS4_USB2_HOST_EHCI_OFFSET 0x02580000
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#define EXYNOS4_USB2_HOST_OHCI_OFFSET 0x02590000
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#define EXYNOS4_USB2_HOST_PHYCTRL_OFFSET 0x025B0000
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#define EXYNOS4_USBOTG1_OFFSET 0x025B0000 /* USB On The Go interface */
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#define EXYNOS4_PDMA0_OFFSET 0x02680000 /* Peripheral DMA */
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#define EXYNOS4_PDMA1_OFFSET 0x02690000
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#define EXYNOS4_GADC_OFFSET 0x026C0000 /* General AD Converter */
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#define EXYNOS4_ROTATOR_OFFSET 0x02810000 /* Image rotator for video output */
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#define EXYNOS4_SMDMA_OFFSET 0x02840000 /* (s) Memory DMA */
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#define EXYNOS4_NSMDMA_OFFSET 0x02850000 /* (ns) Memory DMA */
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#define EXYNOS4_SMMUROTATOR_OFFSET 0x02A30000 /* system mmu for rotator */
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#define EXYNOS4_SMMUMDMA_OFFSET 0x02A40000
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#define EXYNOS4_VP_OFFSET 0x02C00000 /* Video Processor */
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#define EXYNOS4_MIXER_OFFSET 0x02C10000 /* Video mixer */
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#define EXYNOS4_HDMI0_OFFSET 0x02D00000
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#define EXYNOS4_HDMI1_OFFSET 0x02D10000
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#define EXYNOS4_HDMI2_OFFSET 0x02D20000
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#define EXYNOS4_HDMI3_OFFSET 0x02D30000
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#define EXYNOS4_HDMI4_OFFSET 0x02D40000
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#define EXYNOS4_HDMI5_OFFSET 0x02D50000
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#define EXYNOS4_HDMI6_OFFSET 0x02D60000
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#define EXYNOS4_SMMUTV_OFFSET 0x02E20000
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#define EXYNOS4_G3D_OFFSET 0x03000000 /* 3D Graphics Accelerator */
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#define EXYNOS4_PPMU_3D_OFFSET 0x03220000
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#define EXYNOS4_MFC_OFFSET 0x03400000 /* Multi Format Codec */
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#define EXYNOS4_SMMUMFC_L_OFFSET 0x03620000
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#define EXYNOS4_SMMUMFC_R_OFFSET 0x03630000
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#define EXYNOS4_PMMU_MFC_L_OFFSET 0x03660000 /* ? */
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#define EXYNOS4_PMMU_MFC_R_OFFSET 0x03670000 /* ? */
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#define EXYNOS4_UART0_OFFSET 0x03800000 /* serial port 0 */
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#define EXYNOS4_UART1_OFFSET 0x03810000 /* serial port 1 */
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#define EXYNOS4_UART2_OFFSET 0x03820000 /* serial port 2 */
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#define EXYNOS4_UART3_OFFSET 0x03830000 /* serial port 3 */
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#define EXYNOS4_UART4_OFFSET 0x03840000 /* serial port 4 */
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#define EXYNOS4_I2C0_OFFSET 0x03860000 /* Inter Integrated Circuit (I2C) */
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#define EXYNOS4_I2C1_OFFSET 0x03870000 /* Inter Integrated Circuit (I2C) */
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#define EXYNOS4_I2C2_OFFSET 0x03880000 /* Inter Integrated Circuit (I2C) */
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#define EXYNOS4_I2C3_OFFSET 0x03890000 /* Inter Integrated Circuit (I2C) */
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#define EXYNOS4_I2C4_OFFSET 0x038A0000 /* Inter Integrated Circuit (I2C) */
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#define EXYNOS4_I2C5_OFFSET 0x038B0000 /* Inter Integrated Circuit (I2C) */
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#define EXYNOS4_I2C6_OFFSET 0x038C0000 /* Inter Integrated Circuit (I2C) */
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#define EXYNOS4_I2C7_OFFSET 0x038D0000 /* Inter Integrated Circuit (I2C) */
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#define EXYNOS4_I2CHDMI_OFFSET 0x038E0000 /* I2C for HDMI */
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#define EXYNOS4_SPI0_OFFSET 0x03920000 /* Serial Peripheral Interface0 */
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#define EXYNOS4_SPI1_OFFSET 0x03930000 /* Serial Peripheral Interface0 */
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#define EXYNOS4_SPI2_OFFSET 0x03940000 /* Serial Peripheral Interface0 */
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#define EXYNOS4_I2S1_OFFSET 0x03960000 /* sound */
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#define EXYNOS4_I2S2_OFFSET 0x03970000 /* sound */
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#define EXYNOS4_PCM1_OFFSET 0x03980000 /* sound */
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#define EXYNOS4_PCM2_OFFSET 0x03990000 /* sound */
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#define EXYNOS4_AC97_OFFSET 0x039A0000 /* AC97 audio codec sound */
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#define EXYNOS4_SPDIF_OFFSET 0x039B0000 /* SPDIF sound */
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#define EXYNOS4_PWMTIMER_OFFSET 0x039D0000
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/* AUDIOCORE */
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#define EXYNOS4_AUDIOCORE_OFFSET 0x04000000 /* on 1Mb L1 chunk */
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#define EXYNOS4_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS4_AUDIOCORE_OFFSET)
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#define EXYNOS4_AUDIOCORE_PBASE 0x03800000 /* Audio SFR */
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#define EXYNOS4_AUDIOCORE_SIZE 0x00100000
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#define EXYNOS4_GPIO_I2S0_OFFSET (EXYNOS4_AUDIOCORE_OFFSET + 0x00060000)
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/* used Exynos4 USB PHY registers */
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#define USB_PHYPWR 0x00
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#define PHYPWR_FORCE_SUSPEND __BIT(1)
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#define PHYPWR_ANALOG_POWERDOWN __BIT(3)
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#define PHYPWR_OTG_DISABLE __BIT(4)
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#define PHYPWR_SLEEP_PHY0 __BIT(5)
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#define PHYPWR_NORMAL_MASK 0x19
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#define PHYPWR_NORMAL_MASK_PHY0 (__BITS(3,3) | 1)
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#define PHYPWR_NORMAL_MASK_PHY1 __BITS(6,3)
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#define PHYPWR_NORMAL_MASK_HSIC0 __BITS(9,3)
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#define PHYPWR_NORMAL_MASK_HSIC1 __BITS(12,3)
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#define USB_PHYCLK 0x04 /* holds FSEL_CLKSEL_ */
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#define USB_RSTCON 0x08
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#define RSTCON_SWRST __BIT(0)
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#define RSTCON_HLINK_RWRST __BIT(1)
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#define RSTCON_DEVPHYLINK_SWRST __BIT(2)
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#define RSTCON_DEVPHY_SWRST __BITS(0,3)
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#define RSTCON_HOSTPHY_SWRST __BITS(3,4)
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#define RSTCON_HOSTPHYLINK_SWRST __BITS(7,4)
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#endif /* _ARM_SAMSUNG_EXYNOS4_REG_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: exynos_platform.c,v 1.12 2018/08/05 14:02:35 skrll Exp $ */
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/* $NetBSD: exynos_platform.c,v 1.13 2018/08/19 07:27:33 skrll Exp $ */
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/*-
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* Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca>
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@ -34,7 +34,7 @@
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#include "ukbd.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.12 2018/08/05 14:02:35 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.13 2018/08/19 07:27:33 skrll Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
|
||||
|
|
@ -52,37 +52,24 @@ __KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.12 2018/08/05 14:02:35 skrll E
|
|||
#include <arm/samsung/exynos_reg.h>
|
||||
#include <arm/samsung/exynos_var.h>
|
||||
#include <arm/samsung/mct_var.h>
|
||||
#include <arm/samsung/sscom_reg.h>
|
||||
|
||||
#include <evbarm/exynos/platform.h>
|
||||
|
||||
#include <arm/fdt/arm_fdtvar.h>
|
||||
|
||||
void exynos_platform_early_putchar(char);
|
||||
|
||||
#define EXYNOS5_SWRESET_REG 0x10040400
|
||||
|
||||
static const struct pmap_devmap *
|
||||
exynos_platform_devmap(void)
|
||||
{
|
||||
static const struct pmap_devmap devmap[] = {
|
||||
DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
|
||||
EXYNOS_CORE_PBASE,
|
||||
EXYNOS5_CORE_SIZE),
|
||||
DEVMAP_ENTRY(EXYNOS5_AUDIOCORE_VBASE,
|
||||
EXYNOS5_AUDIOCORE_PBASE,
|
||||
EXYNOS5_AUDIOCORE_SIZE),
|
||||
DEVMAP_ENTRY_END
|
||||
};
|
||||
|
||||
return devmap;
|
||||
}
|
||||
|
||||
#define EXYNOS_IOPHYSTOVIRT(a) \
|
||||
((vaddr_t)(((a) - EXYNOS_CORE_PBASE) + EXYNOS_CORE_VBASE))
|
||||
|
||||
static void
|
||||
exynos_platform_bootstrap(void)
|
||||
{
|
||||
paddr_t uart_address = armreg_tpidruro_read(); /* XXX */
|
||||
exynos_bootstrap(EXYNOS_CORE_VBASE, EXYNOS_IOPHYSTOVIRT(uart_address));
|
||||
|
||||
exynos_bootstrap(EXYNOS_CORE_VBASE);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -97,13 +84,21 @@ exynos_platform_init_attach_args(struct fdt_attach_args *faa)
|
|||
faa->faa_dmat = &arm_generic_dma_tag;
|
||||
}
|
||||
|
||||
static void
|
||||
|
||||
void
|
||||
exynos_platform_early_putchar(char c)
|
||||
{
|
||||
#if defined(VERBOSE_INIT_ARM)
|
||||
extern void exynos_putchar(int); /* XXX from exynos_start.S */
|
||||
#ifdef CONSADDR
|
||||
#define CONSADDR_VA (CONSADDR - EXYNOS_CORE_PBASE + EXYNOS_CORE_VBASE)
|
||||
|
||||
exynos_putchar(c);
|
||||
volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
|
||||
(volatile uint32_t *)CONSADDR_VA :
|
||||
(volatile uint32_t *)CONSADDR;
|
||||
|
||||
while ((uartaddr[SSCOM_UFSTAT / 4] & UFSTAT_TXFULL) != 0)
|
||||
;
|
||||
|
||||
uartaddr[SSCOM_UTXH / 4] = c;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -129,8 +124,58 @@ exynos_platform_uart_freq(void)
|
|||
return EXYNOS_UART_FREQ;
|
||||
}
|
||||
|
||||
|
||||
#if defined(SOC_EXYNOS4)
|
||||
static const struct pmap_devmap *
|
||||
exynos4_platform_devmap(void)
|
||||
{
|
||||
static const struct pmap_devmap devmap[] = {
|
||||
DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
|
||||
EXYNOS_CORE_PBASE,
|
||||
EXYNOS4_CORE_SIZE),
|
||||
DEVMAP_ENTRY(EXYNOS4_AUDIOCORE_VBASE,
|
||||
EXYNOS4_AUDIOCORE_PBASE,
|
||||
EXYNOS4_AUDIOCORE_SIZE),
|
||||
DEVMAP_ENTRY_END
|
||||
};
|
||||
|
||||
return devmap;
|
||||
}
|
||||
|
||||
static const struct arm_platform exynos4_platform = {
|
||||
.ap_devmap = exynos4_platform_devmap,
|
||||
.ap_bootstrap = exynos_platform_bootstrap,
|
||||
.ap_init_attach_args = exynos_platform_init_attach_args,
|
||||
.ap_early_putchar = exynos_platform_early_putchar,
|
||||
.ap_device_register = exynos_platform_device_register,
|
||||
.ap_reset = exynos5_platform_reset,
|
||||
.ap_delay = mct_delay,
|
||||
.ap_uart_freq = exynos_platform_uart_freq,
|
||||
};
|
||||
|
||||
ARM_PLATFORM(exynos4, "samsung,exynos4", &exynos4_platform);
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(SOC_EXYNOS5)
|
||||
static const struct pmap_devmap *
|
||||
exynos5_platform_devmap(void)
|
||||
{
|
||||
static const struct pmap_devmap devmap[] = {
|
||||
DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
|
||||
EXYNOS_CORE_PBASE,
|
||||
EXYNOS5_CORE_SIZE),
|
||||
DEVMAP_ENTRY(EXYNOS5_AUDIOCORE_VBASE,
|
||||
EXYNOS5_AUDIOCORE_PBASE,
|
||||
EXYNOS5_AUDIOCORE_SIZE),
|
||||
DEVMAP_ENTRY_END
|
||||
};
|
||||
|
||||
return devmap;
|
||||
}
|
||||
|
||||
static const struct arm_platform exynos5_platform = {
|
||||
.ap_devmap = exynos_platform_devmap,
|
||||
.ap_devmap = exynos5_platform_devmap,
|
||||
.ap_bootstrap = exynos_platform_bootstrap,
|
||||
.ap_init_attach_args = exynos_platform_init_attach_args,
|
||||
.ap_early_putchar = exynos_platform_early_putchar,
|
||||
|
|
@ -141,3 +186,4 @@ static const struct arm_platform exynos5_platform = {
|
|||
};
|
||||
|
||||
ARM_PLATFORM(exynos5, "samsung,exynos5", &exynos5_platform);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: exynos_soc.c,v 1.34 2018/07/31 06:46:25 skrll Exp $ */
|
||||
/* $NetBSD: exynos_soc.c,v 1.35 2018/08/19 07:27:33 skrll Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
#include "opt_exynos.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.34 2018/07/31 06:46:25 skrll Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.35 2018/08/19 07:27:33 skrll Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
|
|
@ -76,6 +76,8 @@ struct cpu_freq {
|
|||
|
||||
|
||||
#ifdef SOC_EXYNOS4
|
||||
int exynos4_l2cc_init(void);
|
||||
|
||||
const struct cpu_freq cpu_freq_settings_exynos4[] = {
|
||||
{ 200, 3, 100, 2},
|
||||
{ 300, 4, 200, 2},
|
||||
|
|
@ -473,7 +475,7 @@ exynos_clocks_bootstrap(void)
|
|||
|
||||
|
||||
void
|
||||
exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase)
|
||||
exynos_bootstrap(vaddr_t iobase)
|
||||
{
|
||||
int error;
|
||||
size_t core_size, audiocore_size;
|
||||
|
|
@ -484,13 +486,6 @@ exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase)
|
|||
bus_addr_t exynos_sysreg_offset;
|
||||
bus_addr_t exynos_cmu_apll_offset;
|
||||
|
||||
/* set up early console so we can use printf() and friends */
|
||||
#ifdef EXYNOS_CONSOLE_EARLY
|
||||
uart_base = (volatile uint8_t *) uartbase;
|
||||
cn_tab = &exynos_earlycons;
|
||||
printf("Exynos early console operational\n\n");
|
||||
#endif
|
||||
|
||||
#ifdef SOC_EXYNOS4
|
||||
core_size = EXYNOS4_CORE_SIZE;
|
||||
audiocore_size = EXYNOS4_AUDIOCORE_SIZE;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: exynos_var.h,v 1.24 2018/07/02 23:54:52 jmcneill Exp $ */
|
||||
/* $NetBSD: exynos_var.h,v 1.25 2018/08/19 07:27:33 skrll Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
|
||||
|
|
@ -143,7 +143,7 @@ extern bus_space_handle_t exynos_pmu_bsh;
|
|||
extern bus_space_handle_t exynos_cmu_bsh;
|
||||
extern bus_space_handle_t exynos_sysreg_bsh;
|
||||
|
||||
extern void exynos_bootstrap(vaddr_t, vaddr_t);
|
||||
extern void exynos_bootstrap(vaddr_t);
|
||||
extern void exynos_dma_bootstrap(psize_t memsize);
|
||||
|
||||
struct exynos_pinctrl_softc;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: files.exynos,v 1.30 2018/07/05 13:11:58 jmcneill Exp $
|
||||
# $NetBSD: files.exynos,v 1.31 2018/08/19 07:27:33 skrll Exp $
|
||||
#
|
||||
# Configuration info for Samsung Exynos SoC ARM Peripherals
|
||||
#
|
||||
|
|
@ -27,7 +27,6 @@ defparam opt_exynos.h CONMODE
|
|||
# Memory size in megabytes
|
||||
defparam opt_exynos.h MEMSIZE
|
||||
defparam opt_exynos.h EXYNOS_WDT_DEFAULT_PERIOD
|
||||
defflag opt_exynos.h EXYNOS_CONSOLE_EARLY
|
||||
|
||||
#
|
||||
defflag opt_exynos.h SOC_EXYNOS4: CPU_CORTEXA9
|
||||
|
|
@ -43,7 +42,7 @@ defflag opt_exynos.h SOC_EXYNOS5420: SOC_EXYNOS5
|
|||
defflag opt_exynos.h SOC_EXYNOS5440: SOC_EXYNOS5
|
||||
defflag opt_exynos.h SOC_EXYNOS5422: SOC_EXYNOS5
|
||||
|
||||
file arch/arm/samsung/exynos_platform.c soc_exynos5
|
||||
file arch/arm/samsung/exynos_platform.c
|
||||
|
||||
# Interrupt combiner
|
||||
device exyointr
|
||||
|
|
@ -58,12 +57,12 @@ file arch/arm/samsung/exynos_rtc.c exynos_rtc
|
|||
# Multi Core timer
|
||||
device mct
|
||||
attach mct at fdt with exyo_mct
|
||||
file arch/arm/samsung/mct.c exyo_mct
|
||||
file arch/arm/samsung/mct.c exyo_mct
|
||||
|
||||
# Watchdog
|
||||
device exyowdt : sysmon_wdog
|
||||
attach exyowdt at fdt with exynos_wdt
|
||||
file arch/arm/samsung/exynos_wdt.c exynos_wdt needs-flag
|
||||
file arch/arm/samsung/exynos_wdt.c exynos_wdt needs-flag
|
||||
|
||||
# UARTs
|
||||
device exuart
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# $NetBSD: EXYNOS,v 1.31 2018/07/14 15:09:41 maxv Exp $
|
||||
# $NetBSD: EXYNOS,v 1.32 2018/08/19 07:27:33 skrll Exp $
|
||||
#
|
||||
# Samsung Exynos SoC kernel
|
||||
#
|
||||
|
|
@ -27,6 +27,10 @@ pseudo-device openfirm # /dev/openfirm
|
|||
#options LOCKDEBUG
|
||||
#options PMAP_DEBUG # Enable pmap_debug_level code
|
||||
#options VERBOSE_INIT_ARM # verbose bootstrapping messages
|
||||
# CONSADDR is required for early init messages from VERBOSE_INIT_ARM.
|
||||
|
||||
# ODROID-XU lite
|
||||
#options EARLYCONS=exynos, CONSADDR=0x12c20000
|
||||
|
||||
makeoptions DEBUG="-g" # compile full symbol table
|
||||
makeoptions COPY_SYMTAB=1
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: exynos_start.S,v 1.6 2018/07/05 13:11:58 jmcneill Exp $ */
|
||||
/* $NetBSD: exynos_start.S,v 1.7 2018/08/19 07:27:33 skrll Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
|
|
@ -36,6 +36,7 @@
|
|||
#include "opt_arm_debug.h"
|
||||
#include "opt_fdt.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
#include <arm/asm.h>
|
||||
#include <arm/armreg.h>
|
||||
#include "assym.h"
|
||||
|
|
@ -45,16 +46,34 @@
|
|||
|
||||
#include <evbarm/exynos/platform.h>
|
||||
|
||||
RCSID("$NetBSD: exynos_start.S,v 1.6 2018/07/05 13:11:58 jmcneill Exp $")
|
||||
RCSID("$NetBSD: exynos_start.S,v 1.7 2018/08/19 07:27:33 skrll Exp $")
|
||||
|
||||
#define XPUTC(n)
|
||||
#define XPUTC2(n)
|
||||
#if defined(KERNEL_BASES_EQUAL)
|
||||
#define CALL(f) bl _C_LABEL(f)
|
||||
#else
|
||||
#define CALL(f) \
|
||||
movw fp, #:lower16:_C_LABEL(f); \
|
||||
movt fp, #:upper16:_C_LABEL(f); \
|
||||
sub fp, fp, #KERNEL_BASE_VOFFSET; \
|
||||
blx fp
|
||||
#endif
|
||||
|
||||
#define PLATFORM_EARLY_PUTCHAR ___CONCAT(EARLYCONS, _platform_early_putchar)
|
||||
|
||||
#if defined(VERBOSE_INIT_ARM) && defined(EARLYCONS)
|
||||
#define XPUTC(n) mov r0, n; CALL(PLATFORM_EARLY_PUTCHAR)
|
||||
#define XPUTC2(n) mov r0, n; bl _C_LABEL(PLATFORM_EARLY_PUTCHAR);
|
||||
#else
|
||||
#define XPUTC(n)
|
||||
#define XPUTC2(n)
|
||||
#endif
|
||||
|
||||
#define INIT_MEMSIZE 128
|
||||
|
||||
#define TEMP_L1_TABLE (KERNEL_BASE - KERNEL_BASE_VOFFSET + INIT_MEMSIZE * L1_S_SIZE - L1_TABLE_SIZE)
|
||||
|
||||
#define MD_CPU_HATCH _C_LABEL(arm_fdt_cpu_hatch)
|
||||
#define TMPSTKSIZE 8192
|
||||
|
||||
/*
|
||||
* Kernel start routine for Exynos 5422 boards running on uboot firmware
|
||||
|
|
@ -73,6 +92,11 @@ _C_LABEL(exynos_start):
|
|||
setend be /* force big endian */
|
||||
#endif
|
||||
|
||||
ldr r10, =KERNEL_BASE_VOFFSET
|
||||
ldr r9, =tmpstk
|
||||
add r9, #TMPSTKSIZE
|
||||
sub sp, r9, r10
|
||||
|
||||
/*
|
||||
* Save any arguments passed to us. If .start is not at
|
||||
* 0x80000000 but .text is, we can't directly use the address that
|
||||
|
|
@ -84,22 +108,41 @@ _C_LABEL(exynos_start):
|
|||
sub r4, r4, #KERNEL_BASE_VOFFSET
|
||||
stmia r4, {r0-r3} // Save the arguments
|
||||
|
||||
mov r4, r0
|
||||
mov r5, r1
|
||||
mov r6, r2
|
||||
mov r7, r3
|
||||
|
||||
XPUTC(#'e')
|
||||
XPUTC(#'x')
|
||||
XPUTC(#'y')
|
||||
XPUTC(#'n')
|
||||
XPUTC(#'o')
|
||||
XPUTC(#'s')
|
||||
|
||||
#ifdef FDT
|
||||
/*
|
||||
* ARM boot protocol has FDT address in r2
|
||||
*/
|
||||
XPUTC(#',')
|
||||
XPUTC(#'f')
|
||||
XPUTC(#'d')
|
||||
XPUTC(#'t')
|
||||
|
||||
movw r4, #:lower16:fdt_addr_r
|
||||
movt r4, #:upper16:fdt_addr_r
|
||||
sub r4, r4, #KERNEL_BASE_VOFFSET
|
||||
str r2, [r4]
|
||||
str r6, [r4]
|
||||
#endif
|
||||
|
||||
XPUTC(#':')
|
||||
|
||||
/* Add DTB PA (1MB) from r2 to MMU init table */
|
||||
movw r3, #:lower16:(L1_S_SIZE - 1) /* align DTB PA to 1M */
|
||||
movt r3, #:upper16:(L1_S_SIZE - 1)
|
||||
bic r0, r2, r3
|
||||
bic r0, r6, r3
|
||||
orr r0, r0, #1 /* 1MB mapping */
|
||||
bic r1, r2, r3
|
||||
bic r1, r6, r3
|
||||
movw r3, #:lower16:(L1_S_PROTO_armv7|L1_S_APv7_KRW|L1_S_CACHEABLE)
|
||||
movt r3, #:upper16:(L1_S_PROTO_armv7|L1_S_APv7_KRW|L1_S_CACHEABLE)
|
||||
orr r1, r1, r3
|
||||
|
|
@ -157,6 +200,8 @@ _C_LABEL(exynos_start):
|
|||
.pushsection .text, "ax", %progbits
|
||||
1:
|
||||
#endif
|
||||
|
||||
exynos_startva:
|
||||
XPUTC2(#'Z')
|
||||
|
||||
XPUTC2(#13)
|
||||
|
|
@ -197,6 +242,7 @@ mmu_init_table:
|
|||
EXYNOS_CORE_SIZE / L1_S_SIZE,
|
||||
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
|
||||
|
||||
#if 0
|
||||
/* Map EXYNOS AUDIOBASE */
|
||||
MMU_INIT(EXYNOS5_AUDIOCORE_VBASE, EXYNOS5_AUDIOCORE_VBASE,
|
||||
EXYNOS5_AUDIOCORE_SIZE / L1_S_SIZE,
|
||||
|
|
@ -216,6 +262,7 @@ mmu_init_table:
|
|||
MMU_INIT(EXYNOS5_SYSRAM_PBASE, EXYNOS5_SYSRAM_PBASE,
|
||||
EXYNOS5_SYSRAM_SIZE / L1_S_SIZE,
|
||||
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
|
||||
#endif
|
||||
|
||||
/* Map DTB location in SDRAM, patched in later */
|
||||
.Lmmu_init_table_dtb:
|
||||
|
|
@ -226,3 +273,12 @@ mmu_init_table:
|
|||
MMU_INIT(0, 0, 0, 0)
|
||||
|
||||
END(exynos_start)
|
||||
|
||||
.bss
|
||||
#ifdef __ARM_EABI__
|
||||
.align 3
|
||||
#endif
|
||||
|
||||
tmpstk:
|
||||
.space TMPSTKSIZE
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue