dd support for the Promise Ultra100TX2, Promise Ultra100TX2v2 and Ultra133
IDE controllers. In part from OpenBSD via ragge, in part from FreeBSD.
This commit is contained in:
bouyer
parent
3b488c3f27
commit
a9f41fe33b
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@ -1,4 +1,4 @@
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/* $NetBSD: pciide.c,v 1.137 2001/12/13 20:57:22 bouyer Exp $ */
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/* $NetBSD: pciide.c,v 1.138 2001/12/16 23:35:52 bouyer Exp $ */
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/*
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@ -77,7 +77,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.137 2001/12/13 20:57:22 bouyer Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.138 2001/12/16 23:35:52 bouyer Exp $");
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#ifndef WDCDEBUG
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#define WDCDEBUG
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@ -192,6 +192,7 @@ static int acer_isabr_match __P(( struct pci_attach_args *));
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void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
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void pdc202xx_setup_channel __P((struct channel_softc*));
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void pdc20268_setup_channel __P((struct channel_softc*));
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int pdc202xx_pci_intr __P((void *));
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int pdc20265_pci_intr __P((void *));
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@ -420,6 +421,21 @@ const struct pciide_product_desc pciide_promise_products[] = {
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"Promise Ultra100/ATA Bus Master IDE Accelerator",
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pdc202xx_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_ULTRA100TX2,
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IDE_PCI_CLASS_OVERRIDE,
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"Promise Ultra100TX2/ATA Bus Master IDE Accelerator",
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pdc202xx_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_ULTRA100TX2v2,
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IDE_PCI_CLASS_OVERRIDE,
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"Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator",
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pdc202xx_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_ULTRA133,
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IDE_PCI_CLASS_OVERRIDE,
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"Promise Ultra133/ATA Bus Master IDE Accelerator",
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pdc202xx_chip_map,
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},
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{ 0,
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0,
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NULL,
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@ -3390,10 +3406,20 @@ hpt_pci_intr(arg)
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#define PDC_IS_262(sc) \
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((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X)
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133)
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#define PDC_IS_265(sc) \
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((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X)
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133)
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#define PDC_IS_268(sc) \
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((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \
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(sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133)
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void
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pdc202xx_chip_map(sc, pa)
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@ -3405,14 +3431,17 @@ pdc202xx_chip_map(sc, pa)
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pcireg_t interface, st, mode;
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bus_size_t cmdsize, ctlsize;
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st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE);
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st),
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DEBUG_PROBE);
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if (!PDC_IS_268(sc)) {
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st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE);
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n",
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st), DEBUG_PROBE);
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}
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if (pciide_chipen(sc, pa) == 0)
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return;
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/* turn off RAID mode */
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st &= ~PDC2xx_STATE_IDERAID;
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if (!PDC_IS_268(sc))
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st &= ~PDC2xx_STATE_IDERAID;
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/*
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* can't rely on the PCI_CLASS_REG content if the chip was in raid
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@ -3441,63 +3470,73 @@ pdc202xx_chip_map(sc, pa)
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sc->sc_wdcdev.UDMA_cap = 4;
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else
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sc->sc_wdcdev.UDMA_cap = 2;
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sc->sc_wdcdev.set_modes = pdc202xx_setup_channel;
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sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ?
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pdc20268_setup_channel : pdc202xx_setup_channel;
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sc->sc_wdcdev.channels = sc->wdc_chanarray;
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sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
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/* setup failsafe defaults */
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mode = 0;
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mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]);
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mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]);
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mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]);
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mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]);
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for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 "
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"initial timings 0x%x, now 0x%x\n", channel,
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pci_conf_read(sc->sc_pc, sc->sc_tag,
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PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp),
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if (!PDC_IS_268(sc)) {
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/* setup failsafe defaults */
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mode = 0;
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mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]);
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mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]);
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mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]);
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mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]);
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for (channel = 0;
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channel < sc->sc_wdcdev.nchannels;
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channel++) {
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d "
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"drive 0 initial timings 0x%x, now 0x%x\n",
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channel, pci_conf_read(sc->sc_pc, sc->sc_tag,
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PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp),
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DEBUG_PROBE);
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pci_conf_write(sc->sc_pc, sc->sc_tag,
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PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp);
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d "
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"drive 1 initial timings 0x%x, now 0x%x\n",
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channel, pci_conf_read(sc->sc_pc, sc->sc_tag,
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PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE);
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pci_conf_write(sc->sc_pc, sc->sc_tag,
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PDC2xx_TIM(channel, 1), mode);
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}
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mode = PDC2xx_SCR_DMA;
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if (PDC_IS_262(sc)) {
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mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT);
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} else {
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/* the BIOS set it up this way */
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mode = PDC2xx_SCR_SET_GEN(mode, 0x1);
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}
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mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */
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mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, "
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"now 0x%x\n",
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bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh,
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PDC2xx_SCR),
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mode), DEBUG_PROBE);
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bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
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PDC2xx_SCR, mode);
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/* controller initial state register is OK even without BIOS */
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/* Set DMA mode to IDE DMA compatibility */
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mode =
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bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM);
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode),
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DEBUG_PROBE);
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pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0),
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mode | PDC2xx_TIM_IORDYp);
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 "
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"initial timings 0x%x, now 0x%x\n", channel,
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pci_conf_read(sc->sc_pc, sc->sc_tag,
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PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE);
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pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1),
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mode);
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bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM,
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mode | 0x1);
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mode =
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bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM);
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WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE);
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bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM,
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mode | 0x1);
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}
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mode = PDC2xx_SCR_DMA;
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if (PDC_IS_262(sc)) {
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mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT);
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} else {
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/* the BIOS set it up this way */
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mode = PDC2xx_SCR_SET_GEN(mode, 0x1);
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}
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mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */
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mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n",
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bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode),
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DEBUG_PROBE);
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bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode);
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/* controller initial state register is OK even without BIOS */
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/* Set DMA mode to IDE DMA compatibility */
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mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM);
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ),
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DEBUG_PROBE);
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bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM,
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mode | 0x1);
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mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM);
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WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE);
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bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM,
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mode | 0x1);
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for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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if ((st & (PDC_IS_262(sc) ?
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if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ?
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PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) {
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printf("%s: %s channel ignored (disabled)\n",
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sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
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@ -3511,15 +3550,17 @@ pdc202xx_chip_map(sc, pa)
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pdc202xx_pci_intr);
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if (cp->hw_ok == 0)
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continue;
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if (pciide_chan_candisable(cp))
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if (!PDC_IS_268(sc) && pciide_chan_candisable(cp))
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st &= ~(PDC_IS_262(sc) ?
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PDC262_STATE_EN(channel):PDC246_STATE_EN(channel));
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pciide_map_compat_intr(pa, cp, channel, interface);
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pdc202xx_setup_channel(&cp->wdc_channel);
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}
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st),
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DEBUG_PROBE);
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pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st);
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if (!PDC_IS_268(sc)) {
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WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state "
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"0x%x\n", st), DEBUG_PROBE);
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pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st);
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}
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return;
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}
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@ -3640,6 +3681,57 @@ pdc202xx_setup_channel(chp)
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pciide_print_modes(cp);
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}
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void
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pdc20268_setup_channel(chp)
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struct channel_softc *chp;
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{
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struct ata_drive_datas *drvp;
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int drive;
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u_int32_t idedma_ctl;
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struct pciide_channel *cp = (struct pciide_channel*)chp;
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struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
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int u100;
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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idedma_ctl = 0;
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/* I don't know what this is for, FreeBSD does it ... */
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bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
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IDEDMA_CMD + 0x1, 0x0b);
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/*
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* I don't know what this is for; FreeBSD checks this ... this is not
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* cable type detect.
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*/
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u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
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IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1;
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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if (drvp->drive_flags & DRIVE_UDMA) {
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/* use Ultra/DMA */
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drvp->drive_flags &= ~DRIVE_DMA;
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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if (drvp->UDMA_mode > 2 && u100 == 0)
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drvp->UDMA_mode = 2;
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} else if (drvp->drive_flags & DRIVE_DMA) {
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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}
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}
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/* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */
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if (idedma_ctl != 0) {
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/* Add software bits in status register */
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bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
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IDEDMA_CTL, idedma_ctl);
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}
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pciide_print_modes(cp);
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}
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int
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pdc202xx_pci_intr(arg)
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void *arg;
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