* Include sys/proc.h, sys/fcntl.h and machine/conf.h to get some missing
prototypes. * Get rid of RTC_DEV. All rtc support now lives in clock.c.
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@ -1,4 +1,4 @@
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/* $NetBSD: mem.c,v 1.13 1995/09/26 20:16:30 phil Exp $ */
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/* $NetBSD: mem.c,v 1.14 1997/03/20 12:00:56 matthias Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -45,105 +45,38 @@
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*/
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/buf.h>
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#include <sys/systm.h>
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#include <sys/uio.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <sys/fcntl.h>
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#include <machine/cpu.h>
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#include <machine/conf.h>
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#include <vm/vm.h>
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extern char *vmmap; /* poor name! */
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caddr_t zeropage;
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#ifndef NO_RTC
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int have_rtc = 1; /* For access to rtc. */
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#else
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int have_rtc = 0; /* For no rtc. */
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#endif
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#define ROM_ORIGIN 0xFFF00000 /* Mapped origin! */
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/* Do the actual reading and writing of the rtc. We have to read
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and write the entire contents at a time. rw = 0 => read,
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rw = 1 => write. */
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void rw_rtc (unsigned char *buffer, int rw)
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{
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static unsigned char magic[8] =
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{0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c};
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volatile unsigned char * const rom_p = (unsigned char *)ROM_ORIGIN;
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unsigned char *bp;
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unsigned char dummy; /* To defeat optimization */
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/* Read or write to the real time chip. Address line A0 functions as
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* data input, A2 is used as the /write signal. Accesses to the RTC
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* are always done to one of the addresses (unmapped):
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*
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* 0x10000000 - write a '0' bit
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* 0x10000001 - write a '1' bit
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* 0x10000004 - read a bit
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*
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* Data is output from the RTC using D0. To read or write time
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* information, the chip has to be activated first, to distinguish
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* clock accesses from normal ROM reads. This is done by writing,
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* bit by bit, a magic pattern to the chip. Before that, a dummy read
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* assures that the chip's pattern comparison register pointer is
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* reset. The RTC register file is always read or written wholly,
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* even if we are only interested in a part of it.
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*/
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/* Activate the real time chip */
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dummy = rom_p[4]; /* Synchronize the comparison reg. */
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for (bp=magic; bp<magic+8; bp++) {
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int i;
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for (i=0; i<8; i++)
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dummy = rom_p[ (*bp>>i) & 0x01 ];
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}
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if (rw == 0) {
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/* Read the time from the RTC. Do this even this is
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a write, since the user might have only given
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partial data and the RTC must always be written
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completely.
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*/
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for (bp=buffer; bp<buffer+8; bp++) {
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int i;
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for (i=0; i<8; i++) {
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*bp >>= 1;
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*bp |= ((rom_p[4] & 0x01) ? 0x80 : 0x00);
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}
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}
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} else {
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/* Write to the RTC */
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for (bp=buffer; bp<buffer+8; bp++) {
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int i;
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for (i=0; i<8; i++)
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dummy = rom_p[ (*bp>>i) & 0x01 ];
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}
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}
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}
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/*ARGSUSED*/
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int
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mmopen(dev, flag, mode)
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mmopen(dev, flag, mode, p)
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dev_t dev;
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int flag, mode;
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struct proc *p;
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{
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return (0);
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}
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/*ARGSUSED*/
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int
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mmclose(dev, flag, mode)
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mmclose(dev, flag, mode, p)
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dev_t dev;
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int flag, mode;
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struct proc *p;
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{
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return (0);
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}
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@ -159,8 +92,6 @@ mmrw(dev, uio, flags)
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register struct iovec *iov;
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int error = 0;
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static int physlock;
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/* /dev/rtc support. */
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unsigned char buffer[8];
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if (minor(dev) == 0) {
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/* lock against other uses of shared vmmap */
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@ -213,32 +144,6 @@ mmrw(dev, uio, flags)
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uio->uio_resid = 0;
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return (0);
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#ifdef DEV_RTC
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/* minor device 3 is the realtime clock. */
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case 3:
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if (!have_rtc)
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return (ENXIO);
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/* Calc offsets and lengths. */
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v = uio->uio_offset;
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if (v > 8)
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return (0); /* EOF */
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c = iov->iov_len;
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if (v+c > 8)
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c = 8-v;
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rw_rtc(buffer, 0); /* Read the rtc. */
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error = uiomove((caddr_t)&buffer[v], c, uio);
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if (uio->uio_rw == UIO_READ || error)
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return (error);
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rw_rtc(buffer, 1); /* Write the rtc. */
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return (error);
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#endif
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/* minor device 12 (/dev/zero) is source of nulls on read, rathole on write */
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case 12:
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if (uio->uio_rw == UIO_WRITE) {
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@ -265,7 +170,6 @@ mmrw(dev, uio, flags)
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uio->uio_resid -= c;
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}
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if (minor(dev) == 0) {
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unlock:
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if (physlock > 1)
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wakeup((caddr_t)&physlock);
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physlock = 0;
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@ -278,6 +182,5 @@ mmmmap(dev, off, prot)
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dev_t dev;
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int off, prot;
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{
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return (EOPNOTSUPP);
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}
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